macro-assembler-aarch32.h revision 9ee25b5df54608e45947a7f99f2c23ce61802474
1// Copyright 2015, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright 10// notice, this list of conditions and the following disclaimer in the 11// documentation and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may 13// be used to endorse or promote products derived from this software 14// without specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26// POSSIBILITY OF SUCH DAMAGE. 27 28#ifndef VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 29#define VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 30 31#include "code-generation-scopes-vixl.h" 32#include "macro-assembler-interface.h" 33#include "utils-vixl.h" 34 35#include "aarch32/instructions-aarch32.h" 36#include "aarch32/assembler-aarch32.h" 37#include "aarch32/operands-aarch32.h" 38 39namespace vixl { 40namespace aarch32 { 41 42class JumpTableBase; 43 44enum FlagsUpdate { LeaveFlags = 0, SetFlags = 1, DontCare = 2 }; 45 46// LiteralPool class, defined as a container for literals 47class LiteralPool { 48 public: 49 typedef std::list<RawLiteral*>::iterator RawLiteralListIterator; 50 51 public: 52 LiteralPool() : size_(0) {} 53 ~LiteralPool() { 54 VIXL_ASSERT(literals_.empty() && (size_ == 0)); 55 for (RawLiteralListIterator literal_it = keep_until_delete_.begin(); 56 literal_it != keep_until_delete_.end(); 57 literal_it++) { 58 delete *literal_it; 59 } 60 keep_until_delete_.clear(); 61 } 62 63 unsigned GetSize() const { return size_; } 64 65 // Add a literal to the literal container. 66 void AddLiteral(RawLiteral* literal) { 67 // Manually placed literals can't be added to a literal pool. 68 VIXL_ASSERT(!literal->IsManuallyPlaced()); 69 if (literal->GetPositionInPool() == Label::kMaxOffset) { 70 uint32_t position = GetSize(); 71 literal->SetPositionInPool(position); 72 literals_.push_back(literal); 73 size_ += literal->GetAlignedSize(); 74 } 75 } 76 77 // First literal to be emitted. 78 RawLiteralListIterator GetFirst() { return literals_.begin(); } 79 80 // Mark the end of the literal container. 81 RawLiteralListIterator GetEnd() { return literals_.end(); } 82 83 // Remove all the literals from the container. 84 // If the literal's memory management has been delegated to the container 85 // it will be delete'd. 86 void Clear() { 87 for (RawLiteralListIterator literal_it = GetFirst(); literal_it != GetEnd(); 88 literal_it++) { 89 RawLiteral* literal = *literal_it; 90 switch (literal->GetDeletionPolicy()) { 91 case RawLiteral::kDeletedOnPlacementByPool: 92 delete literal; 93 break; 94 case RawLiteral::kDeletedOnPoolDestruction: 95 keep_until_delete_.push_back(literal); 96 break; 97 case RawLiteral::kManuallyDeleted: 98 break; 99 } 100 } 101 literals_.clear(); 102 size_ = 0; 103 } 104 105 private: 106 // Size (in bytes and including alignments) of the literal pool. 107 unsigned size_; 108 109 // Literal container. 110 std::list<RawLiteral*> literals_; 111 // Already bound Literal container the app requested this pool to keep. 112 std::list<RawLiteral*> keep_until_delete_; 113}; 114 115 116// Macro assembler for aarch32 instruction set. 117class MacroAssembler : public Assembler, public MacroAssemblerInterface { 118 public: 119 enum EmitOption { kBranchRequired, kNoBranchRequired }; 120 121 virtual AssemblerBase* AsAssemblerBase() VIXL_OVERRIDE { return this; } 122 123 virtual void BlockPools() VIXL_OVERRIDE { 124 literal_pool_manager_.Block(); 125 veneer_pool_manager_.Block(); 126 } 127 virtual void ReleasePools() VIXL_OVERRIDE { 128 literal_pool_manager_.Release(); 129 veneer_pool_manager_.Release(); 130 } 131 virtual void EnsureEmitPoolsFor(size_t size) VIXL_OVERRIDE { 132 // TODO: Optimise this. It also checks that there is space in the buffer, 133 // which we do not need to do here. 134 VIXL_ASSERT(IsUint32(size)); 135 EnsureEmitFor(static_cast<uint32_t>(size)); 136 } 137 138 private: 139 class MacroEmissionCheckScope : public EmissionCheckScope { 140 public: 141 explicit MacroEmissionCheckScope(MacroAssemblerInterface* masm) 142 : EmissionCheckScope(masm, kTypicalMacroInstructionMaxSize) {} 143 144 private: 145 static const size_t kTypicalMacroInstructionMaxSize = 146 8 * kMaxInstructionSizeInBytes; 147 }; 148 149 class MacroAssemblerContext { 150 public: 151 MacroAssemblerContext() : count_(0) {} 152 ~MacroAssemblerContext() {} 153 unsigned GetRecursiveCount() const { return count_; } 154 void Up(const char* loc) { 155 location_stack_[count_] = loc; 156 count_++; 157 if (count_ >= kMaxRecursion) { 158 printf( 159 "Recursion limit reached; unable to resolve macro assembler " 160 "call.\n"); 161 printf("Macro assembler context stack:\n"); 162 for (unsigned i = 0; i < kMaxRecursion; i++) { 163 printf("%10s %s\n", (i == 0) ? "oldest -> " : "", location_stack_[i]); 164 } 165 VIXL_ABORT(); 166 } 167 } 168 void Down() { 169 VIXL_ASSERT((count_ > 0) && (count_ < kMaxRecursion)); 170 count_--; 171 } 172 173 private: 174 unsigned count_; 175 static const uint32_t kMaxRecursion = 5; 176 const char* location_stack_[kMaxRecursion]; 177 }; 178 179 // This scope is used at each Delegate entry to avoid infinite recursion of 180 // Delegate calls. The limit is defined by 181 // MacroAssemblerContext::kMaxRecursion. 182 class ContextScope { 183 public: 184 explicit ContextScope(MacroAssembler* const masm, const char* loc) 185 : masm_(masm) { 186 VIXL_ASSERT(masm_->AllowMacroInstructions()); 187 masm_->GetContext()->Up(loc); 188 } 189 ~ContextScope() { masm_->GetContext()->Down(); } 190 191 private: 192 MacroAssembler* const masm_; 193 }; 194 195 MacroAssemblerContext* GetContext() { return &context_; } 196 197 class ITScope { 198 public: 199 ITScope(MacroAssembler* masm, Condition* cond, bool can_use_it = false) 200 : masm_(masm), cond_(*cond), can_use_it_(can_use_it) { 201 if (!cond_.Is(al) && masm->IsUsingT32()) { 202 if (can_use_it_) { 203 // IT is not deprecated (that implies a 16 bit T32 instruction). 204 // We generate an IT instruction and a conditional instruction. 205 masm->it(cond_); 206 } else { 207 // The usage of IT is deprecated for the instruction. 208 // We generate a conditional branch and an unconditional instruction. 209 // TODO: Use a scope utility with a size check. To do that, we'd need 210 // one with Open() and Close() implemented. 211 masm_->EnsureEmitFor(k16BitT32InstructionSizeInBytes + 212 kMaxT32MacroInstructionSizeInBytes); 213 // Generate the branch. 214 masm_->b(cond_.Negate(), Narrow, &label_); 215 // Tell the macro-assembler to generate unconditional instructions. 216 *cond = al; 217 } 218 } 219#ifdef VIXL_DEBUG 220 initial_cursor_offset_ = masm->GetCursorOffset(); 221#else 222 USE(initial_cursor_offset_); 223#endif 224 } 225 ~ITScope() { 226 if (!cond_.Is(al) && masm_->IsUsingT32() && !can_use_it_) { 227 VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <= 228 kMaxT32MacroInstructionSizeInBytes); 229 masm_->BindHelper(&label_); 230 } 231 } 232 233 private: 234 MacroAssembler* masm_; 235 Condition cond_; 236 Label label_; 237 bool can_use_it_; 238 uint32_t initial_cursor_offset_; 239 }; 240 241 template <Assembler::InstructionCondDtDL asmfn> 242 class EmitLiteralCondDtDL { 243 public: 244 EmitLiteralCondDtDL(Condition cond, DataType dt, DRegister rt) 245 : cond_(cond), dt_(dt), rt_(rt) {} 246 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 247 (masm->*asmfn)(cond_, dt_, rt_, literal); 248 } 249 250 private: 251 Condition cond_; 252 DataType dt_; 253 DRegister rt_; 254 }; 255 256 template <Assembler::InstructionCondDtSL asmfn> 257 class EmitLiteralCondDtSL { 258 public: 259 EmitLiteralCondDtSL(Condition cond, DataType dt, SRegister rt) 260 : cond_(cond), dt_(dt), rt_(rt) {} 261 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 262 (masm->*asmfn)(cond_, dt_, rt_, literal); 263 } 264 265 private: 266 Condition cond_; 267 DataType dt_; 268 SRegister rt_; 269 }; 270 271 template <Assembler::InstructionCondRL asmfn> 272 class EmitLiteralCondRL { 273 public: 274 EmitLiteralCondRL(Condition cond, Register rt) : cond_(cond), rt_(rt) {} 275 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 276 (masm->*asmfn)(cond_, rt_, literal); 277 } 278 279 private: 280 Condition cond_; 281 Register rt_; 282 }; 283 284 template <Assembler::InstructionCondRRL asmfn> 285 class EmitLiteralCondRRL { 286 public: 287 EmitLiteralCondRRL(Condition cond, Register rt, Register rt2) 288 : cond_(cond), rt_(rt), rt2_(rt2) {} 289 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 290 (masm->*asmfn)(cond_, rt_, rt2_, literal); 291 } 292 293 private: 294 Condition cond_; 295 Register rt_, rt2_; 296 }; 297 298 class LiteralPoolManager { 299 public: 300 explicit LiteralPoolManager(MacroAssembler* const masm) 301 : masm_(masm), monitor_(0) { 302 ResetCheckpoint(); 303 } 304 305 void ResetCheckpoint() { checkpoint_ = Label::kMaxOffset; } 306 307 LiteralPool* GetLiteralPool() { return &literal_pool_; } 308 Label::Offset GetCheckpoint() const { 309 // Make room for a branch over the pools. 310 return checkpoint_ - kMaxInstructionSizeInBytes; 311 } 312 size_t GetLiteralPoolSize() const { return literal_pool_.GetSize(); } 313 314 // Checks if the insertion of the literal will put the forward reference 315 // too far in the literal pool. 316 bool IsInsertTooFar(RawLiteral* literal, uint32_t from) const { 317 uint32_t checkpoint = from + literal->GetLastInsertForwardDistance(); 318 checkpoint = 319 std::min(checkpoint, static_cast<uint32_t>(literal->GetCheckpoint())); 320 bool too_far = AlignDown(checkpoint, 4) < from + literal_pool_.GetSize() + 321 kMaxInstructionSizeInBytes; 322 return too_far; 323 } 324 325 // Set the different checkpoints where the literal pool has to be emited. 326 void UpdateCheckpoint(RawLiteral* literal) { 327 // The literal should have been placed somewhere in the literal pool 328 VIXL_ASSERT(literal->GetPositionInPool() != Label::kMaxOffset); 329 // TODO(all): Consider AddForwardRef as a virtual so the checkpoint is 330 // updated when inserted. Or move checkpoint_ into Label, 331 literal->UpdateCheckpoint(); 332 Label::Offset tmp = 333 literal->GetAlignedCheckpoint(4) - literal->GetPositionInPool(); 334 if (checkpoint_ > tmp) { 335 checkpoint_ = tmp; 336 masm_->ComputeCheckpoint(); 337 } 338 } 339 340 bool IsEmpty() const { return GetLiteralPoolSize() == 0; } 341 342 void Block() { monitor_++; } 343 void Release() { 344 VIXL_ASSERT(IsBlocked()); 345 if (--monitor_ == 0) { 346 // Ensure the pool has not been blocked for too long. 347 VIXL_ASSERT(masm_->GetCursorOffset() <= checkpoint_); 348 } 349 } 350 bool IsBlocked() const { return monitor_ != 0; } 351 352 private: 353 MacroAssembler* const masm_; 354 LiteralPool literal_pool_; 355 356 // Max offset in the code buffer where the literal needs to be 357 // emitted. A default value of Label::kMaxOffset means that the checkpoint 358 // is invalid. 359 Label::Offset checkpoint_; 360 // Indicates whether the emission of this pool is blocked. 361 int monitor_; 362 }; 363 364 void PerformEnsureEmit(Label::Offset target, uint32_t extra_size); 365 366 protected: 367 void HandleOutOfBoundsImmediate(Condition cond, Register tmp, uint32_t imm); 368 void PadToMinimumBranchRange(Label* label); 369 370 // Generate the instruction and if it's not possible revert the whole thing. 371 // emit the literal pool and regenerate the instruction. 372 // Note: The instruction is generated via 373 // void T::emit(MacroAssembler* const, RawLiteral* const) 374 template <typename T> 375 void GenerateInstruction(T instr_callback, RawLiteral* const literal) { 376 int32_t cursor = GetCursorOffset(); 377 uint32_t where = cursor + GetArchitectureStatePCOffset(); 378 // Emit the instruction, via the assembler 379 { 380 MacroEmissionCheckScope guard(this); 381 instr_callback.emit(this, literal); 382 } 383 if (!literal->IsManuallyPlaced()) { 384 if (IsInsertTooFar(literal, where)) { 385 // The instruction's data is too far: revert the emission 386 GetBuffer()->Rewind(cursor); 387 literal->InvalidateLastForwardReference(RawLiteral::kNoUpdateNecessary); 388 EmitLiteralPool(kBranchRequired); 389 MacroEmissionCheckScope guard(this); 390 instr_callback.emit(this, literal); 391 } 392 literal_pool_manager_.GetLiteralPool()->AddLiteral(literal); 393 literal_pool_manager_.UpdateCheckpoint(literal); 394 } 395 } 396 397 public: 398 explicit MacroAssembler(InstructionSet isa = A32) 399 : Assembler(isa), 400 available_(r12), 401 checkpoint_(Label::kMaxOffset), 402 literal_pool_manager_(this), 403 veneer_pool_manager_(this), 404 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) { 405#ifdef VIXL_DEBUG 406 SetAllowMacroInstructions(true); 407#else 408 USE(literal_pool_manager_); 409 USE(allow_macro_instructions_); 410#endif 411 ComputeCheckpoint(); 412 } 413 explicit MacroAssembler(size_t size, InstructionSet isa = A32) 414 : Assembler(size, isa), 415 available_(r12), 416 checkpoint_(Label::kMaxOffset), 417 literal_pool_manager_(this), 418 veneer_pool_manager_(this), 419 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) { 420#ifdef VIXL_DEBUG 421 SetAllowMacroInstructions(true); 422#endif 423 ComputeCheckpoint(); 424 } 425 MacroAssembler(byte* buffer, size_t size, InstructionSet isa = A32) 426 : Assembler(buffer, size, isa), 427 available_(r12), 428 checkpoint_(Label::kMaxOffset), 429 literal_pool_manager_(this), 430 veneer_pool_manager_(this), 431 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) { 432#ifdef VIXL_DEBUG 433 SetAllowMacroInstructions(true); 434#endif 435 ComputeCheckpoint(); 436 } 437 438 bool GenerateSimulatorCode() const { return generate_simulator_code_; } 439 440#ifdef VIXL_DEBUG 441 // Tell whether any of the macro instruction can be used. When false the 442 // MacroAssembler will assert if a method which can emit a variable number 443 // of instructions is called. 444 void SetAllowMacroInstructions(bool value) VIXL_OVERRIDE { 445 allow_macro_instructions_ = value; 446 } 447 bool AllowMacroInstructions() const VIXL_OVERRIDE { 448 return allow_macro_instructions_; 449 } 450#endif 451 452 void FinalizeCode() { 453 EmitLiteralPool(kNoBranchRequired); 454 Assembler::FinalizeCode(); 455 } 456 457 RegisterList* GetScratchRegisterList() { return &available_; } 458 VRegisterList* GetScratchVRegisterList() { return &available_vfp_; } 459 460 // State and type helpers. 461 bool IsModifiedImmediate(uint32_t imm) { 462 return (IsUsingT32() && ImmediateT32(imm).IsValid()) || 463 ImmediateA32(imm).IsValid(); 464 } 465 466 void Bind(Label* label) { 467 VIXL_ASSERT(allow_macro_instructions_); 468 PadToMinimumBranchRange(label); 469 BindHelper(label); 470 } 471 472 void AddBranchLabel(Label* label) { 473 if (label->IsBound()) return; 474 veneer_pool_manager_.AddLabel(label); 475 } 476 477 void Place(RawLiteral* literal) { 478 VIXL_ASSERT(allow_macro_instructions_); 479 VIXL_ASSERT(literal->IsManuallyPlaced()); 480 // We have two calls to `GetBuffer()->Align()` below, that aligns on word 481 // (4 bytes) boundaries. Only one is taken into account in 482 // `GetAlignedSize()`. 483 static const size_t kMaxAlignSize = 3; 484 size_t size = literal->GetAlignedSize() + kMaxAlignSize; 485 VIXL_ASSERT(IsUint32(size)); 486 // TODO: We should use a scope here to check the size of data emitted. We 487 // currently cannot because `aarch32::CodeBufferCheckScope` currently checks 488 // for pools, so that could lead to an infinite loop. 489 EnsureEmitFor(static_cast<uint32_t>(size)); 490 // Literals must be emitted aligned on word (4 bytes) boundaries. 491 GetBuffer()->Align(); 492 PlaceHelper(literal); 493 GetBuffer()->Align(); 494 } 495 496 void ComputeCheckpoint(); 497 498 int32_t GetMarginBeforeVeneerEmission() const { 499 return veneer_pool_manager_.GetCheckpoint() - GetCursorOffset(); 500 } 501 502 int32_t GetMarginBeforeLiteralEmission() const { 503 return literal_pool_manager_.GetCheckpoint() - GetCursorOffset(); 504 } 505 506 bool VeneerPoolIsEmpty() const { return veneer_pool_manager_.IsEmpty(); } 507 bool LiteralPoolIsEmpty() const { return literal_pool_manager_.IsEmpty(); } 508 509 void EnsureEmitFor(uint32_t size) { 510 Label::Offset target = GetCursorOffset() + size; 511 if (target <= checkpoint_) return; 512 PerformEnsureEmit(target, size); 513 } 514 515 bool IsInsertTooFar(RawLiteral* literal, uint32_t where) { 516 return literal_pool_manager_.IsInsertTooFar(literal, where); 517 } 518 519 bool AliasesAvailableScratchRegister(Register reg) { 520 return GetScratchRegisterList()->Includes(reg); 521 } 522 523 bool AliasesAvailableScratchRegister(RegisterOrAPSR_nzcv reg) { 524 if (reg.IsAPSR_nzcv()) return false; 525 return GetScratchRegisterList()->Includes(reg.AsRegister()); 526 } 527 528 bool AliasesAvailableScratchRegister(VRegister reg) { 529 return GetScratchVRegisterList()->IncludesAliasOf(reg); 530 } 531 532 bool AliasesAvailableScratchRegister(const Operand& operand) { 533 if (operand.IsImmediate()) return false; 534 return AliasesAvailableScratchRegister(operand.GetBaseRegister()) || 535 (operand.IsRegisterShiftedRegister() && 536 AliasesAvailableScratchRegister(operand.GetShiftRegister())); 537 } 538 539 bool AliasesAvailableScratchRegister(const NeonOperand& operand) { 540 if (operand.IsImmediate()) return false; 541 return AliasesAvailableScratchRegister(operand.GetRegister()); 542 } 543 544 bool AliasesAvailableScratchRegister(SRegisterList list) { 545 for (int n = 0; n < list.GetLength(); n++) { 546 if (AliasesAvailableScratchRegister(list.GetSRegister(n))) return true; 547 } 548 return false; 549 } 550 551 bool AliasesAvailableScratchRegister(DRegisterList list) { 552 for (int n = 0; n < list.GetLength(); n++) { 553 if (AliasesAvailableScratchRegister(list.GetDRegister(n))) return true; 554 } 555 return false; 556 } 557 558 bool AliasesAvailableScratchRegister(NeonRegisterList list) { 559 for (int n = 0; n < list.GetLength(); n++) { 560 if (AliasesAvailableScratchRegister(list.GetDRegister(n))) return true; 561 } 562 return false; 563 } 564 565 bool AliasesAvailableScratchRegister(RegisterList list) { 566 return GetScratchRegisterList()->Overlaps(list); 567 } 568 569 bool AliasesAvailableScratchRegister(const MemOperand& operand) { 570 return AliasesAvailableScratchRegister(operand.GetBaseRegister()) || 571 (operand.IsShiftedRegister() && 572 AliasesAvailableScratchRegister(operand.GetOffsetRegister())); 573 } 574 575 // Emit the literal pool in the code buffer. 576 // Every literal is placed on a 32bit boundary 577 // All the literals in the pool will be removed from the pool and potentially 578 // delete'd. 579 void EmitLiteralPool(LiteralPool* const literal_pool, EmitOption option); 580 void EmitLiteralPool(EmitOption option = kBranchRequired) { 581 VIXL_ASSERT(!literal_pool_manager_.IsBlocked()); 582 EmitLiteralPool(literal_pool_manager_.GetLiteralPool(), option); 583 literal_pool_manager_.ResetCheckpoint(); 584 ComputeCheckpoint(); 585 } 586 587 size_t GetLiteralPoolSize() const { 588 return literal_pool_manager_.GetLiteralPoolSize(); 589 } 590 591 // Adr with a literal already constructed. Add the literal to the pool if it 592 // is not already done. 593 void Adr(Condition cond, Register rd, RawLiteral* literal) { 594 EmitLiteralCondRL<&Assembler::adr> emit_helper(cond, rd); 595 GenerateInstruction(emit_helper, literal); 596 } 597 void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); } 598 599 // Loads with literals already constructed. Add the literal to the pool 600 // if it is not already done. 601 void Ldr(Condition cond, Register rt, RawLiteral* literal) { 602 EmitLiteralCondRL<&Assembler::ldr> emit_helper(cond, rt); 603 GenerateInstruction(emit_helper, literal); 604 } 605 void Ldr(Register rt, RawLiteral* literal) { Ldr(al, rt, literal); } 606 607 void Ldrb(Condition cond, Register rt, RawLiteral* literal) { 608 EmitLiteralCondRL<&Assembler::ldrb> emit_helper(cond, rt); 609 GenerateInstruction(emit_helper, literal); 610 } 611 void Ldrb(Register rt, RawLiteral* literal) { Ldrb(al, rt, literal); } 612 613 void Ldrd(Condition cond, Register rt, Register rt2, RawLiteral* literal) { 614 EmitLiteralCondRRL<&Assembler::ldrd> emit_helper(cond, rt, rt2); 615 GenerateInstruction(emit_helper, literal); 616 } 617 void Ldrd(Register rt, Register rt2, RawLiteral* literal) { 618 Ldrd(al, rt, rt2, literal); 619 } 620 621 void Ldrh(Condition cond, Register rt, RawLiteral* literal) { 622 EmitLiteralCondRL<&Assembler::ldrh> emit_helper(cond, rt); 623 GenerateInstruction(emit_helper, literal); 624 } 625 void Ldrh(Register rt, RawLiteral* literal) { Ldrh(al, rt, literal); } 626 627 void Ldrsb(Condition cond, Register rt, RawLiteral* literal) { 628 EmitLiteralCondRL<&Assembler::ldrsb> emit_helper(cond, rt); 629 GenerateInstruction(emit_helper, literal); 630 } 631 void Ldrsb(Register rt, RawLiteral* literal) { Ldrsb(al, rt, literal); } 632 633 void Ldrsh(Condition cond, Register rt, RawLiteral* literal) { 634 EmitLiteralCondRL<&Assembler::ldrsh> emit_helper(cond, rt); 635 GenerateInstruction(emit_helper, literal); 636 } 637 void Ldrsh(Register rt, RawLiteral* literal) { Ldrsh(al, rt, literal); } 638 639 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) { 640 EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(cond, dt, rd); 641 GenerateInstruction(emit_helper, literal); 642 } 643 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) { 644 Vldr(al, dt, rd, literal); 645 } 646 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) { 647 Vldr(cond, Untyped64, rd, literal); 648 } 649 void Vldr(DRegister rd, RawLiteral* literal) { 650 Vldr(al, Untyped64, rd, literal); 651 } 652 653 void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) { 654 EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(cond, dt, rd); 655 GenerateInstruction(emit_helper, literal); 656 } 657 void Vldr(DataType dt, SRegister rd, RawLiteral* literal) { 658 Vldr(al, dt, rd, literal); 659 } 660 void Vldr(Condition cond, SRegister rd, RawLiteral* literal) { 661 Vldr(cond, Untyped32, rd, literal); 662 } 663 void Vldr(SRegister rd, RawLiteral* literal) { 664 Vldr(al, Untyped32, rd, literal); 665 } 666 667 // Generic Ldr(register, data) 668 void Ldr(Condition cond, Register rt, uint32_t v) { 669 RawLiteral* literal = 670 new Literal<uint32_t>(v, RawLiteral::kDeletedOnPlacementByPool); 671 EmitLiteralCondRL<&Assembler::ldr> emit_helper(cond, rt); 672 GenerateInstruction(emit_helper, literal); 673 } 674 template <typename T> 675 void Ldr(Register rt, T v) { 676 Ldr(al, rt, v); 677 } 678 679 // Generic Ldrd(rt, rt2, data) 680 void Ldrd(Condition cond, Register rt, Register rt2, uint64_t v) { 681 RawLiteral* literal = 682 new Literal<uint64_t>(v, RawLiteral::kDeletedOnPlacementByPool); 683 EmitLiteralCondRRL<&Assembler::ldrd> emit_helper(cond, rt, rt2); 684 GenerateInstruction(emit_helper, literal); 685 } 686 template <typename T> 687 void Ldrd(Register rt, Register rt2, T v) { 688 Ldrd(al, rt, rt2, v); 689 } 690 691 void Vldr(Condition cond, SRegister rd, float v) { 692 RawLiteral* literal = 693 new Literal<float>(v, RawLiteral::kDeletedOnPlacementByPool); 694 EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(cond, Untyped32, rd); 695 GenerateInstruction(emit_helper, literal); 696 } 697 void Vldr(SRegister rd, float v) { Vldr(al, rd, v); } 698 699 void Vldr(Condition cond, DRegister rd, double v) { 700 RawLiteral* literal = 701 new Literal<double>(v, RawLiteral::kDeletedOnPlacementByPool); 702 EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(cond, Untyped64, rd); 703 GenerateInstruction(emit_helper, literal); 704 } 705 void Vldr(DRegister rd, double v) { Vldr(al, rd, v); } 706 707 void Vmov(Condition cond, DRegister rt, double v) { Vmov(cond, F64, rt, v); } 708 void Vmov(DRegister rt, double v) { Vmov(al, F64, rt, v); } 709 void Vmov(Condition cond, SRegister rt, float v) { Vmov(cond, F32, rt, v); } 710 void Vmov(SRegister rt, float v) { Vmov(al, F32, rt, v); } 711 712 void Switch(Register reg, JumpTableBase* table); 713 void GenerateSwitchTable(JumpTableBase* table, int table_size); 714 void Case(JumpTableBase* table, int case_index); 715 void Break(JumpTableBase* table); 716 void Default(JumpTableBase* table); 717 void EndSwitch(JumpTableBase* table); 718 719 // Claim memory on the stack. 720 // Note that the Claim, Drop, and Peek helpers below ensure that offsets used 721 // are multiples of 32 bits to help maintain 32-bit SP alignment. 722 // We could `Align{Up,Down}(size, 4)`, but that's potentially problematic: 723 // Claim(3) 724 // Claim(1) 725 // Drop(4) 726 // would seem correct, when in fact: 727 // Claim(3) -> sp = sp - 4 728 // Claim(1) -> sp = sp - 4 729 // Drop(4) -> sp = sp + 4 730 // 731 void Claim(int32_t size) { 732 if (size == 0) return; 733 // The stack must be kept 32bit aligned. 734 VIXL_ASSERT((size > 0) && ((size % 4) == 0)); 735 Sub(sp, sp, size); 736 } 737 // Release memory on the stack 738 void Drop(int32_t size) { 739 if (size == 0) return; 740 // The stack must be kept 32bit aligned. 741 VIXL_ASSERT((size > 0) && ((size % 4) == 0)); 742 Add(sp, sp, size); 743 } 744 void Peek(Register dst, int32_t offset) { 745 VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0)); 746 Ldr(dst, MemOperand(sp, offset)); 747 } 748 void Poke(Register src, int32_t offset) { 749 VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0)); 750 Str(src, MemOperand(sp, offset)); 751 } 752 void Printf(const char* format, 753 CPURegister reg1 = NoReg, 754 CPURegister reg2 = NoReg, 755 CPURegister reg3 = NoReg, 756 CPURegister reg4 = NoReg); 757 // Functions used by Printf for generation. 758 void PushRegister(CPURegister reg); 759 void PreparePrintfArgument(CPURegister reg, 760 int* core_count, 761 int* vfp_count, 762 uint32_t* printf_type); 763 // Handlers for cases not handled by the assembler. 764 virtual void Delegate(InstructionType type, 765 InstructionCondROp instruction, 766 Condition cond, 767 Register rn, 768 const Operand& operand) VIXL_OVERRIDE; 769 virtual void Delegate(InstructionType type, 770 InstructionCondSizeROp instruction, 771 Condition cond, 772 EncodingSize size, 773 Register rn, 774 const Operand& operand) VIXL_OVERRIDE; 775 virtual void Delegate(InstructionType type, 776 InstructionCondRROp instruction, 777 Condition cond, 778 Register rd, 779 Register rn, 780 const Operand& operand) VIXL_OVERRIDE; 781 virtual void Delegate(InstructionType type, 782 InstructionCondSizeRROp instruction, 783 Condition cond, 784 EncodingSize size, 785 Register rd, 786 Register rn, 787 const Operand& operand) VIXL_OVERRIDE; 788 virtual void Delegate(InstructionType type, 789 InstructionRL instruction, 790 Register rn, 791 Label* label) VIXL_OVERRIDE; 792 virtual void Delegate(InstructionType type, 793 InstructionCondDtSSop instruction, 794 Condition cond, 795 DataType dt, 796 SRegister rd, 797 const SOperand& operand) VIXL_OVERRIDE; 798 virtual void Delegate(InstructionType type, 799 InstructionCondDtDDop instruction, 800 Condition cond, 801 DataType dt, 802 DRegister rd, 803 const DOperand& operand) VIXL_OVERRIDE; 804 virtual void Delegate(InstructionType type, 805 InstructionCondDtQQop instruction, 806 Condition cond, 807 DataType dt, 808 QRegister rd, 809 const QOperand& operand) VIXL_OVERRIDE; 810 virtual void Delegate(InstructionType type, 811 InstructionCondSizeRMop instruction, 812 Condition cond, 813 EncodingSize size, 814 Register rd, 815 const MemOperand& operand) VIXL_OVERRIDE; 816 virtual void Delegate(InstructionType type, 817 InstructionCondRRMop instruction, 818 Condition cond, 819 Register rt, 820 Register rt2, 821 const MemOperand& operand) VIXL_OVERRIDE; 822 virtual void Delegate(InstructionType type, 823 InstructionCondDtSMop instruction, 824 Condition cond, 825 DataType dt, 826 SRegister rd, 827 const MemOperand& operand) VIXL_OVERRIDE; 828 virtual void Delegate(InstructionType type, 829 InstructionCondDtDMop instruction, 830 Condition cond, 831 DataType dt, 832 DRegister rd, 833 const MemOperand& operand) VIXL_OVERRIDE; 834 virtual void Delegate(InstructionType type, 835 InstructionCondMsrOp instruction, 836 Condition cond, 837 MaskedSpecialRegister spec_reg, 838 const Operand& operand) VIXL_OVERRIDE; 839 840 // Start of generated code. 841 842 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { 843 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 844 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 845 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 846 VIXL_ASSERT(allow_macro_instructions_); 847 VIXL_ASSERT(OutsideITBlock()); 848 MacroEmissionCheckScope guard(this); 849 bool can_use_it = 850 // ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 851 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && 852 operand.GetBaseRegister().IsLow(); 853 ITScope it_scope(this, &cond, can_use_it); 854 adc(cond, rd, rn, operand); 855 } 856 void Adc(Register rd, Register rn, const Operand& operand) { 857 Adc(al, rd, rn, operand); 858 } 859 void Adc(FlagsUpdate flags, 860 Condition cond, 861 Register rd, 862 Register rn, 863 const Operand& operand) { 864 switch (flags) { 865 case LeaveFlags: 866 Adc(cond, rd, rn, operand); 867 break; 868 case SetFlags: 869 Adcs(cond, rd, rn, operand); 870 break; 871 case DontCare: 872 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 873 rn.Is(rd) && operand.IsPlainRegister() && 874 operand.GetBaseRegister().IsLow(); 875 if (can_be_16bit_encoded) { 876 Adcs(cond, rd, rn, operand); 877 } else { 878 Adc(cond, rd, rn, operand); 879 } 880 break; 881 } 882 } 883 void Adc(FlagsUpdate flags, 884 Register rd, 885 Register rn, 886 const Operand& operand) { 887 Adc(flags, al, rd, rn, operand); 888 } 889 890 void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 891 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 892 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 893 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 894 VIXL_ASSERT(allow_macro_instructions_); 895 VIXL_ASSERT(OutsideITBlock()); 896 MacroEmissionCheckScope guard(this); 897 ITScope it_scope(this, &cond); 898 adcs(cond, rd, rn, operand); 899 } 900 void Adcs(Register rd, Register rn, const Operand& operand) { 901 Adcs(al, rd, rn, operand); 902 } 903 904 void Add(Condition cond, Register rd, Register rn, const Operand& operand) { 905 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 906 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 907 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 908 VIXL_ASSERT(allow_macro_instructions_); 909 VIXL_ASSERT(OutsideITBlock()); 910 MacroEmissionCheckScope guard(this); 911 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) { 912 uint32_t immediate = operand.GetImmediate(); 913 if (immediate == 0) { 914 return; 915 } 916 } 917 bool can_use_it = 918 // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 919 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() && 920 rd.IsLow()) || 921 // ADD<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2 922 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 923 rd.IsLow() && rn.Is(rd)) || 924 // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1 925 (operand.IsImmediate() && (operand.GetImmediate() <= 508) && 926 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) || 927 // ADD<c>{<q>} <Rd>, <Rn>, <Rm> 928 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 929 operand.GetBaseRegister().IsLow()) || 930 // ADD<c>{<q>} <Rdn>, <Rm> ; T2 931 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) && 932 !operand.GetBaseRegister().IsSP() && 933 !operand.GetBaseRegister().IsPC()) || 934 // ADD{<c>}{<q>} {<Rdm>,} SP, <Rdm> ; T1 935 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && 936 operand.GetBaseRegister().Is(rd)); 937 ITScope it_scope(this, &cond, can_use_it); 938 add(cond, rd, rn, operand); 939 } 940 void Add(Register rd, Register rn, const Operand& operand) { 941 Add(al, rd, rn, operand); 942 } 943 void Add(FlagsUpdate flags, 944 Condition cond, 945 Register rd, 946 Register rn, 947 const Operand& operand) { 948 switch (flags) { 949 case LeaveFlags: 950 Add(cond, rd, rn, operand); 951 break; 952 case SetFlags: 953 Adds(cond, rd, rn, operand); 954 break; 955 case DontCare: 956 bool can_be_16bit_encoded = 957 IsUsingT32() && cond.Is(al) && 958 ((operand.IsPlainRegister() && 959 ((rd.IsLow() && rn.IsLow() && 960 operand.GetBaseRegister().IsLow()) || 961 rd.Is(rn))) || 962 (operand.IsImmediate() && 963 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) || 964 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256))))); 965 if (can_be_16bit_encoded) { 966 Adds(cond, rd, rn, operand); 967 } else { 968 Add(cond, rd, rn, operand); 969 } 970 break; 971 } 972 } 973 void Add(FlagsUpdate flags, 974 Register rd, 975 Register rn, 976 const Operand& operand) { 977 Add(flags, al, rd, rn, operand); 978 } 979 980 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) { 981 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 982 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 983 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 984 VIXL_ASSERT(allow_macro_instructions_); 985 VIXL_ASSERT(OutsideITBlock()); 986 MacroEmissionCheckScope guard(this); 987 ITScope it_scope(this, &cond); 988 adds(cond, rd, rn, operand); 989 } 990 void Adds(Register rd, Register rn, const Operand& operand) { 991 Adds(al, rd, rn, operand); 992 } 993 994 void Adr(Condition cond, Register rd, Label* label) { 995 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 996 VIXL_ASSERT(allow_macro_instructions_); 997 VIXL_ASSERT(OutsideITBlock()); 998 MacroEmissionCheckScope guard(this); 999 ITScope it_scope(this, &cond); 1000 adr(cond, rd, label); 1001 } 1002 void Adr(Register rd, Label* label) { Adr(al, rd, label); } 1003 1004 void And(Condition cond, Register rd, Register rn, const Operand& operand) { 1005 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1006 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1007 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1008 VIXL_ASSERT(allow_macro_instructions_); 1009 VIXL_ASSERT(OutsideITBlock()); 1010 MacroEmissionCheckScope guard(this); 1011 if (cond.Is(al) && operand.IsImmediate()) { 1012 uint32_t immediate = operand.GetImmediate(); 1013 if (immediate == 0) { 1014 mov(rd, 0); 1015 return; 1016 } 1017 if ((immediate == 0xffffffff) && rd.Is(rn)) { 1018 return; 1019 } 1020 } 1021 bool can_use_it = 1022 // AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1023 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1024 operand.GetBaseRegister().IsLow(); 1025 ITScope it_scope(this, &cond, can_use_it); 1026 and_(cond, rd, rn, operand); 1027 } 1028 void And(Register rd, Register rn, const Operand& operand) { 1029 And(al, rd, rn, operand); 1030 } 1031 void And(FlagsUpdate flags, 1032 Condition cond, 1033 Register rd, 1034 Register rn, 1035 const Operand& operand) { 1036 switch (flags) { 1037 case LeaveFlags: 1038 And(cond, rd, rn, operand); 1039 break; 1040 case SetFlags: 1041 Ands(cond, rd, rn, operand); 1042 break; 1043 case DontCare: 1044 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1045 rn.Is(rd) && operand.IsPlainRegister() && 1046 operand.GetBaseRegister().IsLow(); 1047 if (can_be_16bit_encoded) { 1048 Ands(cond, rd, rn, operand); 1049 } else { 1050 And(cond, rd, rn, operand); 1051 } 1052 break; 1053 } 1054 } 1055 void And(FlagsUpdate flags, 1056 Register rd, 1057 Register rn, 1058 const Operand& operand) { 1059 And(flags, al, rd, rn, operand); 1060 } 1061 1062 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) { 1063 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1064 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1065 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1066 VIXL_ASSERT(allow_macro_instructions_); 1067 VIXL_ASSERT(OutsideITBlock()); 1068 MacroEmissionCheckScope guard(this); 1069 ITScope it_scope(this, &cond); 1070 ands(cond, rd, rn, operand); 1071 } 1072 void Ands(Register rd, Register rn, const Operand& operand) { 1073 Ands(al, rd, rn, operand); 1074 } 1075 1076 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { 1077 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1078 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1079 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1080 VIXL_ASSERT(allow_macro_instructions_); 1081 VIXL_ASSERT(OutsideITBlock()); 1082 MacroEmissionCheckScope guard(this); 1083 bool can_use_it = 1084 // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 1085 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 1086 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || 1087 // ASR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 1088 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 1089 operand.GetBaseRegister().IsLow()); 1090 ITScope it_scope(this, &cond, can_use_it); 1091 asr(cond, rd, rm, operand); 1092 } 1093 void Asr(Register rd, Register rm, const Operand& operand) { 1094 Asr(al, rd, rm, operand); 1095 } 1096 void Asr(FlagsUpdate flags, 1097 Condition cond, 1098 Register rd, 1099 Register rm, 1100 const Operand& operand) { 1101 switch (flags) { 1102 case LeaveFlags: 1103 Asr(cond, rd, rm, operand); 1104 break; 1105 case SetFlags: 1106 Asrs(cond, rd, rm, operand); 1107 break; 1108 case DontCare: 1109 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1110 rm.IsLow() && operand.IsImmediate() && 1111 (operand.GetImmediate() < 32); 1112 if (can_be_16bit_encoded) { 1113 Asrs(cond, rd, rm, operand); 1114 } else { 1115 Asr(cond, rd, rm, operand); 1116 } 1117 break; 1118 } 1119 } 1120 void Asr(FlagsUpdate flags, 1121 Register rd, 1122 Register rm, 1123 const Operand& operand) { 1124 Asr(flags, al, rd, rm, operand); 1125 } 1126 1127 void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 1128 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1129 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1130 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1131 VIXL_ASSERT(allow_macro_instructions_); 1132 VIXL_ASSERT(OutsideITBlock()); 1133 MacroEmissionCheckScope guard(this); 1134 ITScope it_scope(this, &cond); 1135 asrs(cond, rd, rm, operand); 1136 } 1137 void Asrs(Register rd, Register rm, const Operand& operand) { 1138 Asrs(al, rd, rm, operand); 1139 } 1140 1141 void B(Condition cond, Label* label) { 1142 VIXL_ASSERT(allow_macro_instructions_); 1143 VIXL_ASSERT(OutsideITBlock()); 1144 MacroEmissionCheckScope guard(this); 1145 b(cond, label); 1146 AddBranchLabel(label); 1147 } 1148 void B(Label* label) { B(al, label); } 1149 1150 void Bfc(Condition cond, Register rd, uint32_t lsb, const Operand& operand) { 1151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1152 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1153 VIXL_ASSERT(allow_macro_instructions_); 1154 VIXL_ASSERT(OutsideITBlock()); 1155 MacroEmissionCheckScope guard(this); 1156 ITScope it_scope(this, &cond); 1157 bfc(cond, rd, lsb, operand); 1158 } 1159 void Bfc(Register rd, uint32_t lsb, const Operand& operand) { 1160 Bfc(al, rd, lsb, operand); 1161 } 1162 1163 void Bfi(Condition cond, 1164 Register rd, 1165 Register rn, 1166 uint32_t lsb, 1167 const Operand& operand) { 1168 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1169 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1170 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1171 VIXL_ASSERT(allow_macro_instructions_); 1172 VIXL_ASSERT(OutsideITBlock()); 1173 MacroEmissionCheckScope guard(this); 1174 ITScope it_scope(this, &cond); 1175 bfi(cond, rd, rn, lsb, operand); 1176 } 1177 void Bfi(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 1178 Bfi(al, rd, rn, lsb, operand); 1179 } 1180 1181 void Bic(Condition cond, Register rd, Register rn, const Operand& operand) { 1182 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1183 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1184 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1185 VIXL_ASSERT(allow_macro_instructions_); 1186 VIXL_ASSERT(OutsideITBlock()); 1187 MacroEmissionCheckScope guard(this); 1188 if (cond.Is(al) && operand.IsImmediate()) { 1189 uint32_t immediate = operand.GetImmediate(); 1190 if ((immediate == 0) && rd.Is(rn)) { 1191 return; 1192 } 1193 if (immediate == 0xffffffff) { 1194 mov(rd, 0); 1195 return; 1196 } 1197 } 1198 bool can_use_it = 1199 // BIC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1200 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1201 operand.GetBaseRegister().IsLow(); 1202 ITScope it_scope(this, &cond, can_use_it); 1203 bic(cond, rd, rn, operand); 1204 } 1205 void Bic(Register rd, Register rn, const Operand& operand) { 1206 Bic(al, rd, rn, operand); 1207 } 1208 void Bic(FlagsUpdate flags, 1209 Condition cond, 1210 Register rd, 1211 Register rn, 1212 const Operand& operand) { 1213 switch (flags) { 1214 case LeaveFlags: 1215 Bic(cond, rd, rn, operand); 1216 break; 1217 case SetFlags: 1218 Bics(cond, rd, rn, operand); 1219 break; 1220 case DontCare: 1221 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1222 rn.Is(rd) && operand.IsPlainRegister() && 1223 operand.GetBaseRegister().IsLow(); 1224 if (can_be_16bit_encoded) { 1225 Bics(cond, rd, rn, operand); 1226 } else { 1227 Bic(cond, rd, rn, operand); 1228 } 1229 break; 1230 } 1231 } 1232 void Bic(FlagsUpdate flags, 1233 Register rd, 1234 Register rn, 1235 const Operand& operand) { 1236 Bic(flags, al, rd, rn, operand); 1237 } 1238 1239 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) { 1240 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1241 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1242 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1243 VIXL_ASSERT(allow_macro_instructions_); 1244 VIXL_ASSERT(OutsideITBlock()); 1245 MacroEmissionCheckScope guard(this); 1246 ITScope it_scope(this, &cond); 1247 bics(cond, rd, rn, operand); 1248 } 1249 void Bics(Register rd, Register rn, const Operand& operand) { 1250 Bics(al, rd, rn, operand); 1251 } 1252 1253 void Bkpt(Condition cond, uint32_t imm) { 1254 VIXL_ASSERT(allow_macro_instructions_); 1255 VIXL_ASSERT(OutsideITBlock()); 1256 MacroEmissionCheckScope guard(this); 1257 ITScope it_scope(this, &cond); 1258 bkpt(cond, imm); 1259 } 1260 void Bkpt(uint32_t imm) { Bkpt(al, imm); } 1261 1262 void Bl(Condition cond, Label* label) { 1263 VIXL_ASSERT(allow_macro_instructions_); 1264 VIXL_ASSERT(OutsideITBlock()); 1265 MacroEmissionCheckScope guard(this); 1266 ITScope it_scope(this, &cond); 1267 bl(cond, label); 1268 AddBranchLabel(label); 1269 } 1270 void Bl(Label* label) { Bl(al, label); } 1271 1272 void Blx(Condition cond, Label* label) { 1273 VIXL_ASSERT(allow_macro_instructions_); 1274 VIXL_ASSERT(OutsideITBlock()); 1275 MacroEmissionCheckScope guard(this); 1276 ITScope it_scope(this, &cond); 1277 blx(cond, label); 1278 AddBranchLabel(label); 1279 } 1280 void Blx(Label* label) { Blx(al, label); } 1281 1282 void Blx(Condition cond, Register rm) { 1283 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1284 VIXL_ASSERT(allow_macro_instructions_); 1285 VIXL_ASSERT(OutsideITBlock()); 1286 MacroEmissionCheckScope guard(this); 1287 bool can_use_it = 1288 // BLX{<c>}{<q>} <Rm> ; T1 1289 !rm.IsPC(); 1290 ITScope it_scope(this, &cond, can_use_it); 1291 blx(cond, rm); 1292 } 1293 void Blx(Register rm) { Blx(al, rm); } 1294 1295 void Bx(Condition cond, Register rm) { 1296 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1297 VIXL_ASSERT(allow_macro_instructions_); 1298 VIXL_ASSERT(OutsideITBlock()); 1299 MacroEmissionCheckScope guard(this); 1300 bool can_use_it = 1301 // BX{<c>}{<q>} <Rm> ; T1 1302 !rm.IsPC(); 1303 ITScope it_scope(this, &cond, can_use_it); 1304 bx(cond, rm); 1305 } 1306 void Bx(Register rm) { Bx(al, rm); } 1307 1308 void Bxj(Condition cond, Register rm) { 1309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1310 VIXL_ASSERT(allow_macro_instructions_); 1311 VIXL_ASSERT(OutsideITBlock()); 1312 MacroEmissionCheckScope guard(this); 1313 ITScope it_scope(this, &cond); 1314 bxj(cond, rm); 1315 } 1316 void Bxj(Register rm) { Bxj(al, rm); } 1317 1318 void Cbnz(Register rn, Label* label) { 1319 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1320 VIXL_ASSERT(allow_macro_instructions_); 1321 VIXL_ASSERT(OutsideITBlock()); 1322 MacroEmissionCheckScope guard(this); 1323 cbnz(rn, label); 1324 AddBranchLabel(label); 1325 } 1326 1327 void Cbz(Register rn, Label* label) { 1328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1329 VIXL_ASSERT(allow_macro_instructions_); 1330 VIXL_ASSERT(OutsideITBlock()); 1331 MacroEmissionCheckScope guard(this); 1332 cbz(rn, label); 1333 AddBranchLabel(label); 1334 } 1335 1336 void Clrex(Condition cond) { 1337 VIXL_ASSERT(allow_macro_instructions_); 1338 VIXL_ASSERT(OutsideITBlock()); 1339 MacroEmissionCheckScope guard(this); 1340 ITScope it_scope(this, &cond); 1341 clrex(cond); 1342 } 1343 void Clrex() { Clrex(al); } 1344 1345 void Clz(Condition cond, Register rd, Register rm) { 1346 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1347 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1348 VIXL_ASSERT(allow_macro_instructions_); 1349 VIXL_ASSERT(OutsideITBlock()); 1350 MacroEmissionCheckScope guard(this); 1351 ITScope it_scope(this, &cond); 1352 clz(cond, rd, rm); 1353 } 1354 void Clz(Register rd, Register rm) { Clz(al, rd, rm); } 1355 1356 void Cmn(Condition cond, Register rn, const Operand& operand) { 1357 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1358 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1359 VIXL_ASSERT(allow_macro_instructions_); 1360 VIXL_ASSERT(OutsideITBlock()); 1361 MacroEmissionCheckScope guard(this); 1362 bool can_use_it = 1363 // CMN{<c>}{<q>} <Rn>, <Rm> ; T1 1364 operand.IsPlainRegister() && rn.IsLow() && 1365 operand.GetBaseRegister().IsLow(); 1366 ITScope it_scope(this, &cond, can_use_it); 1367 cmn(cond, rn, operand); 1368 } 1369 void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); } 1370 1371 void Cmp(Condition cond, Register rn, const Operand& operand) { 1372 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1373 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1374 VIXL_ASSERT(allow_macro_instructions_); 1375 VIXL_ASSERT(OutsideITBlock()); 1376 MacroEmissionCheckScope guard(this); 1377 bool can_use_it = 1378 // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1 1379 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 1380 rn.IsLow()) || 1381 // CMP{<c>}{<q>} <Rn>, <Rm> ; T1 T2 1382 (operand.IsPlainRegister() && !rn.IsPC() && 1383 !operand.GetBaseRegister().IsPC()); 1384 ITScope it_scope(this, &cond, can_use_it); 1385 cmp(cond, rn, operand); 1386 } 1387 void Cmp(Register rn, const Operand& operand) { Cmp(al, rn, operand); } 1388 1389 void Crc32b(Condition cond, Register rd, Register rn, Register rm) { 1390 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1391 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1392 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1393 VIXL_ASSERT(allow_macro_instructions_); 1394 VIXL_ASSERT(OutsideITBlock()); 1395 MacroEmissionCheckScope guard(this); 1396 ITScope it_scope(this, &cond); 1397 crc32b(cond, rd, rn, rm); 1398 } 1399 void Crc32b(Register rd, Register rn, Register rm) { Crc32b(al, rd, rn, rm); } 1400 1401 void Crc32cb(Condition cond, Register rd, Register rn, Register rm) { 1402 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1403 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1404 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1405 VIXL_ASSERT(allow_macro_instructions_); 1406 VIXL_ASSERT(OutsideITBlock()); 1407 MacroEmissionCheckScope guard(this); 1408 ITScope it_scope(this, &cond); 1409 crc32cb(cond, rd, rn, rm); 1410 } 1411 void Crc32cb(Register rd, Register rn, Register rm) { 1412 Crc32cb(al, rd, rn, rm); 1413 } 1414 1415 void Crc32ch(Condition cond, Register rd, Register rn, Register rm) { 1416 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1417 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1418 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1419 VIXL_ASSERT(allow_macro_instructions_); 1420 VIXL_ASSERT(OutsideITBlock()); 1421 MacroEmissionCheckScope guard(this); 1422 ITScope it_scope(this, &cond); 1423 crc32ch(cond, rd, rn, rm); 1424 } 1425 void Crc32ch(Register rd, Register rn, Register rm) { 1426 Crc32ch(al, rd, rn, rm); 1427 } 1428 1429 void Crc32cw(Condition cond, Register rd, Register rn, Register rm) { 1430 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1431 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1432 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1433 VIXL_ASSERT(allow_macro_instructions_); 1434 VIXL_ASSERT(OutsideITBlock()); 1435 MacroEmissionCheckScope guard(this); 1436 ITScope it_scope(this, &cond); 1437 crc32cw(cond, rd, rn, rm); 1438 } 1439 void Crc32cw(Register rd, Register rn, Register rm) { 1440 Crc32cw(al, rd, rn, rm); 1441 } 1442 1443 void Crc32h(Condition cond, Register rd, Register rn, Register rm) { 1444 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1445 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1446 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1447 VIXL_ASSERT(allow_macro_instructions_); 1448 VIXL_ASSERT(OutsideITBlock()); 1449 MacroEmissionCheckScope guard(this); 1450 ITScope it_scope(this, &cond); 1451 crc32h(cond, rd, rn, rm); 1452 } 1453 void Crc32h(Register rd, Register rn, Register rm) { Crc32h(al, rd, rn, rm); } 1454 1455 void Crc32w(Condition cond, Register rd, Register rn, Register rm) { 1456 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1457 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1458 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1459 VIXL_ASSERT(allow_macro_instructions_); 1460 VIXL_ASSERT(OutsideITBlock()); 1461 MacroEmissionCheckScope guard(this); 1462 ITScope it_scope(this, &cond); 1463 crc32w(cond, rd, rn, rm); 1464 } 1465 void Crc32w(Register rd, Register rn, Register rm) { Crc32w(al, rd, rn, rm); } 1466 1467 void Dmb(Condition cond, MemoryBarrier option) { 1468 VIXL_ASSERT(allow_macro_instructions_); 1469 VIXL_ASSERT(OutsideITBlock()); 1470 MacroEmissionCheckScope guard(this); 1471 ITScope it_scope(this, &cond); 1472 dmb(cond, option); 1473 } 1474 void Dmb(MemoryBarrier option) { Dmb(al, option); } 1475 1476 void Dsb(Condition cond, MemoryBarrier option) { 1477 VIXL_ASSERT(allow_macro_instructions_); 1478 VIXL_ASSERT(OutsideITBlock()); 1479 MacroEmissionCheckScope guard(this); 1480 ITScope it_scope(this, &cond); 1481 dsb(cond, option); 1482 } 1483 void Dsb(MemoryBarrier option) { Dsb(al, option); } 1484 1485 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { 1486 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1487 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1488 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1489 VIXL_ASSERT(allow_macro_instructions_); 1490 VIXL_ASSERT(OutsideITBlock()); 1491 MacroEmissionCheckScope guard(this); 1492 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) { 1493 uint32_t immediate = operand.GetImmediate(); 1494 if (immediate == 0) { 1495 return; 1496 } 1497 if (immediate == 0xffffffff) { 1498 mvn(rd, rn); 1499 return; 1500 } 1501 } 1502 bool can_use_it = 1503 // EOR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1504 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1505 operand.GetBaseRegister().IsLow(); 1506 ITScope it_scope(this, &cond, can_use_it); 1507 eor(cond, rd, rn, operand); 1508 } 1509 void Eor(Register rd, Register rn, const Operand& operand) { 1510 Eor(al, rd, rn, operand); 1511 } 1512 void Eor(FlagsUpdate flags, 1513 Condition cond, 1514 Register rd, 1515 Register rn, 1516 const Operand& operand) { 1517 switch (flags) { 1518 case LeaveFlags: 1519 Eor(cond, rd, rn, operand); 1520 break; 1521 case SetFlags: 1522 Eors(cond, rd, rn, operand); 1523 break; 1524 case DontCare: 1525 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1526 rn.Is(rd) && operand.IsPlainRegister() && 1527 operand.GetBaseRegister().IsLow(); 1528 if (can_be_16bit_encoded) { 1529 Eors(cond, rd, rn, operand); 1530 } else { 1531 Eor(cond, rd, rn, operand); 1532 } 1533 break; 1534 } 1535 } 1536 void Eor(FlagsUpdate flags, 1537 Register rd, 1538 Register rn, 1539 const Operand& operand) { 1540 Eor(flags, al, rd, rn, operand); 1541 } 1542 1543 void Eors(Condition cond, Register rd, Register rn, const Operand& operand) { 1544 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1545 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1546 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1547 VIXL_ASSERT(allow_macro_instructions_); 1548 VIXL_ASSERT(OutsideITBlock()); 1549 MacroEmissionCheckScope guard(this); 1550 ITScope it_scope(this, &cond); 1551 eors(cond, rd, rn, operand); 1552 } 1553 void Eors(Register rd, Register rn, const Operand& operand) { 1554 Eors(al, rd, rn, operand); 1555 } 1556 1557 void Fldmdbx(Condition cond, 1558 Register rn, 1559 WriteBack write_back, 1560 DRegisterList dreglist) { 1561 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1562 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1563 VIXL_ASSERT(allow_macro_instructions_); 1564 VIXL_ASSERT(OutsideITBlock()); 1565 MacroEmissionCheckScope guard(this); 1566 ITScope it_scope(this, &cond); 1567 fldmdbx(cond, rn, write_back, dreglist); 1568 } 1569 void Fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1570 Fldmdbx(al, rn, write_back, dreglist); 1571 } 1572 1573 void Fldmiax(Condition cond, 1574 Register rn, 1575 WriteBack write_back, 1576 DRegisterList dreglist) { 1577 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1578 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1579 VIXL_ASSERT(allow_macro_instructions_); 1580 VIXL_ASSERT(OutsideITBlock()); 1581 MacroEmissionCheckScope guard(this); 1582 ITScope it_scope(this, &cond); 1583 fldmiax(cond, rn, write_back, dreglist); 1584 } 1585 void Fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1586 Fldmiax(al, rn, write_back, dreglist); 1587 } 1588 1589 void Fstmdbx(Condition cond, 1590 Register rn, 1591 WriteBack write_back, 1592 DRegisterList dreglist) { 1593 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1594 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1595 VIXL_ASSERT(allow_macro_instructions_); 1596 VIXL_ASSERT(OutsideITBlock()); 1597 MacroEmissionCheckScope guard(this); 1598 ITScope it_scope(this, &cond); 1599 fstmdbx(cond, rn, write_back, dreglist); 1600 } 1601 void Fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1602 Fstmdbx(al, rn, write_back, dreglist); 1603 } 1604 1605 void Fstmiax(Condition cond, 1606 Register rn, 1607 WriteBack write_back, 1608 DRegisterList dreglist) { 1609 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1610 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1611 VIXL_ASSERT(allow_macro_instructions_); 1612 VIXL_ASSERT(OutsideITBlock()); 1613 MacroEmissionCheckScope guard(this); 1614 ITScope it_scope(this, &cond); 1615 fstmiax(cond, rn, write_back, dreglist); 1616 } 1617 void Fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1618 Fstmiax(al, rn, write_back, dreglist); 1619 } 1620 1621 void Hlt(Condition cond, uint32_t imm) { 1622 VIXL_ASSERT(allow_macro_instructions_); 1623 VIXL_ASSERT(OutsideITBlock()); 1624 MacroEmissionCheckScope guard(this); 1625 ITScope it_scope(this, &cond); 1626 hlt(cond, imm); 1627 } 1628 void Hlt(uint32_t imm) { Hlt(al, imm); } 1629 1630 void Hvc(Condition cond, uint32_t imm) { 1631 VIXL_ASSERT(allow_macro_instructions_); 1632 VIXL_ASSERT(OutsideITBlock()); 1633 MacroEmissionCheckScope guard(this); 1634 ITScope it_scope(this, &cond); 1635 hvc(cond, imm); 1636 } 1637 void Hvc(uint32_t imm) { Hvc(al, imm); } 1638 1639 void Isb(Condition cond, MemoryBarrier option) { 1640 VIXL_ASSERT(allow_macro_instructions_); 1641 VIXL_ASSERT(OutsideITBlock()); 1642 MacroEmissionCheckScope guard(this); 1643 ITScope it_scope(this, &cond); 1644 isb(cond, option); 1645 } 1646 void Isb(MemoryBarrier option) { Isb(al, option); } 1647 1648 1649 void Lda(Condition cond, Register rt, const MemOperand& operand) { 1650 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1651 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1652 VIXL_ASSERT(allow_macro_instructions_); 1653 VIXL_ASSERT(OutsideITBlock()); 1654 MacroEmissionCheckScope guard(this); 1655 ITScope it_scope(this, &cond); 1656 lda(cond, rt, operand); 1657 } 1658 void Lda(Register rt, const MemOperand& operand) { Lda(al, rt, operand); } 1659 1660 void Ldab(Condition cond, Register rt, const MemOperand& operand) { 1661 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1662 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1663 VIXL_ASSERT(allow_macro_instructions_); 1664 VIXL_ASSERT(OutsideITBlock()); 1665 MacroEmissionCheckScope guard(this); 1666 ITScope it_scope(this, &cond); 1667 ldab(cond, rt, operand); 1668 } 1669 void Ldab(Register rt, const MemOperand& operand) { Ldab(al, rt, operand); } 1670 1671 void Ldaex(Condition cond, Register rt, const MemOperand& operand) { 1672 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1673 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1674 VIXL_ASSERT(allow_macro_instructions_); 1675 VIXL_ASSERT(OutsideITBlock()); 1676 MacroEmissionCheckScope guard(this); 1677 ITScope it_scope(this, &cond); 1678 ldaex(cond, rt, operand); 1679 } 1680 void Ldaex(Register rt, const MemOperand& operand) { Ldaex(al, rt, operand); } 1681 1682 void Ldaexb(Condition cond, Register rt, const MemOperand& operand) { 1683 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1684 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1685 VIXL_ASSERT(allow_macro_instructions_); 1686 VIXL_ASSERT(OutsideITBlock()); 1687 MacroEmissionCheckScope guard(this); 1688 ITScope it_scope(this, &cond); 1689 ldaexb(cond, rt, operand); 1690 } 1691 void Ldaexb(Register rt, const MemOperand& operand) { 1692 Ldaexb(al, rt, operand); 1693 } 1694 1695 void Ldaexd(Condition cond, 1696 Register rt, 1697 Register rt2, 1698 const MemOperand& operand) { 1699 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1700 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 1701 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1702 VIXL_ASSERT(allow_macro_instructions_); 1703 VIXL_ASSERT(OutsideITBlock()); 1704 MacroEmissionCheckScope guard(this); 1705 ITScope it_scope(this, &cond); 1706 ldaexd(cond, rt, rt2, operand); 1707 } 1708 void Ldaexd(Register rt, Register rt2, const MemOperand& operand) { 1709 Ldaexd(al, rt, rt2, operand); 1710 } 1711 1712 void Ldaexh(Condition cond, Register rt, const MemOperand& operand) { 1713 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1714 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1715 VIXL_ASSERT(allow_macro_instructions_); 1716 VIXL_ASSERT(OutsideITBlock()); 1717 MacroEmissionCheckScope guard(this); 1718 ITScope it_scope(this, &cond); 1719 ldaexh(cond, rt, operand); 1720 } 1721 void Ldaexh(Register rt, const MemOperand& operand) { 1722 Ldaexh(al, rt, operand); 1723 } 1724 1725 void Ldah(Condition cond, Register rt, const MemOperand& operand) { 1726 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1727 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1728 VIXL_ASSERT(allow_macro_instructions_); 1729 VIXL_ASSERT(OutsideITBlock()); 1730 MacroEmissionCheckScope guard(this); 1731 ITScope it_scope(this, &cond); 1732 ldah(cond, rt, operand); 1733 } 1734 void Ldah(Register rt, const MemOperand& operand) { Ldah(al, rt, operand); } 1735 1736 void Ldm(Condition cond, 1737 Register rn, 1738 WriteBack write_back, 1739 RegisterList registers) { 1740 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1741 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1742 VIXL_ASSERT(allow_macro_instructions_); 1743 VIXL_ASSERT(OutsideITBlock()); 1744 MacroEmissionCheckScope guard(this); 1745 ITScope it_scope(this, &cond); 1746 ldm(cond, rn, write_back, registers); 1747 } 1748 void Ldm(Register rn, WriteBack write_back, RegisterList registers) { 1749 Ldm(al, rn, write_back, registers); 1750 } 1751 1752 void Ldmda(Condition cond, 1753 Register rn, 1754 WriteBack write_back, 1755 RegisterList registers) { 1756 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1757 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1758 VIXL_ASSERT(allow_macro_instructions_); 1759 VIXL_ASSERT(OutsideITBlock()); 1760 MacroEmissionCheckScope guard(this); 1761 ITScope it_scope(this, &cond); 1762 ldmda(cond, rn, write_back, registers); 1763 } 1764 void Ldmda(Register rn, WriteBack write_back, RegisterList registers) { 1765 Ldmda(al, rn, write_back, registers); 1766 } 1767 1768 void Ldmdb(Condition cond, 1769 Register rn, 1770 WriteBack write_back, 1771 RegisterList registers) { 1772 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1773 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1774 VIXL_ASSERT(allow_macro_instructions_); 1775 VIXL_ASSERT(OutsideITBlock()); 1776 MacroEmissionCheckScope guard(this); 1777 ITScope it_scope(this, &cond); 1778 ldmdb(cond, rn, write_back, registers); 1779 } 1780 void Ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 1781 Ldmdb(al, rn, write_back, registers); 1782 } 1783 1784 void Ldmea(Condition cond, 1785 Register rn, 1786 WriteBack write_back, 1787 RegisterList registers) { 1788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1789 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1790 VIXL_ASSERT(allow_macro_instructions_); 1791 VIXL_ASSERT(OutsideITBlock()); 1792 MacroEmissionCheckScope guard(this); 1793 ITScope it_scope(this, &cond); 1794 ldmea(cond, rn, write_back, registers); 1795 } 1796 void Ldmea(Register rn, WriteBack write_back, RegisterList registers) { 1797 Ldmea(al, rn, write_back, registers); 1798 } 1799 1800 void Ldmed(Condition cond, 1801 Register rn, 1802 WriteBack write_back, 1803 RegisterList registers) { 1804 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1805 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1806 VIXL_ASSERT(allow_macro_instructions_); 1807 VIXL_ASSERT(OutsideITBlock()); 1808 MacroEmissionCheckScope guard(this); 1809 ITScope it_scope(this, &cond); 1810 ldmed(cond, rn, write_back, registers); 1811 } 1812 void Ldmed(Register rn, WriteBack write_back, RegisterList registers) { 1813 Ldmed(al, rn, write_back, registers); 1814 } 1815 1816 void Ldmfa(Condition cond, 1817 Register rn, 1818 WriteBack write_back, 1819 RegisterList registers) { 1820 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1821 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1822 VIXL_ASSERT(allow_macro_instructions_); 1823 VIXL_ASSERT(OutsideITBlock()); 1824 MacroEmissionCheckScope guard(this); 1825 ITScope it_scope(this, &cond); 1826 ldmfa(cond, rn, write_back, registers); 1827 } 1828 void Ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 1829 Ldmfa(al, rn, write_back, registers); 1830 } 1831 1832 void Ldmfd(Condition cond, 1833 Register rn, 1834 WriteBack write_back, 1835 RegisterList registers) { 1836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1837 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1838 VIXL_ASSERT(allow_macro_instructions_); 1839 VIXL_ASSERT(OutsideITBlock()); 1840 MacroEmissionCheckScope guard(this); 1841 ITScope it_scope(this, &cond); 1842 ldmfd(cond, rn, write_back, registers); 1843 } 1844 void Ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 1845 Ldmfd(al, rn, write_back, registers); 1846 } 1847 1848 void Ldmib(Condition cond, 1849 Register rn, 1850 WriteBack write_back, 1851 RegisterList registers) { 1852 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1853 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1854 VIXL_ASSERT(allow_macro_instructions_); 1855 VIXL_ASSERT(OutsideITBlock()); 1856 MacroEmissionCheckScope guard(this); 1857 ITScope it_scope(this, &cond); 1858 ldmib(cond, rn, write_back, registers); 1859 } 1860 void Ldmib(Register rn, WriteBack write_back, RegisterList registers) { 1861 Ldmib(al, rn, write_back, registers); 1862 } 1863 1864 void Ldr(Condition cond, Register rt, const MemOperand& operand) { 1865 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1866 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1867 VIXL_ASSERT(allow_macro_instructions_); 1868 VIXL_ASSERT(OutsideITBlock()); 1869 MacroEmissionCheckScope guard(this); 1870 bool can_use_it = 1871 // LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 1872 (operand.IsImmediate() && rt.IsLow() && 1873 operand.GetBaseRegister().IsLow() && 1874 operand.IsOffsetImmediateWithinRange(0, 124, 4) && 1875 (operand.GetAddrMode() == Offset)) || 1876 // LDR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2 1877 (operand.IsImmediate() && rt.IsLow() && 1878 operand.GetBaseRegister().IsSP() && 1879 operand.IsOffsetImmediateWithinRange(0, 1020, 4) && 1880 (operand.GetAddrMode() == Offset)) || 1881 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1882 (operand.IsPlainRegister() && rt.IsLow() && 1883 operand.GetBaseRegister().IsLow() && 1884 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1885 (operand.GetAddrMode() == Offset)); 1886 ITScope it_scope(this, &cond, can_use_it); 1887 ldr(cond, rt, operand); 1888 } 1889 void Ldr(Register rt, const MemOperand& operand) { Ldr(al, rt, operand); } 1890 1891 void Ldr(Condition cond, Register rt, Label* label) { 1892 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1893 VIXL_ASSERT(allow_macro_instructions_); 1894 VIXL_ASSERT(OutsideITBlock()); 1895 MacroEmissionCheckScope guard(this); 1896 ITScope it_scope(this, &cond); 1897 ldr(cond, rt, label); 1898 } 1899 void Ldr(Register rt, Label* label) { Ldr(al, rt, label); } 1900 1901 void Ldrb(Condition cond, Register rt, const MemOperand& operand) { 1902 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1903 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1904 VIXL_ASSERT(allow_macro_instructions_); 1905 VIXL_ASSERT(OutsideITBlock()); 1906 MacroEmissionCheckScope guard(this); 1907 bool can_use_it = 1908 // LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 1909 (operand.IsImmediate() && rt.IsLow() && 1910 operand.GetBaseRegister().IsLow() && 1911 operand.IsOffsetImmediateWithinRange(0, 31) && 1912 (operand.GetAddrMode() == Offset)) || 1913 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1914 (operand.IsPlainRegister() && rt.IsLow() && 1915 operand.GetBaseRegister().IsLow() && 1916 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1917 (operand.GetAddrMode() == Offset)); 1918 ITScope it_scope(this, &cond, can_use_it); 1919 ldrb(cond, rt, operand); 1920 } 1921 void Ldrb(Register rt, const MemOperand& operand) { Ldrb(al, rt, operand); } 1922 1923 void Ldrb(Condition cond, Register rt, Label* label) { 1924 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1925 VIXL_ASSERT(allow_macro_instructions_); 1926 VIXL_ASSERT(OutsideITBlock()); 1927 MacroEmissionCheckScope guard(this); 1928 ITScope it_scope(this, &cond); 1929 ldrb(cond, rt, label); 1930 } 1931 void Ldrb(Register rt, Label* label) { Ldrb(al, rt, label); } 1932 1933 void Ldrd(Condition cond, 1934 Register rt, 1935 Register rt2, 1936 const MemOperand& operand) { 1937 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1938 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 1939 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1940 VIXL_ASSERT(allow_macro_instructions_); 1941 VIXL_ASSERT(OutsideITBlock()); 1942 MacroEmissionCheckScope guard(this); 1943 ITScope it_scope(this, &cond); 1944 ldrd(cond, rt, rt2, operand); 1945 } 1946 void Ldrd(Register rt, Register rt2, const MemOperand& operand) { 1947 Ldrd(al, rt, rt2, operand); 1948 } 1949 1950 void Ldrd(Condition cond, Register rt, Register rt2, Label* label) { 1951 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1952 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 1953 VIXL_ASSERT(allow_macro_instructions_); 1954 VIXL_ASSERT(OutsideITBlock()); 1955 MacroEmissionCheckScope guard(this); 1956 ITScope it_scope(this, &cond); 1957 ldrd(cond, rt, rt2, label); 1958 } 1959 void Ldrd(Register rt, Register rt2, Label* label) { 1960 Ldrd(al, rt, rt2, label); 1961 } 1962 1963 void Ldrex(Condition cond, Register rt, const MemOperand& operand) { 1964 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1965 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1966 VIXL_ASSERT(allow_macro_instructions_); 1967 VIXL_ASSERT(OutsideITBlock()); 1968 MacroEmissionCheckScope guard(this); 1969 ITScope it_scope(this, &cond); 1970 ldrex(cond, rt, operand); 1971 } 1972 void Ldrex(Register rt, const MemOperand& operand) { Ldrex(al, rt, operand); } 1973 1974 void Ldrexb(Condition cond, Register rt, const MemOperand& operand) { 1975 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1976 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1977 VIXL_ASSERT(allow_macro_instructions_); 1978 VIXL_ASSERT(OutsideITBlock()); 1979 MacroEmissionCheckScope guard(this); 1980 ITScope it_scope(this, &cond); 1981 ldrexb(cond, rt, operand); 1982 } 1983 void Ldrexb(Register rt, const MemOperand& operand) { 1984 Ldrexb(al, rt, operand); 1985 } 1986 1987 void Ldrexd(Condition cond, 1988 Register rt, 1989 Register rt2, 1990 const MemOperand& operand) { 1991 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1992 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 1993 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1994 VIXL_ASSERT(allow_macro_instructions_); 1995 VIXL_ASSERT(OutsideITBlock()); 1996 MacroEmissionCheckScope guard(this); 1997 ITScope it_scope(this, &cond); 1998 ldrexd(cond, rt, rt2, operand); 1999 } 2000 void Ldrexd(Register rt, Register rt2, const MemOperand& operand) { 2001 Ldrexd(al, rt, rt2, operand); 2002 } 2003 2004 void Ldrexh(Condition cond, Register rt, const MemOperand& operand) { 2005 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2006 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2007 VIXL_ASSERT(allow_macro_instructions_); 2008 VIXL_ASSERT(OutsideITBlock()); 2009 MacroEmissionCheckScope guard(this); 2010 ITScope it_scope(this, &cond); 2011 ldrexh(cond, rt, operand); 2012 } 2013 void Ldrexh(Register rt, const MemOperand& operand) { 2014 Ldrexh(al, rt, operand); 2015 } 2016 2017 void Ldrh(Condition cond, Register rt, const MemOperand& operand) { 2018 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2019 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2020 VIXL_ASSERT(allow_macro_instructions_); 2021 VIXL_ASSERT(OutsideITBlock()); 2022 MacroEmissionCheckScope guard(this); 2023 bool can_use_it = 2024 // LDRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 2025 (operand.IsImmediate() && rt.IsLow() && 2026 operand.GetBaseRegister().IsLow() && 2027 operand.IsOffsetImmediateWithinRange(0, 62, 2) && 2028 (operand.GetAddrMode() == Offset)) || 2029 // LDRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2030 (operand.IsPlainRegister() && rt.IsLow() && 2031 operand.GetBaseRegister().IsLow() && 2032 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2033 (operand.GetAddrMode() == Offset)); 2034 ITScope it_scope(this, &cond, can_use_it); 2035 ldrh(cond, rt, operand); 2036 } 2037 void Ldrh(Register rt, const MemOperand& operand) { Ldrh(al, rt, operand); } 2038 2039 void Ldrh(Condition cond, Register rt, Label* label) { 2040 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2041 VIXL_ASSERT(allow_macro_instructions_); 2042 VIXL_ASSERT(OutsideITBlock()); 2043 MacroEmissionCheckScope guard(this); 2044 ITScope it_scope(this, &cond); 2045 ldrh(cond, rt, label); 2046 } 2047 void Ldrh(Register rt, Label* label) { Ldrh(al, rt, label); } 2048 2049 void Ldrsb(Condition cond, Register rt, const MemOperand& operand) { 2050 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2051 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2052 VIXL_ASSERT(allow_macro_instructions_); 2053 VIXL_ASSERT(OutsideITBlock()); 2054 MacroEmissionCheckScope guard(this); 2055 bool can_use_it = 2056 // LDRSB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2057 operand.IsPlainRegister() && rt.IsLow() && 2058 operand.GetBaseRegister().IsLow() && 2059 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2060 (operand.GetAddrMode() == Offset); 2061 ITScope it_scope(this, &cond, can_use_it); 2062 ldrsb(cond, rt, operand); 2063 } 2064 void Ldrsb(Register rt, const MemOperand& operand) { Ldrsb(al, rt, operand); } 2065 2066 void Ldrsb(Condition cond, Register rt, Label* label) { 2067 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2068 VIXL_ASSERT(allow_macro_instructions_); 2069 VIXL_ASSERT(OutsideITBlock()); 2070 MacroEmissionCheckScope guard(this); 2071 ITScope it_scope(this, &cond); 2072 ldrsb(cond, rt, label); 2073 } 2074 void Ldrsb(Register rt, Label* label) { Ldrsb(al, rt, label); } 2075 2076 void Ldrsh(Condition cond, Register rt, const MemOperand& operand) { 2077 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2078 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2079 VIXL_ASSERT(allow_macro_instructions_); 2080 VIXL_ASSERT(OutsideITBlock()); 2081 MacroEmissionCheckScope guard(this); 2082 bool can_use_it = 2083 // LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2084 operand.IsPlainRegister() && rt.IsLow() && 2085 operand.GetBaseRegister().IsLow() && 2086 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2087 (operand.GetAddrMode() == Offset); 2088 ITScope it_scope(this, &cond, can_use_it); 2089 ldrsh(cond, rt, operand); 2090 } 2091 void Ldrsh(Register rt, const MemOperand& operand) { Ldrsh(al, rt, operand); } 2092 2093 void Ldrsh(Condition cond, Register rt, Label* label) { 2094 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2095 VIXL_ASSERT(allow_macro_instructions_); 2096 VIXL_ASSERT(OutsideITBlock()); 2097 MacroEmissionCheckScope guard(this); 2098 ITScope it_scope(this, &cond); 2099 ldrsh(cond, rt, label); 2100 } 2101 void Ldrsh(Register rt, Label* label) { Ldrsh(al, rt, label); } 2102 2103 void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 2104 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2105 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2106 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2107 VIXL_ASSERT(allow_macro_instructions_); 2108 VIXL_ASSERT(OutsideITBlock()); 2109 MacroEmissionCheckScope guard(this); 2110 bool can_use_it = 2111 // LSL<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 2112 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2113 (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) || 2114 // LSL<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 2115 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 2116 operand.GetBaseRegister().IsLow()); 2117 ITScope it_scope(this, &cond, can_use_it); 2118 lsl(cond, rd, rm, operand); 2119 } 2120 void Lsl(Register rd, Register rm, const Operand& operand) { 2121 Lsl(al, rd, rm, operand); 2122 } 2123 void Lsl(FlagsUpdate flags, 2124 Condition cond, 2125 Register rd, 2126 Register rm, 2127 const Operand& operand) { 2128 switch (flags) { 2129 case LeaveFlags: 2130 Lsl(cond, rd, rm, operand); 2131 break; 2132 case SetFlags: 2133 Lsls(cond, rd, rm, operand); 2134 break; 2135 case DontCare: 2136 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2137 rm.IsLow() && operand.IsImmediate() && 2138 (operand.GetImmediate() < 32) && 2139 (operand.GetImmediate() != 0); 2140 if (can_be_16bit_encoded) { 2141 Lsls(cond, rd, rm, operand); 2142 } else { 2143 Lsl(cond, rd, rm, operand); 2144 } 2145 break; 2146 } 2147 } 2148 void Lsl(FlagsUpdate flags, 2149 Register rd, 2150 Register rm, 2151 const Operand& operand) { 2152 Lsl(flags, al, rd, rm, operand); 2153 } 2154 2155 void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 2156 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2157 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2158 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2159 VIXL_ASSERT(allow_macro_instructions_); 2160 VIXL_ASSERT(OutsideITBlock()); 2161 MacroEmissionCheckScope guard(this); 2162 ITScope it_scope(this, &cond); 2163 lsls(cond, rd, rm, operand); 2164 } 2165 void Lsls(Register rd, Register rm, const Operand& operand) { 2166 Lsls(al, rd, rm, operand); 2167 } 2168 2169 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 2170 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2171 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2172 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2173 VIXL_ASSERT(allow_macro_instructions_); 2174 VIXL_ASSERT(OutsideITBlock()); 2175 MacroEmissionCheckScope guard(this); 2176 bool can_use_it = 2177 // LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 2178 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2179 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || 2180 // LSR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 2181 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 2182 operand.GetBaseRegister().IsLow()); 2183 ITScope it_scope(this, &cond, can_use_it); 2184 lsr(cond, rd, rm, operand); 2185 } 2186 void Lsr(Register rd, Register rm, const Operand& operand) { 2187 Lsr(al, rd, rm, operand); 2188 } 2189 void Lsr(FlagsUpdate flags, 2190 Condition cond, 2191 Register rd, 2192 Register rm, 2193 const Operand& operand) { 2194 switch (flags) { 2195 case LeaveFlags: 2196 Lsr(cond, rd, rm, operand); 2197 break; 2198 case SetFlags: 2199 Lsrs(cond, rd, rm, operand); 2200 break; 2201 case DontCare: 2202 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2203 rm.IsLow() && operand.IsImmediate() && 2204 (operand.GetImmediate() < 32); 2205 if (can_be_16bit_encoded) { 2206 Lsrs(cond, rd, rm, operand); 2207 } else { 2208 Lsr(cond, rd, rm, operand); 2209 } 2210 break; 2211 } 2212 } 2213 void Lsr(FlagsUpdate flags, 2214 Register rd, 2215 Register rm, 2216 const Operand& operand) { 2217 Lsr(flags, al, rd, rm, operand); 2218 } 2219 2220 void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2221 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2222 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2223 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2224 VIXL_ASSERT(allow_macro_instructions_); 2225 VIXL_ASSERT(OutsideITBlock()); 2226 MacroEmissionCheckScope guard(this); 2227 ITScope it_scope(this, &cond); 2228 lsrs(cond, rd, rm, operand); 2229 } 2230 void Lsrs(Register rd, Register rm, const Operand& operand) { 2231 Lsrs(al, rd, rm, operand); 2232 } 2233 2234 void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) { 2235 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2236 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2237 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2238 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 2239 VIXL_ASSERT(allow_macro_instructions_); 2240 VIXL_ASSERT(OutsideITBlock()); 2241 MacroEmissionCheckScope guard(this); 2242 ITScope it_scope(this, &cond); 2243 mla(cond, rd, rn, rm, ra); 2244 } 2245 void Mla(Register rd, Register rn, Register rm, Register ra) { 2246 Mla(al, rd, rn, rm, ra); 2247 } 2248 void Mla(FlagsUpdate flags, 2249 Condition cond, 2250 Register rd, 2251 Register rn, 2252 Register rm, 2253 Register ra) { 2254 switch (flags) { 2255 case LeaveFlags: 2256 Mla(cond, rd, rn, rm, ra); 2257 break; 2258 case SetFlags: 2259 Mlas(cond, rd, rn, rm, ra); 2260 break; 2261 case DontCare: 2262 Mla(cond, rd, rn, rm, ra); 2263 break; 2264 } 2265 } 2266 void Mla( 2267 FlagsUpdate flags, Register rd, Register rn, Register rm, Register ra) { 2268 Mla(flags, al, rd, rn, rm, ra); 2269 } 2270 2271 void Mlas( 2272 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2273 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2274 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2275 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2276 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 2277 VIXL_ASSERT(allow_macro_instructions_); 2278 VIXL_ASSERT(OutsideITBlock()); 2279 MacroEmissionCheckScope guard(this); 2280 ITScope it_scope(this, &cond); 2281 mlas(cond, rd, rn, rm, ra); 2282 } 2283 void Mlas(Register rd, Register rn, Register rm, Register ra) { 2284 Mlas(al, rd, rn, rm, ra); 2285 } 2286 2287 void Mls(Condition cond, Register rd, Register rn, Register rm, Register ra) { 2288 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2289 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2290 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2291 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 2292 VIXL_ASSERT(allow_macro_instructions_); 2293 VIXL_ASSERT(OutsideITBlock()); 2294 MacroEmissionCheckScope guard(this); 2295 ITScope it_scope(this, &cond); 2296 mls(cond, rd, rn, rm, ra); 2297 } 2298 void Mls(Register rd, Register rn, Register rm, Register ra) { 2299 Mls(al, rd, rn, rm, ra); 2300 } 2301 2302 void Mov(Condition cond, Register rd, const Operand& operand) { 2303 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2304 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2305 VIXL_ASSERT(allow_macro_instructions_); 2306 VIXL_ASSERT(OutsideITBlock()); 2307 MacroEmissionCheckScope guard(this); 2308 bool can_use_it = 2309 // MOV<c>{<q>} <Rd>, #<imm8> ; T1 2310 (operand.IsImmediate() && rd.IsLow() && 2311 (operand.GetImmediate() <= 255)) || 2312 // MOV{<c>}{<q>} <Rd>, <Rm> ; T1 2313 (operand.IsPlainRegister() && !rd.IsPC() && 2314 !operand.GetBaseRegister().IsPC()) || 2315 // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} ; T2 2316 (operand.IsImmediateShiftedRegister() && rd.IsLow() && 2317 operand.GetBaseRegister().IsLow() && 2318 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) || 2319 operand.GetShift().Is(ASR))) || 2320 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 2321 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 2322 // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 2323 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 2324 (operand.IsRegisterShiftedRegister() && 2325 rd.Is(operand.GetBaseRegister()) && rd.IsLow() && 2326 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) || 2327 operand.GetShift().Is(ASR) || operand.GetShift().Is(ROR)) && 2328 operand.GetShiftRegister().IsLow()); 2329 ITScope it_scope(this, &cond, can_use_it); 2330 mov(cond, rd, operand); 2331 } 2332 void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); } 2333 void Mov(FlagsUpdate flags, 2334 Condition cond, 2335 Register rd, 2336 const Operand& operand) { 2337 switch (flags) { 2338 case LeaveFlags: 2339 Mov(cond, rd, operand); 2340 break; 2341 case SetFlags: 2342 Movs(cond, rd, operand); 2343 break; 2344 case DontCare: 2345 bool can_be_16bit_encoded = 2346 IsUsingT32() && cond.Is(al) && 2347 ((operand.IsImmediateShiftedRegister() && rd.IsLow() && 2348 operand.GetBaseRegister().IsLow() && 2349 (operand.GetShiftAmount() < 32) && 2350 (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() || 2351 operand.GetShift().IsASR())) || 2352 (operand.IsRegisterShiftedRegister() && rd.IsLow() && 2353 operand.GetBaseRegister().Is(rd) && 2354 operand.GetShiftRegister().IsLow() && 2355 (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() || 2356 operand.GetShift().IsASR() || operand.GetShift().IsROR())) || 2357 (operand.IsImmediate() && rd.IsLow() && 2358 (operand.GetImmediate() < 256))); 2359 if (can_be_16bit_encoded) { 2360 Movs(cond, rd, operand); 2361 } else { 2362 Mov(cond, rd, operand); 2363 } 2364 break; 2365 } 2366 } 2367 void Mov(FlagsUpdate flags, Register rd, const Operand& operand) { 2368 Mov(flags, al, rd, operand); 2369 } 2370 2371 void Movs(Condition cond, Register rd, const Operand& operand) { 2372 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2373 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2374 VIXL_ASSERT(allow_macro_instructions_); 2375 VIXL_ASSERT(OutsideITBlock()); 2376 MacroEmissionCheckScope guard(this); 2377 ITScope it_scope(this, &cond); 2378 movs(cond, rd, operand); 2379 } 2380 void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); } 2381 2382 void Movt(Condition cond, Register rd, const Operand& operand) { 2383 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2384 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2385 VIXL_ASSERT(allow_macro_instructions_); 2386 VIXL_ASSERT(OutsideITBlock()); 2387 MacroEmissionCheckScope guard(this); 2388 ITScope it_scope(this, &cond); 2389 movt(cond, rd, operand); 2390 } 2391 void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); } 2392 2393 void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) { 2394 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2395 VIXL_ASSERT(allow_macro_instructions_); 2396 VIXL_ASSERT(OutsideITBlock()); 2397 MacroEmissionCheckScope guard(this); 2398 ITScope it_scope(this, &cond); 2399 mrs(cond, rd, spec_reg); 2400 } 2401 void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); } 2402 2403 void Msr(Condition cond, 2404 MaskedSpecialRegister spec_reg, 2405 const Operand& operand) { 2406 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2407 VIXL_ASSERT(allow_macro_instructions_); 2408 VIXL_ASSERT(OutsideITBlock()); 2409 MacroEmissionCheckScope guard(this); 2410 ITScope it_scope(this, &cond); 2411 msr(cond, spec_reg, operand); 2412 } 2413 void Msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2414 Msr(al, spec_reg, operand); 2415 } 2416 2417 void Mul(Condition cond, Register rd, Register rn, Register rm) { 2418 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2419 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2420 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2421 VIXL_ASSERT(allow_macro_instructions_); 2422 VIXL_ASSERT(OutsideITBlock()); 2423 MacroEmissionCheckScope guard(this); 2424 bool can_use_it = 2425 // MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>} ; T1 2426 rd.Is(rm) && rn.IsLow() && rm.IsLow(); 2427 ITScope it_scope(this, &cond, can_use_it); 2428 mul(cond, rd, rn, rm); 2429 } 2430 void Mul(Register rd, Register rn, Register rm) { Mul(al, rd, rn, rm); } 2431 void Mul(FlagsUpdate flags, 2432 Condition cond, 2433 Register rd, 2434 Register rn, 2435 Register rm) { 2436 switch (flags) { 2437 case LeaveFlags: 2438 Mul(cond, rd, rn, rm); 2439 break; 2440 case SetFlags: 2441 Muls(cond, rd, rn, rm); 2442 break; 2443 case DontCare: 2444 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2445 rn.IsLow() && rm.Is(rd); 2446 if (can_be_16bit_encoded) { 2447 Muls(cond, rd, rn, rm); 2448 } else { 2449 Mul(cond, rd, rn, rm); 2450 } 2451 break; 2452 } 2453 } 2454 void Mul(FlagsUpdate flags, Register rd, Register rn, Register rm) { 2455 Mul(flags, al, rd, rn, rm); 2456 } 2457 2458 void Muls(Condition cond, Register rd, Register rn, Register rm) { 2459 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2460 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2461 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2462 VIXL_ASSERT(allow_macro_instructions_); 2463 VIXL_ASSERT(OutsideITBlock()); 2464 MacroEmissionCheckScope guard(this); 2465 ITScope it_scope(this, &cond); 2466 muls(cond, rd, rn, rm); 2467 } 2468 void Muls(Register rd, Register rn, Register rm) { Muls(al, rd, rn, rm); } 2469 2470 void Mvn(Condition cond, Register rd, const Operand& operand) { 2471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2472 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2473 VIXL_ASSERT(allow_macro_instructions_); 2474 VIXL_ASSERT(OutsideITBlock()); 2475 MacroEmissionCheckScope guard(this); 2476 bool can_use_it = 2477 // MVN<c>{<q>} <Rd>, <Rm> ; T1 2478 operand.IsPlainRegister() && rd.IsLow() && 2479 operand.GetBaseRegister().IsLow(); 2480 ITScope it_scope(this, &cond, can_use_it); 2481 mvn(cond, rd, operand); 2482 } 2483 void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); } 2484 void Mvn(FlagsUpdate flags, 2485 Condition cond, 2486 Register rd, 2487 const Operand& operand) { 2488 switch (flags) { 2489 case LeaveFlags: 2490 Mvn(cond, rd, operand); 2491 break; 2492 case SetFlags: 2493 Mvns(cond, rd, operand); 2494 break; 2495 case DontCare: 2496 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2497 operand.IsPlainRegister() && 2498 operand.GetBaseRegister().IsLow(); 2499 if (can_be_16bit_encoded) { 2500 Mvns(cond, rd, operand); 2501 } else { 2502 Mvn(cond, rd, operand); 2503 } 2504 break; 2505 } 2506 } 2507 void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) { 2508 Mvn(flags, al, rd, operand); 2509 } 2510 2511 void Mvns(Condition cond, Register rd, const Operand& operand) { 2512 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2513 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2514 VIXL_ASSERT(allow_macro_instructions_); 2515 VIXL_ASSERT(OutsideITBlock()); 2516 MacroEmissionCheckScope guard(this); 2517 ITScope it_scope(this, &cond); 2518 mvns(cond, rd, operand); 2519 } 2520 void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); } 2521 2522 void Nop(Condition cond) { 2523 VIXL_ASSERT(allow_macro_instructions_); 2524 VIXL_ASSERT(OutsideITBlock()); 2525 MacroEmissionCheckScope guard(this); 2526 ITScope it_scope(this, &cond); 2527 nop(cond); 2528 } 2529 void Nop() { Nop(al); } 2530 2531 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { 2532 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2533 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2534 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2535 VIXL_ASSERT(allow_macro_instructions_); 2536 VIXL_ASSERT(OutsideITBlock()); 2537 MacroEmissionCheckScope guard(this); 2538 if (cond.Is(al) && operand.IsImmediate()) { 2539 uint32_t immediate = operand.GetImmediate(); 2540 if (immediate == 0) { 2541 mvn(rd, 0); 2542 return; 2543 } 2544 if ((immediate == 0xffffffff) && rd.Is(rn)) { 2545 return; 2546 } 2547 } 2548 ITScope it_scope(this, &cond); 2549 orn(cond, rd, rn, operand); 2550 } 2551 void Orn(Register rd, Register rn, const Operand& operand) { 2552 Orn(al, rd, rn, operand); 2553 } 2554 void Orn(FlagsUpdate flags, 2555 Condition cond, 2556 Register rd, 2557 Register rn, 2558 const Operand& operand) { 2559 switch (flags) { 2560 case LeaveFlags: 2561 Orn(cond, rd, rn, operand); 2562 break; 2563 case SetFlags: 2564 Orns(cond, rd, rn, operand); 2565 break; 2566 case DontCare: 2567 Orn(cond, rd, rn, operand); 2568 break; 2569 } 2570 } 2571 void Orn(FlagsUpdate flags, 2572 Register rd, 2573 Register rn, 2574 const Operand& operand) { 2575 Orn(flags, al, rd, rn, operand); 2576 } 2577 2578 void Orns(Condition cond, Register rd, Register rn, const Operand& operand) { 2579 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2580 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2581 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2582 VIXL_ASSERT(allow_macro_instructions_); 2583 VIXL_ASSERT(OutsideITBlock()); 2584 MacroEmissionCheckScope guard(this); 2585 ITScope it_scope(this, &cond); 2586 orns(cond, rd, rn, operand); 2587 } 2588 void Orns(Register rd, Register rn, const Operand& operand) { 2589 Orns(al, rd, rn, operand); 2590 } 2591 2592 void Orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2593 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2594 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2595 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2596 VIXL_ASSERT(allow_macro_instructions_); 2597 VIXL_ASSERT(OutsideITBlock()); 2598 MacroEmissionCheckScope guard(this); 2599 if (cond.Is(al) && operand.IsImmediate()) { 2600 uint32_t immediate = operand.GetImmediate(); 2601 if ((immediate == 0) && rd.Is(rn)) { 2602 return; 2603 } 2604 if (immediate == 0xffffffff) { 2605 mvn(rd, 0); 2606 return; 2607 } 2608 } 2609 bool can_use_it = 2610 // ORR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 2611 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 2612 operand.GetBaseRegister().IsLow(); 2613 ITScope it_scope(this, &cond, can_use_it); 2614 orr(cond, rd, rn, operand); 2615 } 2616 void Orr(Register rd, Register rn, const Operand& operand) { 2617 Orr(al, rd, rn, operand); 2618 } 2619 void Orr(FlagsUpdate flags, 2620 Condition cond, 2621 Register rd, 2622 Register rn, 2623 const Operand& operand) { 2624 switch (flags) { 2625 case LeaveFlags: 2626 Orr(cond, rd, rn, operand); 2627 break; 2628 case SetFlags: 2629 Orrs(cond, rd, rn, operand); 2630 break; 2631 case DontCare: 2632 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2633 rn.Is(rd) && operand.IsPlainRegister() && 2634 operand.GetBaseRegister().IsLow(); 2635 if (can_be_16bit_encoded) { 2636 Orrs(cond, rd, rn, operand); 2637 } else { 2638 Orr(cond, rd, rn, operand); 2639 } 2640 break; 2641 } 2642 } 2643 void Orr(FlagsUpdate flags, 2644 Register rd, 2645 Register rn, 2646 const Operand& operand) { 2647 Orr(flags, al, rd, rn, operand); 2648 } 2649 2650 void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2651 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2652 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2653 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2654 VIXL_ASSERT(allow_macro_instructions_); 2655 VIXL_ASSERT(OutsideITBlock()); 2656 MacroEmissionCheckScope guard(this); 2657 ITScope it_scope(this, &cond); 2658 orrs(cond, rd, rn, operand); 2659 } 2660 void Orrs(Register rd, Register rn, const Operand& operand) { 2661 Orrs(al, rd, rn, operand); 2662 } 2663 2664 void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) { 2665 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2666 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2667 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2668 VIXL_ASSERT(allow_macro_instructions_); 2669 VIXL_ASSERT(OutsideITBlock()); 2670 MacroEmissionCheckScope guard(this); 2671 ITScope it_scope(this, &cond); 2672 pkhbt(cond, rd, rn, operand); 2673 } 2674 void Pkhbt(Register rd, Register rn, const Operand& operand) { 2675 Pkhbt(al, rd, rn, operand); 2676 } 2677 2678 void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) { 2679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2680 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2681 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2682 VIXL_ASSERT(allow_macro_instructions_); 2683 VIXL_ASSERT(OutsideITBlock()); 2684 MacroEmissionCheckScope guard(this); 2685 ITScope it_scope(this, &cond); 2686 pkhtb(cond, rd, rn, operand); 2687 } 2688 void Pkhtb(Register rd, Register rn, const Operand& operand) { 2689 Pkhtb(al, rd, rn, operand); 2690 } 2691 2692 void Pld(Condition cond, Label* label) { 2693 VIXL_ASSERT(allow_macro_instructions_); 2694 VIXL_ASSERT(OutsideITBlock()); 2695 MacroEmissionCheckScope guard(this); 2696 ITScope it_scope(this, &cond); 2697 pld(cond, label); 2698 } 2699 void Pld(Label* label) { Pld(al, label); } 2700 2701 void Pld(Condition cond, const MemOperand& operand) { 2702 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2703 VIXL_ASSERT(allow_macro_instructions_); 2704 VIXL_ASSERT(OutsideITBlock()); 2705 MacroEmissionCheckScope guard(this); 2706 ITScope it_scope(this, &cond); 2707 pld(cond, operand); 2708 } 2709 void Pld(const MemOperand& operand) { Pld(al, operand); } 2710 2711 void Pldw(Condition cond, const MemOperand& operand) { 2712 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2713 VIXL_ASSERT(allow_macro_instructions_); 2714 VIXL_ASSERT(OutsideITBlock()); 2715 MacroEmissionCheckScope guard(this); 2716 ITScope it_scope(this, &cond); 2717 pldw(cond, operand); 2718 } 2719 void Pldw(const MemOperand& operand) { Pldw(al, operand); } 2720 2721 void Pli(Condition cond, const MemOperand& operand) { 2722 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2723 VIXL_ASSERT(allow_macro_instructions_); 2724 VIXL_ASSERT(OutsideITBlock()); 2725 MacroEmissionCheckScope guard(this); 2726 ITScope it_scope(this, &cond); 2727 pli(cond, operand); 2728 } 2729 void Pli(const MemOperand& operand) { Pli(al, operand); } 2730 2731 void Pli(Condition cond, Label* label) { 2732 VIXL_ASSERT(allow_macro_instructions_); 2733 VIXL_ASSERT(OutsideITBlock()); 2734 MacroEmissionCheckScope guard(this); 2735 ITScope it_scope(this, &cond); 2736 pli(cond, label); 2737 } 2738 void Pli(Label* label) { Pli(al, label); } 2739 2740 void Pop(Condition cond, RegisterList registers) { 2741 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2742 VIXL_ASSERT(allow_macro_instructions_); 2743 VIXL_ASSERT(OutsideITBlock()); 2744 MacroEmissionCheckScope guard(this); 2745 ITScope it_scope(this, &cond); 2746 pop(cond, registers); 2747 } 2748 void Pop(RegisterList registers) { Pop(al, registers); } 2749 2750 void Pop(Condition cond, Register rt) { 2751 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2752 VIXL_ASSERT(allow_macro_instructions_); 2753 VIXL_ASSERT(OutsideITBlock()); 2754 MacroEmissionCheckScope guard(this); 2755 ITScope it_scope(this, &cond); 2756 pop(cond, rt); 2757 } 2758 void Pop(Register rt) { Pop(al, rt); } 2759 2760 void Push(Condition cond, RegisterList registers) { 2761 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2762 VIXL_ASSERT(allow_macro_instructions_); 2763 VIXL_ASSERT(OutsideITBlock()); 2764 MacroEmissionCheckScope guard(this); 2765 ITScope it_scope(this, &cond); 2766 push(cond, registers); 2767 } 2768 void Push(RegisterList registers) { Push(al, registers); } 2769 2770 void Push(Condition cond, Register rt) { 2771 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2772 VIXL_ASSERT(allow_macro_instructions_); 2773 VIXL_ASSERT(OutsideITBlock()); 2774 MacroEmissionCheckScope guard(this); 2775 ITScope it_scope(this, &cond); 2776 push(cond, rt); 2777 } 2778 void Push(Register rt) { Push(al, rt); } 2779 2780 void Qadd(Condition cond, Register rd, Register rm, Register rn) { 2781 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2782 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2783 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2784 VIXL_ASSERT(allow_macro_instructions_); 2785 VIXL_ASSERT(OutsideITBlock()); 2786 MacroEmissionCheckScope guard(this); 2787 ITScope it_scope(this, &cond); 2788 qadd(cond, rd, rm, rn); 2789 } 2790 void Qadd(Register rd, Register rm, Register rn) { Qadd(al, rd, rm, rn); } 2791 2792 void Qadd16(Condition cond, Register rd, Register rn, Register rm) { 2793 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2794 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2795 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2796 VIXL_ASSERT(allow_macro_instructions_); 2797 VIXL_ASSERT(OutsideITBlock()); 2798 MacroEmissionCheckScope guard(this); 2799 ITScope it_scope(this, &cond); 2800 qadd16(cond, rd, rn, rm); 2801 } 2802 void Qadd16(Register rd, Register rn, Register rm) { Qadd16(al, rd, rn, rm); } 2803 2804 void Qadd8(Condition cond, Register rd, Register rn, Register rm) { 2805 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2806 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2807 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2808 VIXL_ASSERT(allow_macro_instructions_); 2809 VIXL_ASSERT(OutsideITBlock()); 2810 MacroEmissionCheckScope guard(this); 2811 ITScope it_scope(this, &cond); 2812 qadd8(cond, rd, rn, rm); 2813 } 2814 void Qadd8(Register rd, Register rn, Register rm) { Qadd8(al, rd, rn, rm); } 2815 2816 void Qasx(Condition cond, Register rd, Register rn, Register rm) { 2817 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2818 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2819 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2820 VIXL_ASSERT(allow_macro_instructions_); 2821 VIXL_ASSERT(OutsideITBlock()); 2822 MacroEmissionCheckScope guard(this); 2823 ITScope it_scope(this, &cond); 2824 qasx(cond, rd, rn, rm); 2825 } 2826 void Qasx(Register rd, Register rn, Register rm) { Qasx(al, rd, rn, rm); } 2827 2828 void Qdadd(Condition cond, Register rd, Register rm, Register rn) { 2829 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2830 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2831 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2832 VIXL_ASSERT(allow_macro_instructions_); 2833 VIXL_ASSERT(OutsideITBlock()); 2834 MacroEmissionCheckScope guard(this); 2835 ITScope it_scope(this, &cond); 2836 qdadd(cond, rd, rm, rn); 2837 } 2838 void Qdadd(Register rd, Register rm, Register rn) { Qdadd(al, rd, rm, rn); } 2839 2840 void Qdsub(Condition cond, Register rd, Register rm, Register rn) { 2841 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2842 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2843 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2844 VIXL_ASSERT(allow_macro_instructions_); 2845 VIXL_ASSERT(OutsideITBlock()); 2846 MacroEmissionCheckScope guard(this); 2847 ITScope it_scope(this, &cond); 2848 qdsub(cond, rd, rm, rn); 2849 } 2850 void Qdsub(Register rd, Register rm, Register rn) { Qdsub(al, rd, rm, rn); } 2851 2852 void Qsax(Condition cond, Register rd, Register rn, Register rm) { 2853 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2854 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2856 VIXL_ASSERT(allow_macro_instructions_); 2857 VIXL_ASSERT(OutsideITBlock()); 2858 MacroEmissionCheckScope guard(this); 2859 ITScope it_scope(this, &cond); 2860 qsax(cond, rd, rn, rm); 2861 } 2862 void Qsax(Register rd, Register rn, Register rm) { Qsax(al, rd, rn, rm); } 2863 2864 void Qsub(Condition cond, Register rd, Register rm, Register rn) { 2865 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2867 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2868 VIXL_ASSERT(allow_macro_instructions_); 2869 VIXL_ASSERT(OutsideITBlock()); 2870 MacroEmissionCheckScope guard(this); 2871 ITScope it_scope(this, &cond); 2872 qsub(cond, rd, rm, rn); 2873 } 2874 void Qsub(Register rd, Register rm, Register rn) { Qsub(al, rd, rm, rn); } 2875 2876 void Qsub16(Condition cond, Register rd, Register rn, Register rm) { 2877 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2878 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2879 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2880 VIXL_ASSERT(allow_macro_instructions_); 2881 VIXL_ASSERT(OutsideITBlock()); 2882 MacroEmissionCheckScope guard(this); 2883 ITScope it_scope(this, &cond); 2884 qsub16(cond, rd, rn, rm); 2885 } 2886 void Qsub16(Register rd, Register rn, Register rm) { Qsub16(al, rd, rn, rm); } 2887 2888 void Qsub8(Condition cond, Register rd, Register rn, Register rm) { 2889 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2890 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2891 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2892 VIXL_ASSERT(allow_macro_instructions_); 2893 VIXL_ASSERT(OutsideITBlock()); 2894 MacroEmissionCheckScope guard(this); 2895 ITScope it_scope(this, &cond); 2896 qsub8(cond, rd, rn, rm); 2897 } 2898 void Qsub8(Register rd, Register rn, Register rm) { Qsub8(al, rd, rn, rm); } 2899 2900 void Rbit(Condition cond, Register rd, Register rm) { 2901 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2902 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2903 VIXL_ASSERT(allow_macro_instructions_); 2904 VIXL_ASSERT(OutsideITBlock()); 2905 MacroEmissionCheckScope guard(this); 2906 ITScope it_scope(this, &cond); 2907 rbit(cond, rd, rm); 2908 } 2909 void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); } 2910 2911 void Rev(Condition cond, Register rd, Register rm) { 2912 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2913 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2914 VIXL_ASSERT(allow_macro_instructions_); 2915 VIXL_ASSERT(OutsideITBlock()); 2916 MacroEmissionCheckScope guard(this); 2917 ITScope it_scope(this, &cond); 2918 rev(cond, rd, rm); 2919 } 2920 void Rev(Register rd, Register rm) { Rev(al, rd, rm); } 2921 2922 void Rev16(Condition cond, Register rd, Register rm) { 2923 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2924 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2925 VIXL_ASSERT(allow_macro_instructions_); 2926 VIXL_ASSERT(OutsideITBlock()); 2927 MacroEmissionCheckScope guard(this); 2928 ITScope it_scope(this, &cond); 2929 rev16(cond, rd, rm); 2930 } 2931 void Rev16(Register rd, Register rm) { Rev16(al, rd, rm); } 2932 2933 void Revsh(Condition cond, Register rd, Register rm) { 2934 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2935 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2936 VIXL_ASSERT(allow_macro_instructions_); 2937 VIXL_ASSERT(OutsideITBlock()); 2938 MacroEmissionCheckScope guard(this); 2939 ITScope it_scope(this, &cond); 2940 revsh(cond, rd, rm); 2941 } 2942 void Revsh(Register rd, Register rm) { Revsh(al, rd, rm); } 2943 2944 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) { 2945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2947 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2948 VIXL_ASSERT(allow_macro_instructions_); 2949 VIXL_ASSERT(OutsideITBlock()); 2950 MacroEmissionCheckScope guard(this); 2951 bool can_use_it = 2952 // ROR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 2953 operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 2954 operand.GetBaseRegister().IsLow(); 2955 ITScope it_scope(this, &cond, can_use_it); 2956 ror(cond, rd, rm, operand); 2957 } 2958 void Ror(Register rd, Register rm, const Operand& operand) { 2959 Ror(al, rd, rm, operand); 2960 } 2961 void Ror(FlagsUpdate flags, 2962 Condition cond, 2963 Register rd, 2964 Register rm, 2965 const Operand& operand) { 2966 switch (flags) { 2967 case LeaveFlags: 2968 Ror(cond, rd, rm, operand); 2969 break; 2970 case SetFlags: 2971 Rors(cond, rd, rm, operand); 2972 break; 2973 case DontCare: 2974 Ror(cond, rd, rm, operand); 2975 break; 2976 } 2977 } 2978 void Ror(FlagsUpdate flags, 2979 Register rd, 2980 Register rm, 2981 const Operand& operand) { 2982 Ror(flags, al, rd, rm, operand); 2983 } 2984 2985 void Rors(Condition cond, Register rd, Register rm, const Operand& operand) { 2986 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2987 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2988 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2989 VIXL_ASSERT(allow_macro_instructions_); 2990 VIXL_ASSERT(OutsideITBlock()); 2991 MacroEmissionCheckScope guard(this); 2992 ITScope it_scope(this, &cond); 2993 rors(cond, rd, rm, operand); 2994 } 2995 void Rors(Register rd, Register rm, const Operand& operand) { 2996 Rors(al, rd, rm, operand); 2997 } 2998 2999 void Rrx(Condition cond, Register rd, Register rm) { 3000 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3001 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3002 VIXL_ASSERT(allow_macro_instructions_); 3003 VIXL_ASSERT(OutsideITBlock()); 3004 MacroEmissionCheckScope guard(this); 3005 ITScope it_scope(this, &cond); 3006 rrx(cond, rd, rm); 3007 } 3008 void Rrx(Register rd, Register rm) { Rrx(al, rd, rm); } 3009 void Rrx(FlagsUpdate flags, Condition cond, Register rd, Register rm) { 3010 switch (flags) { 3011 case LeaveFlags: 3012 Rrx(cond, rd, rm); 3013 break; 3014 case SetFlags: 3015 Rrxs(cond, rd, rm); 3016 break; 3017 case DontCare: 3018 Rrx(cond, rd, rm); 3019 break; 3020 } 3021 } 3022 void Rrx(FlagsUpdate flags, Register rd, Register rm) { 3023 Rrx(flags, al, rd, rm); 3024 } 3025 3026 void Rrxs(Condition cond, Register rd, Register rm) { 3027 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3028 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3029 VIXL_ASSERT(allow_macro_instructions_); 3030 VIXL_ASSERT(OutsideITBlock()); 3031 MacroEmissionCheckScope guard(this); 3032 ITScope it_scope(this, &cond); 3033 rrxs(cond, rd, rm); 3034 } 3035 void Rrxs(Register rd, Register rm) { Rrxs(al, rd, rm); } 3036 3037 void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 3038 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3040 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3041 VIXL_ASSERT(allow_macro_instructions_); 3042 VIXL_ASSERT(OutsideITBlock()); 3043 MacroEmissionCheckScope guard(this); 3044 bool can_use_it = 3045 // RSB<c>{<q>} {<Rd>, }<Rn>, #0 ; T1 3046 operand.IsImmediate() && rd.IsLow() && rn.IsLow() && 3047 (operand.GetImmediate() == 0); 3048 ITScope it_scope(this, &cond, can_use_it); 3049 rsb(cond, rd, rn, operand); 3050 } 3051 void Rsb(Register rd, Register rn, const Operand& operand) { 3052 Rsb(al, rd, rn, operand); 3053 } 3054 void Rsb(FlagsUpdate flags, 3055 Condition cond, 3056 Register rd, 3057 Register rn, 3058 const Operand& operand) { 3059 switch (flags) { 3060 case LeaveFlags: 3061 Rsb(cond, rd, rn, operand); 3062 break; 3063 case SetFlags: 3064 Rsbs(cond, rd, rn, operand); 3065 break; 3066 case DontCare: 3067 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 3068 rn.IsLow() && operand.IsImmediate() && 3069 (operand.GetImmediate() == 0); 3070 if (can_be_16bit_encoded) { 3071 Rsbs(cond, rd, rn, operand); 3072 } else { 3073 Rsb(cond, rd, rn, operand); 3074 } 3075 break; 3076 } 3077 } 3078 void Rsb(FlagsUpdate flags, 3079 Register rd, 3080 Register rn, 3081 const Operand& operand) { 3082 Rsb(flags, al, rd, rn, operand); 3083 } 3084 3085 void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 3086 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3087 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3088 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3089 VIXL_ASSERT(allow_macro_instructions_); 3090 VIXL_ASSERT(OutsideITBlock()); 3091 MacroEmissionCheckScope guard(this); 3092 ITScope it_scope(this, &cond); 3093 rsbs(cond, rd, rn, operand); 3094 } 3095 void Rsbs(Register rd, Register rn, const Operand& operand) { 3096 Rsbs(al, rd, rn, operand); 3097 } 3098 3099 void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) { 3100 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3101 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3102 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3103 VIXL_ASSERT(allow_macro_instructions_); 3104 VIXL_ASSERT(OutsideITBlock()); 3105 MacroEmissionCheckScope guard(this); 3106 ITScope it_scope(this, &cond); 3107 rsc(cond, rd, rn, operand); 3108 } 3109 void Rsc(Register rd, Register rn, const Operand& operand) { 3110 Rsc(al, rd, rn, operand); 3111 } 3112 void Rsc(FlagsUpdate flags, 3113 Condition cond, 3114 Register rd, 3115 Register rn, 3116 const Operand& operand) { 3117 switch (flags) { 3118 case LeaveFlags: 3119 Rsc(cond, rd, rn, operand); 3120 break; 3121 case SetFlags: 3122 Rscs(cond, rd, rn, operand); 3123 break; 3124 case DontCare: 3125 Rsc(cond, rd, rn, operand); 3126 break; 3127 } 3128 } 3129 void Rsc(FlagsUpdate flags, 3130 Register rd, 3131 Register rn, 3132 const Operand& operand) { 3133 Rsc(flags, al, rd, rn, operand); 3134 } 3135 3136 void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) { 3137 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3138 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3139 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3140 VIXL_ASSERT(allow_macro_instructions_); 3141 VIXL_ASSERT(OutsideITBlock()); 3142 MacroEmissionCheckScope guard(this); 3143 ITScope it_scope(this, &cond); 3144 rscs(cond, rd, rn, operand); 3145 } 3146 void Rscs(Register rd, Register rn, const Operand& operand) { 3147 Rscs(al, rd, rn, operand); 3148 } 3149 3150 void Sadd16(Condition cond, Register rd, Register rn, Register rm) { 3151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3152 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3153 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3154 VIXL_ASSERT(allow_macro_instructions_); 3155 VIXL_ASSERT(OutsideITBlock()); 3156 MacroEmissionCheckScope guard(this); 3157 ITScope it_scope(this, &cond); 3158 sadd16(cond, rd, rn, rm); 3159 } 3160 void Sadd16(Register rd, Register rn, Register rm) { Sadd16(al, rd, rn, rm); } 3161 3162 void Sadd8(Condition cond, Register rd, Register rn, Register rm) { 3163 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3164 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3165 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3166 VIXL_ASSERT(allow_macro_instructions_); 3167 VIXL_ASSERT(OutsideITBlock()); 3168 MacroEmissionCheckScope guard(this); 3169 ITScope it_scope(this, &cond); 3170 sadd8(cond, rd, rn, rm); 3171 } 3172 void Sadd8(Register rd, Register rn, Register rm) { Sadd8(al, rd, rn, rm); } 3173 3174 void Sasx(Condition cond, Register rd, Register rn, Register rm) { 3175 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3176 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3177 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3178 VIXL_ASSERT(allow_macro_instructions_); 3179 VIXL_ASSERT(OutsideITBlock()); 3180 MacroEmissionCheckScope guard(this); 3181 ITScope it_scope(this, &cond); 3182 sasx(cond, rd, rn, rm); 3183 } 3184 void Sasx(Register rd, Register rn, Register rm) { Sasx(al, rd, rn, rm); } 3185 3186 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 3187 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3189 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3190 VIXL_ASSERT(allow_macro_instructions_); 3191 VIXL_ASSERT(OutsideITBlock()); 3192 MacroEmissionCheckScope guard(this); 3193 bool can_use_it = 3194 // SBC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 3195 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && 3196 operand.GetBaseRegister().IsLow(); 3197 ITScope it_scope(this, &cond, can_use_it); 3198 sbc(cond, rd, rn, operand); 3199 } 3200 void Sbc(Register rd, Register rn, const Operand& operand) { 3201 Sbc(al, rd, rn, operand); 3202 } 3203 void Sbc(FlagsUpdate flags, 3204 Condition cond, 3205 Register rd, 3206 Register rn, 3207 const Operand& operand) { 3208 switch (flags) { 3209 case LeaveFlags: 3210 Sbc(cond, rd, rn, operand); 3211 break; 3212 case SetFlags: 3213 Sbcs(cond, rd, rn, operand); 3214 break; 3215 case DontCare: 3216 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 3217 rn.Is(rd) && operand.IsPlainRegister() && 3218 operand.GetBaseRegister().IsLow(); 3219 if (can_be_16bit_encoded) { 3220 Sbcs(cond, rd, rn, operand); 3221 } else { 3222 Sbc(cond, rd, rn, operand); 3223 } 3224 break; 3225 } 3226 } 3227 void Sbc(FlagsUpdate flags, 3228 Register rd, 3229 Register rn, 3230 const Operand& operand) { 3231 Sbc(flags, al, rd, rn, operand); 3232 } 3233 3234 void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 3235 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3236 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3237 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3238 VIXL_ASSERT(allow_macro_instructions_); 3239 VIXL_ASSERT(OutsideITBlock()); 3240 MacroEmissionCheckScope guard(this); 3241 ITScope it_scope(this, &cond); 3242 sbcs(cond, rd, rn, operand); 3243 } 3244 void Sbcs(Register rd, Register rn, const Operand& operand) { 3245 Sbcs(al, rd, rn, operand); 3246 } 3247 3248 void Sbfx(Condition cond, 3249 Register rd, 3250 Register rn, 3251 uint32_t lsb, 3252 const Operand& operand) { 3253 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3254 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3255 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3256 VIXL_ASSERT(allow_macro_instructions_); 3257 VIXL_ASSERT(OutsideITBlock()); 3258 MacroEmissionCheckScope guard(this); 3259 ITScope it_scope(this, &cond); 3260 sbfx(cond, rd, rn, lsb, operand); 3261 } 3262 void Sbfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 3263 Sbfx(al, rd, rn, lsb, operand); 3264 } 3265 3266 void Sdiv(Condition cond, Register rd, Register rn, Register rm) { 3267 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3268 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3269 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3270 VIXL_ASSERT(allow_macro_instructions_); 3271 VIXL_ASSERT(OutsideITBlock()); 3272 MacroEmissionCheckScope guard(this); 3273 ITScope it_scope(this, &cond); 3274 sdiv(cond, rd, rn, rm); 3275 } 3276 void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); } 3277 3278 void Sel(Condition cond, Register rd, Register rn, Register rm) { 3279 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3280 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3281 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3282 VIXL_ASSERT(allow_macro_instructions_); 3283 VIXL_ASSERT(OutsideITBlock()); 3284 MacroEmissionCheckScope guard(this); 3285 ITScope it_scope(this, &cond); 3286 sel(cond, rd, rn, rm); 3287 } 3288 void Sel(Register rd, Register rn, Register rm) { Sel(al, rd, rn, rm); } 3289 3290 void Shadd16(Condition cond, Register rd, Register rn, Register rm) { 3291 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3292 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3293 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3294 VIXL_ASSERT(allow_macro_instructions_); 3295 VIXL_ASSERT(OutsideITBlock()); 3296 MacroEmissionCheckScope guard(this); 3297 ITScope it_scope(this, &cond); 3298 shadd16(cond, rd, rn, rm); 3299 } 3300 void Shadd16(Register rd, Register rn, Register rm) { 3301 Shadd16(al, rd, rn, rm); 3302 } 3303 3304 void Shadd8(Condition cond, Register rd, Register rn, Register rm) { 3305 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3306 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3307 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3308 VIXL_ASSERT(allow_macro_instructions_); 3309 VIXL_ASSERT(OutsideITBlock()); 3310 MacroEmissionCheckScope guard(this); 3311 ITScope it_scope(this, &cond); 3312 shadd8(cond, rd, rn, rm); 3313 } 3314 void Shadd8(Register rd, Register rn, Register rm) { Shadd8(al, rd, rn, rm); } 3315 3316 void Shasx(Condition cond, Register rd, Register rn, Register rm) { 3317 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3318 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3319 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3320 VIXL_ASSERT(allow_macro_instructions_); 3321 VIXL_ASSERT(OutsideITBlock()); 3322 MacroEmissionCheckScope guard(this); 3323 ITScope it_scope(this, &cond); 3324 shasx(cond, rd, rn, rm); 3325 } 3326 void Shasx(Register rd, Register rn, Register rm) { Shasx(al, rd, rn, rm); } 3327 3328 void Shsax(Condition cond, Register rd, Register rn, Register rm) { 3329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3330 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3331 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3332 VIXL_ASSERT(allow_macro_instructions_); 3333 VIXL_ASSERT(OutsideITBlock()); 3334 MacroEmissionCheckScope guard(this); 3335 ITScope it_scope(this, &cond); 3336 shsax(cond, rd, rn, rm); 3337 } 3338 void Shsax(Register rd, Register rn, Register rm) { Shsax(al, rd, rn, rm); } 3339 3340 void Shsub16(Condition cond, Register rd, Register rn, Register rm) { 3341 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3342 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3343 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3344 VIXL_ASSERT(allow_macro_instructions_); 3345 VIXL_ASSERT(OutsideITBlock()); 3346 MacroEmissionCheckScope guard(this); 3347 ITScope it_scope(this, &cond); 3348 shsub16(cond, rd, rn, rm); 3349 } 3350 void Shsub16(Register rd, Register rn, Register rm) { 3351 Shsub16(al, rd, rn, rm); 3352 } 3353 3354 void Shsub8(Condition cond, Register rd, Register rn, Register rm) { 3355 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3356 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3357 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3358 VIXL_ASSERT(allow_macro_instructions_); 3359 VIXL_ASSERT(OutsideITBlock()); 3360 MacroEmissionCheckScope guard(this); 3361 ITScope it_scope(this, &cond); 3362 shsub8(cond, rd, rn, rm); 3363 } 3364 void Shsub8(Register rd, Register rn, Register rm) { Shsub8(al, rd, rn, rm); } 3365 3366 void Smlabb( 3367 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3368 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3369 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3370 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3371 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3372 VIXL_ASSERT(allow_macro_instructions_); 3373 VIXL_ASSERT(OutsideITBlock()); 3374 MacroEmissionCheckScope guard(this); 3375 ITScope it_scope(this, &cond); 3376 smlabb(cond, rd, rn, rm, ra); 3377 } 3378 void Smlabb(Register rd, Register rn, Register rm, Register ra) { 3379 Smlabb(al, rd, rn, rm, ra); 3380 } 3381 3382 void Smlabt( 3383 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3384 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3385 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3386 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3387 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3388 VIXL_ASSERT(allow_macro_instructions_); 3389 VIXL_ASSERT(OutsideITBlock()); 3390 MacroEmissionCheckScope guard(this); 3391 ITScope it_scope(this, &cond); 3392 smlabt(cond, rd, rn, rm, ra); 3393 } 3394 void Smlabt(Register rd, Register rn, Register rm, Register ra) { 3395 Smlabt(al, rd, rn, rm, ra); 3396 } 3397 3398 void Smlad( 3399 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3400 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3401 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3402 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3403 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3404 VIXL_ASSERT(allow_macro_instructions_); 3405 VIXL_ASSERT(OutsideITBlock()); 3406 MacroEmissionCheckScope guard(this); 3407 ITScope it_scope(this, &cond); 3408 smlad(cond, rd, rn, rm, ra); 3409 } 3410 void Smlad(Register rd, Register rn, Register rm, Register ra) { 3411 Smlad(al, rd, rn, rm, ra); 3412 } 3413 3414 void Smladx( 3415 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3416 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3417 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3418 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3419 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3420 VIXL_ASSERT(allow_macro_instructions_); 3421 VIXL_ASSERT(OutsideITBlock()); 3422 MacroEmissionCheckScope guard(this); 3423 ITScope it_scope(this, &cond); 3424 smladx(cond, rd, rn, rm, ra); 3425 } 3426 void Smladx(Register rd, Register rn, Register rm, Register ra) { 3427 Smladx(al, rd, rn, rm, ra); 3428 } 3429 3430 void Smlal( 3431 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3432 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3433 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3434 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3435 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3436 VIXL_ASSERT(allow_macro_instructions_); 3437 VIXL_ASSERT(OutsideITBlock()); 3438 MacroEmissionCheckScope guard(this); 3439 ITScope it_scope(this, &cond); 3440 smlal(cond, rdlo, rdhi, rn, rm); 3441 } 3442 void Smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3443 Smlal(al, rdlo, rdhi, rn, rm); 3444 } 3445 3446 void Smlalbb( 3447 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3448 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3449 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3450 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3451 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3452 VIXL_ASSERT(allow_macro_instructions_); 3453 VIXL_ASSERT(OutsideITBlock()); 3454 MacroEmissionCheckScope guard(this); 3455 ITScope it_scope(this, &cond); 3456 smlalbb(cond, rdlo, rdhi, rn, rm); 3457 } 3458 void Smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 3459 Smlalbb(al, rdlo, rdhi, rn, rm); 3460 } 3461 3462 void Smlalbt( 3463 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3464 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3465 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3466 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3467 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3468 VIXL_ASSERT(allow_macro_instructions_); 3469 VIXL_ASSERT(OutsideITBlock()); 3470 MacroEmissionCheckScope guard(this); 3471 ITScope it_scope(this, &cond); 3472 smlalbt(cond, rdlo, rdhi, rn, rm); 3473 } 3474 void Smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 3475 Smlalbt(al, rdlo, rdhi, rn, rm); 3476 } 3477 3478 void Smlald( 3479 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3480 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3481 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3482 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3483 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3484 VIXL_ASSERT(allow_macro_instructions_); 3485 VIXL_ASSERT(OutsideITBlock()); 3486 MacroEmissionCheckScope guard(this); 3487 ITScope it_scope(this, &cond); 3488 smlald(cond, rdlo, rdhi, rn, rm); 3489 } 3490 void Smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 3491 Smlald(al, rdlo, rdhi, rn, rm); 3492 } 3493 3494 void Smlaldx( 3495 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3496 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3497 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3498 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3499 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3500 VIXL_ASSERT(allow_macro_instructions_); 3501 VIXL_ASSERT(OutsideITBlock()); 3502 MacroEmissionCheckScope guard(this); 3503 ITScope it_scope(this, &cond); 3504 smlaldx(cond, rdlo, rdhi, rn, rm); 3505 } 3506 void Smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3507 Smlaldx(al, rdlo, rdhi, rn, rm); 3508 } 3509 3510 void Smlals( 3511 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3512 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3513 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3514 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3515 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3516 VIXL_ASSERT(allow_macro_instructions_); 3517 VIXL_ASSERT(OutsideITBlock()); 3518 MacroEmissionCheckScope guard(this); 3519 ITScope it_scope(this, &cond); 3520 smlals(cond, rdlo, rdhi, rn, rm); 3521 } 3522 void Smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3523 Smlals(al, rdlo, rdhi, rn, rm); 3524 } 3525 3526 void Smlaltb( 3527 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3528 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3529 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3530 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3531 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3532 VIXL_ASSERT(allow_macro_instructions_); 3533 VIXL_ASSERT(OutsideITBlock()); 3534 MacroEmissionCheckScope guard(this); 3535 ITScope it_scope(this, &cond); 3536 smlaltb(cond, rdlo, rdhi, rn, rm); 3537 } 3538 void Smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 3539 Smlaltb(al, rdlo, rdhi, rn, rm); 3540 } 3541 3542 void Smlaltt( 3543 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3544 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3545 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3546 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3547 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3548 VIXL_ASSERT(allow_macro_instructions_); 3549 VIXL_ASSERT(OutsideITBlock()); 3550 MacroEmissionCheckScope guard(this); 3551 ITScope it_scope(this, &cond); 3552 smlaltt(cond, rdlo, rdhi, rn, rm); 3553 } 3554 void Smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 3555 Smlaltt(al, rdlo, rdhi, rn, rm); 3556 } 3557 3558 void Smlatb( 3559 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3560 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3561 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3562 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3563 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3564 VIXL_ASSERT(allow_macro_instructions_); 3565 VIXL_ASSERT(OutsideITBlock()); 3566 MacroEmissionCheckScope guard(this); 3567 ITScope it_scope(this, &cond); 3568 smlatb(cond, rd, rn, rm, ra); 3569 } 3570 void Smlatb(Register rd, Register rn, Register rm, Register ra) { 3571 Smlatb(al, rd, rn, rm, ra); 3572 } 3573 3574 void Smlatt( 3575 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3576 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3577 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3578 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3579 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3580 VIXL_ASSERT(allow_macro_instructions_); 3581 VIXL_ASSERT(OutsideITBlock()); 3582 MacroEmissionCheckScope guard(this); 3583 ITScope it_scope(this, &cond); 3584 smlatt(cond, rd, rn, rm, ra); 3585 } 3586 void Smlatt(Register rd, Register rn, Register rm, Register ra) { 3587 Smlatt(al, rd, rn, rm, ra); 3588 } 3589 3590 void Smlawb( 3591 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3592 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3593 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3594 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3595 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3596 VIXL_ASSERT(allow_macro_instructions_); 3597 VIXL_ASSERT(OutsideITBlock()); 3598 MacroEmissionCheckScope guard(this); 3599 ITScope it_scope(this, &cond); 3600 smlawb(cond, rd, rn, rm, ra); 3601 } 3602 void Smlawb(Register rd, Register rn, Register rm, Register ra) { 3603 Smlawb(al, rd, rn, rm, ra); 3604 } 3605 3606 void Smlawt( 3607 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3608 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3609 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3610 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3611 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3612 VIXL_ASSERT(allow_macro_instructions_); 3613 VIXL_ASSERT(OutsideITBlock()); 3614 MacroEmissionCheckScope guard(this); 3615 ITScope it_scope(this, &cond); 3616 smlawt(cond, rd, rn, rm, ra); 3617 } 3618 void Smlawt(Register rd, Register rn, Register rm, Register ra) { 3619 Smlawt(al, rd, rn, rm, ra); 3620 } 3621 3622 void Smlsd( 3623 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3624 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3625 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3626 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3627 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3628 VIXL_ASSERT(allow_macro_instructions_); 3629 VIXL_ASSERT(OutsideITBlock()); 3630 MacroEmissionCheckScope guard(this); 3631 ITScope it_scope(this, &cond); 3632 smlsd(cond, rd, rn, rm, ra); 3633 } 3634 void Smlsd(Register rd, Register rn, Register rm, Register ra) { 3635 Smlsd(al, rd, rn, rm, ra); 3636 } 3637 3638 void Smlsdx( 3639 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3640 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3641 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3642 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3643 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3644 VIXL_ASSERT(allow_macro_instructions_); 3645 VIXL_ASSERT(OutsideITBlock()); 3646 MacroEmissionCheckScope guard(this); 3647 ITScope it_scope(this, &cond); 3648 smlsdx(cond, rd, rn, rm, ra); 3649 } 3650 void Smlsdx(Register rd, Register rn, Register rm, Register ra) { 3651 Smlsdx(al, rd, rn, rm, ra); 3652 } 3653 3654 void Smlsld( 3655 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3656 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3657 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3658 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3659 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3660 VIXL_ASSERT(allow_macro_instructions_); 3661 VIXL_ASSERT(OutsideITBlock()); 3662 MacroEmissionCheckScope guard(this); 3663 ITScope it_scope(this, &cond); 3664 smlsld(cond, rdlo, rdhi, rn, rm); 3665 } 3666 void Smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 3667 Smlsld(al, rdlo, rdhi, rn, rm); 3668 } 3669 3670 void Smlsldx( 3671 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3672 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3673 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3674 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3675 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3676 VIXL_ASSERT(allow_macro_instructions_); 3677 VIXL_ASSERT(OutsideITBlock()); 3678 MacroEmissionCheckScope guard(this); 3679 ITScope it_scope(this, &cond); 3680 smlsldx(cond, rdlo, rdhi, rn, rm); 3681 } 3682 void Smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3683 Smlsldx(al, rdlo, rdhi, rn, rm); 3684 } 3685 3686 void Smmla( 3687 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3688 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3689 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3690 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3691 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3692 VIXL_ASSERT(allow_macro_instructions_); 3693 VIXL_ASSERT(OutsideITBlock()); 3694 MacroEmissionCheckScope guard(this); 3695 ITScope it_scope(this, &cond); 3696 smmla(cond, rd, rn, rm, ra); 3697 } 3698 void Smmla(Register rd, Register rn, Register rm, Register ra) { 3699 Smmla(al, rd, rn, rm, ra); 3700 } 3701 3702 void Smmlar( 3703 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3704 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3705 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3706 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3707 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3708 VIXL_ASSERT(allow_macro_instructions_); 3709 VIXL_ASSERT(OutsideITBlock()); 3710 MacroEmissionCheckScope guard(this); 3711 ITScope it_scope(this, &cond); 3712 smmlar(cond, rd, rn, rm, ra); 3713 } 3714 void Smmlar(Register rd, Register rn, Register rm, Register ra) { 3715 Smmlar(al, rd, rn, rm, ra); 3716 } 3717 3718 void Smmls( 3719 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3720 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3721 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3722 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3723 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3724 VIXL_ASSERT(allow_macro_instructions_); 3725 VIXL_ASSERT(OutsideITBlock()); 3726 MacroEmissionCheckScope guard(this); 3727 ITScope it_scope(this, &cond); 3728 smmls(cond, rd, rn, rm, ra); 3729 } 3730 void Smmls(Register rd, Register rn, Register rm, Register ra) { 3731 Smmls(al, rd, rn, rm, ra); 3732 } 3733 3734 void Smmlsr( 3735 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3736 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3737 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3738 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3739 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3740 VIXL_ASSERT(allow_macro_instructions_); 3741 VIXL_ASSERT(OutsideITBlock()); 3742 MacroEmissionCheckScope guard(this); 3743 ITScope it_scope(this, &cond); 3744 smmlsr(cond, rd, rn, rm, ra); 3745 } 3746 void Smmlsr(Register rd, Register rn, Register rm, Register ra) { 3747 Smmlsr(al, rd, rn, rm, ra); 3748 } 3749 3750 void Smmul(Condition cond, Register rd, Register rn, Register rm) { 3751 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3752 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3753 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3754 VIXL_ASSERT(allow_macro_instructions_); 3755 VIXL_ASSERT(OutsideITBlock()); 3756 MacroEmissionCheckScope guard(this); 3757 ITScope it_scope(this, &cond); 3758 smmul(cond, rd, rn, rm); 3759 } 3760 void Smmul(Register rd, Register rn, Register rm) { Smmul(al, rd, rn, rm); } 3761 3762 void Smmulr(Condition cond, Register rd, Register rn, Register rm) { 3763 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3764 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3765 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3766 VIXL_ASSERT(allow_macro_instructions_); 3767 VIXL_ASSERT(OutsideITBlock()); 3768 MacroEmissionCheckScope guard(this); 3769 ITScope it_scope(this, &cond); 3770 smmulr(cond, rd, rn, rm); 3771 } 3772 void Smmulr(Register rd, Register rn, Register rm) { Smmulr(al, rd, rn, rm); } 3773 3774 void Smuad(Condition cond, Register rd, Register rn, Register rm) { 3775 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3778 VIXL_ASSERT(allow_macro_instructions_); 3779 VIXL_ASSERT(OutsideITBlock()); 3780 MacroEmissionCheckScope guard(this); 3781 ITScope it_scope(this, &cond); 3782 smuad(cond, rd, rn, rm); 3783 } 3784 void Smuad(Register rd, Register rn, Register rm) { Smuad(al, rd, rn, rm); } 3785 3786 void Smuadx(Condition cond, Register rd, Register rn, Register rm) { 3787 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3789 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3790 VIXL_ASSERT(allow_macro_instructions_); 3791 VIXL_ASSERT(OutsideITBlock()); 3792 MacroEmissionCheckScope guard(this); 3793 ITScope it_scope(this, &cond); 3794 smuadx(cond, rd, rn, rm); 3795 } 3796 void Smuadx(Register rd, Register rn, Register rm) { Smuadx(al, rd, rn, rm); } 3797 3798 void Smulbb(Condition cond, Register rd, Register rn, Register rm) { 3799 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3800 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3801 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3802 VIXL_ASSERT(allow_macro_instructions_); 3803 VIXL_ASSERT(OutsideITBlock()); 3804 MacroEmissionCheckScope guard(this); 3805 ITScope it_scope(this, &cond); 3806 smulbb(cond, rd, rn, rm); 3807 } 3808 void Smulbb(Register rd, Register rn, Register rm) { Smulbb(al, rd, rn, rm); } 3809 3810 void Smulbt(Condition cond, Register rd, Register rn, Register rm) { 3811 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3812 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3813 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3814 VIXL_ASSERT(allow_macro_instructions_); 3815 VIXL_ASSERT(OutsideITBlock()); 3816 MacroEmissionCheckScope guard(this); 3817 ITScope it_scope(this, &cond); 3818 smulbt(cond, rd, rn, rm); 3819 } 3820 void Smulbt(Register rd, Register rn, Register rm) { Smulbt(al, rd, rn, rm); } 3821 3822 void Smull( 3823 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3824 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3825 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3826 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3827 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3828 VIXL_ASSERT(allow_macro_instructions_); 3829 VIXL_ASSERT(OutsideITBlock()); 3830 MacroEmissionCheckScope guard(this); 3831 ITScope it_scope(this, &cond); 3832 smull(cond, rdlo, rdhi, rn, rm); 3833 } 3834 void Smull(Register rdlo, Register rdhi, Register rn, Register rm) { 3835 Smull(al, rdlo, rdhi, rn, rm); 3836 } 3837 void Smull(FlagsUpdate flags, 3838 Condition cond, 3839 Register rdlo, 3840 Register rdhi, 3841 Register rn, 3842 Register rm) { 3843 switch (flags) { 3844 case LeaveFlags: 3845 Smull(cond, rdlo, rdhi, rn, rm); 3846 break; 3847 case SetFlags: 3848 Smulls(cond, rdlo, rdhi, rn, rm); 3849 break; 3850 case DontCare: 3851 Smull(cond, rdlo, rdhi, rn, rm); 3852 break; 3853 } 3854 } 3855 void Smull(FlagsUpdate flags, 3856 Register rdlo, 3857 Register rdhi, 3858 Register rn, 3859 Register rm) { 3860 Smull(flags, al, rdlo, rdhi, rn, rm); 3861 } 3862 3863 void Smulls( 3864 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3865 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3867 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3868 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3869 VIXL_ASSERT(allow_macro_instructions_); 3870 VIXL_ASSERT(OutsideITBlock()); 3871 MacroEmissionCheckScope guard(this); 3872 ITScope it_scope(this, &cond); 3873 smulls(cond, rdlo, rdhi, rn, rm); 3874 } 3875 void Smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3876 Smulls(al, rdlo, rdhi, rn, rm); 3877 } 3878 3879 void Smultb(Condition cond, Register rd, Register rn, Register rm) { 3880 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3882 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3883 VIXL_ASSERT(allow_macro_instructions_); 3884 VIXL_ASSERT(OutsideITBlock()); 3885 MacroEmissionCheckScope guard(this); 3886 ITScope it_scope(this, &cond); 3887 smultb(cond, rd, rn, rm); 3888 } 3889 void Smultb(Register rd, Register rn, Register rm) { Smultb(al, rd, rn, rm); } 3890 3891 void Smultt(Condition cond, Register rd, Register rn, Register rm) { 3892 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3893 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3894 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3895 VIXL_ASSERT(allow_macro_instructions_); 3896 VIXL_ASSERT(OutsideITBlock()); 3897 MacroEmissionCheckScope guard(this); 3898 ITScope it_scope(this, &cond); 3899 smultt(cond, rd, rn, rm); 3900 } 3901 void Smultt(Register rd, Register rn, Register rm) { Smultt(al, rd, rn, rm); } 3902 3903 void Smulwb(Condition cond, Register rd, Register rn, Register rm) { 3904 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3905 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3906 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3907 VIXL_ASSERT(allow_macro_instructions_); 3908 VIXL_ASSERT(OutsideITBlock()); 3909 MacroEmissionCheckScope guard(this); 3910 ITScope it_scope(this, &cond); 3911 smulwb(cond, rd, rn, rm); 3912 } 3913 void Smulwb(Register rd, Register rn, Register rm) { Smulwb(al, rd, rn, rm); } 3914 3915 void Smulwt(Condition cond, Register rd, Register rn, Register rm) { 3916 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3917 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3918 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3919 VIXL_ASSERT(allow_macro_instructions_); 3920 VIXL_ASSERT(OutsideITBlock()); 3921 MacroEmissionCheckScope guard(this); 3922 ITScope it_scope(this, &cond); 3923 smulwt(cond, rd, rn, rm); 3924 } 3925 void Smulwt(Register rd, Register rn, Register rm) { Smulwt(al, rd, rn, rm); } 3926 3927 void Smusd(Condition cond, Register rd, Register rn, Register rm) { 3928 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3929 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3930 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3931 VIXL_ASSERT(allow_macro_instructions_); 3932 VIXL_ASSERT(OutsideITBlock()); 3933 MacroEmissionCheckScope guard(this); 3934 ITScope it_scope(this, &cond); 3935 smusd(cond, rd, rn, rm); 3936 } 3937 void Smusd(Register rd, Register rn, Register rm) { Smusd(al, rd, rn, rm); } 3938 3939 void Smusdx(Condition cond, Register rd, Register rn, Register rm) { 3940 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3941 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3942 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3943 VIXL_ASSERT(allow_macro_instructions_); 3944 VIXL_ASSERT(OutsideITBlock()); 3945 MacroEmissionCheckScope guard(this); 3946 ITScope it_scope(this, &cond); 3947 smusdx(cond, rd, rn, rm); 3948 } 3949 void Smusdx(Register rd, Register rn, Register rm) { Smusdx(al, rd, rn, rm); } 3950 3951 void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) { 3952 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3953 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3954 VIXL_ASSERT(allow_macro_instructions_); 3955 VIXL_ASSERT(OutsideITBlock()); 3956 MacroEmissionCheckScope guard(this); 3957 ITScope it_scope(this, &cond); 3958 ssat(cond, rd, imm, operand); 3959 } 3960 void Ssat(Register rd, uint32_t imm, const Operand& operand) { 3961 Ssat(al, rd, imm, operand); 3962 } 3963 3964 void Ssat16(Condition cond, Register rd, uint32_t imm, Register rn) { 3965 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3966 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3967 VIXL_ASSERT(allow_macro_instructions_); 3968 VIXL_ASSERT(OutsideITBlock()); 3969 MacroEmissionCheckScope guard(this); 3970 ITScope it_scope(this, &cond); 3971 ssat16(cond, rd, imm, rn); 3972 } 3973 void Ssat16(Register rd, uint32_t imm, Register rn) { 3974 Ssat16(al, rd, imm, rn); 3975 } 3976 3977 void Ssax(Condition cond, Register rd, Register rn, Register rm) { 3978 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3979 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3980 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3981 VIXL_ASSERT(allow_macro_instructions_); 3982 VIXL_ASSERT(OutsideITBlock()); 3983 MacroEmissionCheckScope guard(this); 3984 ITScope it_scope(this, &cond); 3985 ssax(cond, rd, rn, rm); 3986 } 3987 void Ssax(Register rd, Register rn, Register rm) { Ssax(al, rd, rn, rm); } 3988 3989 void Ssub16(Condition cond, Register rd, Register rn, Register rm) { 3990 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3991 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3992 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3993 VIXL_ASSERT(allow_macro_instructions_); 3994 VIXL_ASSERT(OutsideITBlock()); 3995 MacroEmissionCheckScope guard(this); 3996 ITScope it_scope(this, &cond); 3997 ssub16(cond, rd, rn, rm); 3998 } 3999 void Ssub16(Register rd, Register rn, Register rm) { Ssub16(al, rd, rn, rm); } 4000 4001 void Ssub8(Condition cond, Register rd, Register rn, Register rm) { 4002 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4003 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4004 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4005 VIXL_ASSERT(allow_macro_instructions_); 4006 VIXL_ASSERT(OutsideITBlock()); 4007 MacroEmissionCheckScope guard(this); 4008 ITScope it_scope(this, &cond); 4009 ssub8(cond, rd, rn, rm); 4010 } 4011 void Ssub8(Register rd, Register rn, Register rm) { Ssub8(al, rd, rn, rm); } 4012 4013 void Stl(Condition cond, Register rt, const MemOperand& operand) { 4014 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4015 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4016 VIXL_ASSERT(allow_macro_instructions_); 4017 VIXL_ASSERT(OutsideITBlock()); 4018 MacroEmissionCheckScope guard(this); 4019 ITScope it_scope(this, &cond); 4020 stl(cond, rt, operand); 4021 } 4022 void Stl(Register rt, const MemOperand& operand) { Stl(al, rt, operand); } 4023 4024 void Stlb(Condition cond, Register rt, const MemOperand& operand) { 4025 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4026 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4027 VIXL_ASSERT(allow_macro_instructions_); 4028 VIXL_ASSERT(OutsideITBlock()); 4029 MacroEmissionCheckScope guard(this); 4030 ITScope it_scope(this, &cond); 4031 stlb(cond, rt, operand); 4032 } 4033 void Stlb(Register rt, const MemOperand& operand) { Stlb(al, rt, operand); } 4034 4035 void Stlex(Condition cond, 4036 Register rd, 4037 Register rt, 4038 const MemOperand& operand) { 4039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4040 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4041 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4042 VIXL_ASSERT(allow_macro_instructions_); 4043 VIXL_ASSERT(OutsideITBlock()); 4044 MacroEmissionCheckScope guard(this); 4045 ITScope it_scope(this, &cond); 4046 stlex(cond, rd, rt, operand); 4047 } 4048 void Stlex(Register rd, Register rt, const MemOperand& operand) { 4049 Stlex(al, rd, rt, operand); 4050 } 4051 4052 void Stlexb(Condition cond, 4053 Register rd, 4054 Register rt, 4055 const MemOperand& operand) { 4056 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4057 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4058 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4059 VIXL_ASSERT(allow_macro_instructions_); 4060 VIXL_ASSERT(OutsideITBlock()); 4061 MacroEmissionCheckScope guard(this); 4062 ITScope it_scope(this, &cond); 4063 stlexb(cond, rd, rt, operand); 4064 } 4065 void Stlexb(Register rd, Register rt, const MemOperand& operand) { 4066 Stlexb(al, rd, rt, operand); 4067 } 4068 4069 void Stlexd(Condition cond, 4070 Register rd, 4071 Register rt, 4072 Register rt2, 4073 const MemOperand& operand) { 4074 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4075 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4076 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 4077 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4078 VIXL_ASSERT(allow_macro_instructions_); 4079 VIXL_ASSERT(OutsideITBlock()); 4080 MacroEmissionCheckScope guard(this); 4081 ITScope it_scope(this, &cond); 4082 stlexd(cond, rd, rt, rt2, operand); 4083 } 4084 void Stlexd(Register rd, 4085 Register rt, 4086 Register rt2, 4087 const MemOperand& operand) { 4088 Stlexd(al, rd, rt, rt2, operand); 4089 } 4090 4091 void Stlexh(Condition cond, 4092 Register rd, 4093 Register rt, 4094 const MemOperand& operand) { 4095 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4096 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4097 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4098 VIXL_ASSERT(allow_macro_instructions_); 4099 VIXL_ASSERT(OutsideITBlock()); 4100 MacroEmissionCheckScope guard(this); 4101 ITScope it_scope(this, &cond); 4102 stlexh(cond, rd, rt, operand); 4103 } 4104 void Stlexh(Register rd, Register rt, const MemOperand& operand) { 4105 Stlexh(al, rd, rt, operand); 4106 } 4107 4108 void Stlh(Condition cond, Register rt, const MemOperand& operand) { 4109 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4110 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4111 VIXL_ASSERT(allow_macro_instructions_); 4112 VIXL_ASSERT(OutsideITBlock()); 4113 MacroEmissionCheckScope guard(this); 4114 ITScope it_scope(this, &cond); 4115 stlh(cond, rt, operand); 4116 } 4117 void Stlh(Register rt, const MemOperand& operand) { Stlh(al, rt, operand); } 4118 4119 void Stm(Condition cond, 4120 Register rn, 4121 WriteBack write_back, 4122 RegisterList registers) { 4123 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4124 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4125 VIXL_ASSERT(allow_macro_instructions_); 4126 VIXL_ASSERT(OutsideITBlock()); 4127 MacroEmissionCheckScope guard(this); 4128 ITScope it_scope(this, &cond); 4129 stm(cond, rn, write_back, registers); 4130 } 4131 void Stm(Register rn, WriteBack write_back, RegisterList registers) { 4132 Stm(al, rn, write_back, registers); 4133 } 4134 4135 void Stmda(Condition cond, 4136 Register rn, 4137 WriteBack write_back, 4138 RegisterList registers) { 4139 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4140 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4141 VIXL_ASSERT(allow_macro_instructions_); 4142 VIXL_ASSERT(OutsideITBlock()); 4143 MacroEmissionCheckScope guard(this); 4144 ITScope it_scope(this, &cond); 4145 stmda(cond, rn, write_back, registers); 4146 } 4147 void Stmda(Register rn, WriteBack write_back, RegisterList registers) { 4148 Stmda(al, rn, write_back, registers); 4149 } 4150 4151 void Stmdb(Condition cond, 4152 Register rn, 4153 WriteBack write_back, 4154 RegisterList registers) { 4155 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4156 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4157 VIXL_ASSERT(allow_macro_instructions_); 4158 VIXL_ASSERT(OutsideITBlock()); 4159 MacroEmissionCheckScope guard(this); 4160 ITScope it_scope(this, &cond); 4161 stmdb(cond, rn, write_back, registers); 4162 } 4163 void Stmdb(Register rn, WriteBack write_back, RegisterList registers) { 4164 Stmdb(al, rn, write_back, registers); 4165 } 4166 4167 void Stmea(Condition cond, 4168 Register rn, 4169 WriteBack write_back, 4170 RegisterList registers) { 4171 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4172 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4173 VIXL_ASSERT(allow_macro_instructions_); 4174 VIXL_ASSERT(OutsideITBlock()); 4175 MacroEmissionCheckScope guard(this); 4176 ITScope it_scope(this, &cond); 4177 stmea(cond, rn, write_back, registers); 4178 } 4179 void Stmea(Register rn, WriteBack write_back, RegisterList registers) { 4180 Stmea(al, rn, write_back, registers); 4181 } 4182 4183 void Stmed(Condition cond, 4184 Register rn, 4185 WriteBack write_back, 4186 RegisterList registers) { 4187 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4188 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4189 VIXL_ASSERT(allow_macro_instructions_); 4190 VIXL_ASSERT(OutsideITBlock()); 4191 MacroEmissionCheckScope guard(this); 4192 ITScope it_scope(this, &cond); 4193 stmed(cond, rn, write_back, registers); 4194 } 4195 void Stmed(Register rn, WriteBack write_back, RegisterList registers) { 4196 Stmed(al, rn, write_back, registers); 4197 } 4198 4199 void Stmfa(Condition cond, 4200 Register rn, 4201 WriteBack write_back, 4202 RegisterList registers) { 4203 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4204 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4205 VIXL_ASSERT(allow_macro_instructions_); 4206 VIXL_ASSERT(OutsideITBlock()); 4207 MacroEmissionCheckScope guard(this); 4208 ITScope it_scope(this, &cond); 4209 stmfa(cond, rn, write_back, registers); 4210 } 4211 void Stmfa(Register rn, WriteBack write_back, RegisterList registers) { 4212 Stmfa(al, rn, write_back, registers); 4213 } 4214 4215 void Stmfd(Condition cond, 4216 Register rn, 4217 WriteBack write_back, 4218 RegisterList registers) { 4219 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4220 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4221 VIXL_ASSERT(allow_macro_instructions_); 4222 VIXL_ASSERT(OutsideITBlock()); 4223 MacroEmissionCheckScope guard(this); 4224 ITScope it_scope(this, &cond); 4225 stmfd(cond, rn, write_back, registers); 4226 } 4227 void Stmfd(Register rn, WriteBack write_back, RegisterList registers) { 4228 Stmfd(al, rn, write_back, registers); 4229 } 4230 4231 void Stmib(Condition cond, 4232 Register rn, 4233 WriteBack write_back, 4234 RegisterList registers) { 4235 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4236 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4237 VIXL_ASSERT(allow_macro_instructions_); 4238 VIXL_ASSERT(OutsideITBlock()); 4239 MacroEmissionCheckScope guard(this); 4240 ITScope it_scope(this, &cond); 4241 stmib(cond, rn, write_back, registers); 4242 } 4243 void Stmib(Register rn, WriteBack write_back, RegisterList registers) { 4244 Stmib(al, rn, write_back, registers); 4245 } 4246 4247 void Str(Condition cond, Register rt, const MemOperand& operand) { 4248 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4249 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4250 VIXL_ASSERT(allow_macro_instructions_); 4251 VIXL_ASSERT(OutsideITBlock()); 4252 MacroEmissionCheckScope guard(this); 4253 bool can_use_it = 4254 // STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 4255 (operand.IsImmediate() && rt.IsLow() && 4256 operand.GetBaseRegister().IsLow() && 4257 operand.IsOffsetImmediateWithinRange(0, 124, 4) && 4258 (operand.GetAddrMode() == Offset)) || 4259 // STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2 4260 (operand.IsImmediate() && rt.IsLow() && 4261 operand.GetBaseRegister().IsSP() && 4262 operand.IsOffsetImmediateWithinRange(0, 1020, 4) && 4263 (operand.GetAddrMode() == Offset)) || 4264 // STR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 4265 (operand.IsPlainRegister() && rt.IsLow() && 4266 operand.GetBaseRegister().IsLow() && 4267 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 4268 (operand.GetAddrMode() == Offset)); 4269 ITScope it_scope(this, &cond, can_use_it); 4270 str(cond, rt, operand); 4271 } 4272 void Str(Register rt, const MemOperand& operand) { Str(al, rt, operand); } 4273 4274 void Strb(Condition cond, Register rt, const MemOperand& operand) { 4275 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4276 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4277 VIXL_ASSERT(allow_macro_instructions_); 4278 VIXL_ASSERT(OutsideITBlock()); 4279 MacroEmissionCheckScope guard(this); 4280 bool can_use_it = 4281 // STRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 4282 (operand.IsImmediate() && rt.IsLow() && 4283 operand.GetBaseRegister().IsLow() && 4284 operand.IsOffsetImmediateWithinRange(0, 31) && 4285 (operand.GetAddrMode() == Offset)) || 4286 // STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 4287 (operand.IsPlainRegister() && rt.IsLow() && 4288 operand.GetBaseRegister().IsLow() && 4289 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 4290 (operand.GetAddrMode() == Offset)); 4291 ITScope it_scope(this, &cond, can_use_it); 4292 strb(cond, rt, operand); 4293 } 4294 void Strb(Register rt, const MemOperand& operand) { Strb(al, rt, operand); } 4295 4296 void Strd(Condition cond, 4297 Register rt, 4298 Register rt2, 4299 const MemOperand& operand) { 4300 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4301 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 4302 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4303 VIXL_ASSERT(allow_macro_instructions_); 4304 VIXL_ASSERT(OutsideITBlock()); 4305 MacroEmissionCheckScope guard(this); 4306 ITScope it_scope(this, &cond); 4307 strd(cond, rt, rt2, operand); 4308 } 4309 void Strd(Register rt, Register rt2, const MemOperand& operand) { 4310 Strd(al, rt, rt2, operand); 4311 } 4312 4313 void Strex(Condition cond, 4314 Register rd, 4315 Register rt, 4316 const MemOperand& operand) { 4317 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4318 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4319 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4320 VIXL_ASSERT(allow_macro_instructions_); 4321 VIXL_ASSERT(OutsideITBlock()); 4322 MacroEmissionCheckScope guard(this); 4323 ITScope it_scope(this, &cond); 4324 strex(cond, rd, rt, operand); 4325 } 4326 void Strex(Register rd, Register rt, const MemOperand& operand) { 4327 Strex(al, rd, rt, operand); 4328 } 4329 4330 void Strexb(Condition cond, 4331 Register rd, 4332 Register rt, 4333 const MemOperand& operand) { 4334 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4335 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4336 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4337 VIXL_ASSERT(allow_macro_instructions_); 4338 VIXL_ASSERT(OutsideITBlock()); 4339 MacroEmissionCheckScope guard(this); 4340 ITScope it_scope(this, &cond); 4341 strexb(cond, rd, rt, operand); 4342 } 4343 void Strexb(Register rd, Register rt, const MemOperand& operand) { 4344 Strexb(al, rd, rt, operand); 4345 } 4346 4347 void Strexd(Condition cond, 4348 Register rd, 4349 Register rt, 4350 Register rt2, 4351 const MemOperand& operand) { 4352 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4353 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4354 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 4355 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4356 VIXL_ASSERT(allow_macro_instructions_); 4357 VIXL_ASSERT(OutsideITBlock()); 4358 MacroEmissionCheckScope guard(this); 4359 ITScope it_scope(this, &cond); 4360 strexd(cond, rd, rt, rt2, operand); 4361 } 4362 void Strexd(Register rd, 4363 Register rt, 4364 Register rt2, 4365 const MemOperand& operand) { 4366 Strexd(al, rd, rt, rt2, operand); 4367 } 4368 4369 void Strexh(Condition cond, 4370 Register rd, 4371 Register rt, 4372 const MemOperand& operand) { 4373 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4374 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4375 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4376 VIXL_ASSERT(allow_macro_instructions_); 4377 VIXL_ASSERT(OutsideITBlock()); 4378 MacroEmissionCheckScope guard(this); 4379 ITScope it_scope(this, &cond); 4380 strexh(cond, rd, rt, operand); 4381 } 4382 void Strexh(Register rd, Register rt, const MemOperand& operand) { 4383 Strexh(al, rd, rt, operand); 4384 } 4385 4386 void Strh(Condition cond, Register rt, const MemOperand& operand) { 4387 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4388 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4389 VIXL_ASSERT(allow_macro_instructions_); 4390 VIXL_ASSERT(OutsideITBlock()); 4391 MacroEmissionCheckScope guard(this); 4392 bool can_use_it = 4393 // STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 4394 (operand.IsImmediate() && rt.IsLow() && 4395 operand.GetBaseRegister().IsLow() && 4396 operand.IsOffsetImmediateWithinRange(0, 62, 2) && 4397 (operand.GetAddrMode() == Offset)) || 4398 // STRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 4399 (operand.IsPlainRegister() && rt.IsLow() && 4400 operand.GetBaseRegister().IsLow() && 4401 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 4402 (operand.GetAddrMode() == Offset)); 4403 ITScope it_scope(this, &cond, can_use_it); 4404 strh(cond, rt, operand); 4405 } 4406 void Strh(Register rt, const MemOperand& operand) { Strh(al, rt, operand); } 4407 4408 void Sub(Condition cond, Register rd, Register rn, const Operand& operand) { 4409 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4410 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4411 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4412 VIXL_ASSERT(allow_macro_instructions_); 4413 VIXL_ASSERT(OutsideITBlock()); 4414 MacroEmissionCheckScope guard(this); 4415 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) { 4416 uint32_t immediate = operand.GetImmediate(); 4417 if (immediate == 0) { 4418 return; 4419 } 4420 } 4421 bool can_use_it = 4422 // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 4423 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() && 4424 rd.IsLow()) || 4425 // SUB<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2 4426 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 4427 rd.IsLow() && rn.Is(rd)) || 4428 // SUB<c>{<q>} <Rd>, <Rn>, <Rm> 4429 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 4430 operand.GetBaseRegister().IsLow()); 4431 ITScope it_scope(this, &cond, can_use_it); 4432 sub(cond, rd, rn, operand); 4433 } 4434 void Sub(Register rd, Register rn, const Operand& operand) { 4435 Sub(al, rd, rn, operand); 4436 } 4437 void Sub(FlagsUpdate flags, 4438 Condition cond, 4439 Register rd, 4440 Register rn, 4441 const Operand& operand) { 4442 switch (flags) { 4443 case LeaveFlags: 4444 Sub(cond, rd, rn, operand); 4445 break; 4446 case SetFlags: 4447 Subs(cond, rd, rn, operand); 4448 break; 4449 case DontCare: 4450 bool can_be_16bit_encoded = 4451 IsUsingT32() && cond.Is(al) && 4452 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 4453 operand.GetBaseRegister().IsLow()) || 4454 (operand.IsImmediate() && 4455 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) || 4456 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256))))); 4457 if (can_be_16bit_encoded) { 4458 Subs(cond, rd, rn, operand); 4459 } else { 4460 Sub(cond, rd, rn, operand); 4461 } 4462 break; 4463 } 4464 } 4465 void Sub(FlagsUpdate flags, 4466 Register rd, 4467 Register rn, 4468 const Operand& operand) { 4469 Sub(flags, al, rd, rn, operand); 4470 } 4471 4472 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) { 4473 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4474 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4475 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4476 VIXL_ASSERT(allow_macro_instructions_); 4477 VIXL_ASSERT(OutsideITBlock()); 4478 MacroEmissionCheckScope guard(this); 4479 ITScope it_scope(this, &cond); 4480 subs(cond, rd, rn, operand); 4481 } 4482 void Subs(Register rd, Register rn, const Operand& operand) { 4483 Subs(al, rd, rn, operand); 4484 } 4485 4486 void Svc(Condition cond, uint32_t imm) { 4487 VIXL_ASSERT(allow_macro_instructions_); 4488 VIXL_ASSERT(OutsideITBlock()); 4489 MacroEmissionCheckScope guard(this); 4490 ITScope it_scope(this, &cond); 4491 svc(cond, imm); 4492 } 4493 void Svc(uint32_t imm) { Svc(al, imm); } 4494 4495 void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) { 4496 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4497 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4498 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4499 VIXL_ASSERT(allow_macro_instructions_); 4500 VIXL_ASSERT(OutsideITBlock()); 4501 MacroEmissionCheckScope guard(this); 4502 ITScope it_scope(this, &cond); 4503 sxtab(cond, rd, rn, operand); 4504 } 4505 void Sxtab(Register rd, Register rn, const Operand& operand) { 4506 Sxtab(al, rd, rn, operand); 4507 } 4508 4509 void Sxtab16(Condition cond, 4510 Register rd, 4511 Register rn, 4512 const Operand& operand) { 4513 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4514 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4515 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4516 VIXL_ASSERT(allow_macro_instructions_); 4517 VIXL_ASSERT(OutsideITBlock()); 4518 MacroEmissionCheckScope guard(this); 4519 ITScope it_scope(this, &cond); 4520 sxtab16(cond, rd, rn, operand); 4521 } 4522 void Sxtab16(Register rd, Register rn, const Operand& operand) { 4523 Sxtab16(al, rd, rn, operand); 4524 } 4525 4526 void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) { 4527 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4528 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4529 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4530 VIXL_ASSERT(allow_macro_instructions_); 4531 VIXL_ASSERT(OutsideITBlock()); 4532 MacroEmissionCheckScope guard(this); 4533 ITScope it_scope(this, &cond); 4534 sxtah(cond, rd, rn, operand); 4535 } 4536 void Sxtah(Register rd, Register rn, const Operand& operand) { 4537 Sxtah(al, rd, rn, operand); 4538 } 4539 4540 void Sxtb(Condition cond, Register rd, const Operand& operand) { 4541 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4542 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4543 VIXL_ASSERT(allow_macro_instructions_); 4544 VIXL_ASSERT(OutsideITBlock()); 4545 MacroEmissionCheckScope guard(this); 4546 ITScope it_scope(this, &cond); 4547 sxtb(cond, rd, operand); 4548 } 4549 void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); } 4550 4551 void Sxtb16(Condition cond, Register rd, const Operand& operand) { 4552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4553 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4554 VIXL_ASSERT(allow_macro_instructions_); 4555 VIXL_ASSERT(OutsideITBlock()); 4556 MacroEmissionCheckScope guard(this); 4557 ITScope it_scope(this, &cond); 4558 sxtb16(cond, rd, operand); 4559 } 4560 void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); } 4561 4562 void Sxth(Condition cond, Register rd, const Operand& operand) { 4563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4564 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4565 VIXL_ASSERT(allow_macro_instructions_); 4566 VIXL_ASSERT(OutsideITBlock()); 4567 MacroEmissionCheckScope guard(this); 4568 ITScope it_scope(this, &cond); 4569 sxth(cond, rd, operand); 4570 } 4571 void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); } 4572 4573 void Teq(Condition cond, Register rn, const Operand& operand) { 4574 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4575 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4576 VIXL_ASSERT(allow_macro_instructions_); 4577 VIXL_ASSERT(OutsideITBlock()); 4578 MacroEmissionCheckScope guard(this); 4579 ITScope it_scope(this, &cond); 4580 teq(cond, rn, operand); 4581 } 4582 void Teq(Register rn, const Operand& operand) { Teq(al, rn, operand); } 4583 4584 void Tst(Condition cond, Register rn, const Operand& operand) { 4585 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4586 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4587 VIXL_ASSERT(allow_macro_instructions_); 4588 VIXL_ASSERT(OutsideITBlock()); 4589 MacroEmissionCheckScope guard(this); 4590 bool can_use_it = 4591 // TST{<c>}{<q>} <Rn>, <Rm> ; T1 4592 operand.IsPlainRegister() && rn.IsLow() && 4593 operand.GetBaseRegister().IsLow(); 4594 ITScope it_scope(this, &cond, can_use_it); 4595 tst(cond, rn, operand); 4596 } 4597 void Tst(Register rn, const Operand& operand) { Tst(al, rn, operand); } 4598 4599 void Uadd16(Condition cond, Register rd, Register rn, Register rm) { 4600 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4601 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4602 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4603 VIXL_ASSERT(allow_macro_instructions_); 4604 VIXL_ASSERT(OutsideITBlock()); 4605 MacroEmissionCheckScope guard(this); 4606 ITScope it_scope(this, &cond); 4607 uadd16(cond, rd, rn, rm); 4608 } 4609 void Uadd16(Register rd, Register rn, Register rm) { Uadd16(al, rd, rn, rm); } 4610 4611 void Uadd8(Condition cond, Register rd, Register rn, Register rm) { 4612 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4614 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4615 VIXL_ASSERT(allow_macro_instructions_); 4616 VIXL_ASSERT(OutsideITBlock()); 4617 MacroEmissionCheckScope guard(this); 4618 ITScope it_scope(this, &cond); 4619 uadd8(cond, rd, rn, rm); 4620 } 4621 void Uadd8(Register rd, Register rn, Register rm) { Uadd8(al, rd, rn, rm); } 4622 4623 void Uasx(Condition cond, Register rd, Register rn, Register rm) { 4624 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4625 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4626 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4627 VIXL_ASSERT(allow_macro_instructions_); 4628 VIXL_ASSERT(OutsideITBlock()); 4629 MacroEmissionCheckScope guard(this); 4630 ITScope it_scope(this, &cond); 4631 uasx(cond, rd, rn, rm); 4632 } 4633 void Uasx(Register rd, Register rn, Register rm) { Uasx(al, rd, rn, rm); } 4634 4635 void Ubfx(Condition cond, 4636 Register rd, 4637 Register rn, 4638 uint32_t lsb, 4639 const Operand& operand) { 4640 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4641 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4642 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4643 VIXL_ASSERT(allow_macro_instructions_); 4644 VIXL_ASSERT(OutsideITBlock()); 4645 MacroEmissionCheckScope guard(this); 4646 ITScope it_scope(this, &cond); 4647 ubfx(cond, rd, rn, lsb, operand); 4648 } 4649 void Ubfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 4650 Ubfx(al, rd, rn, lsb, operand); 4651 } 4652 4653 void Udf(Condition cond, uint32_t imm) { 4654 VIXL_ASSERT(allow_macro_instructions_); 4655 VIXL_ASSERT(OutsideITBlock()); 4656 MacroEmissionCheckScope guard(this); 4657 ITScope it_scope(this, &cond); 4658 udf(cond, imm); 4659 } 4660 void Udf(uint32_t imm) { Udf(al, imm); } 4661 4662 void Udiv(Condition cond, Register rd, Register rn, Register rm) { 4663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4664 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4665 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4666 VIXL_ASSERT(allow_macro_instructions_); 4667 VIXL_ASSERT(OutsideITBlock()); 4668 MacroEmissionCheckScope guard(this); 4669 ITScope it_scope(this, &cond); 4670 udiv(cond, rd, rn, rm); 4671 } 4672 void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); } 4673 4674 void Uhadd16(Condition cond, Register rd, Register rn, Register rm) { 4675 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4676 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4678 VIXL_ASSERT(allow_macro_instructions_); 4679 VIXL_ASSERT(OutsideITBlock()); 4680 MacroEmissionCheckScope guard(this); 4681 ITScope it_scope(this, &cond); 4682 uhadd16(cond, rd, rn, rm); 4683 } 4684 void Uhadd16(Register rd, Register rn, Register rm) { 4685 Uhadd16(al, rd, rn, rm); 4686 } 4687 4688 void Uhadd8(Condition cond, Register rd, Register rn, Register rm) { 4689 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4690 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4691 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4692 VIXL_ASSERT(allow_macro_instructions_); 4693 VIXL_ASSERT(OutsideITBlock()); 4694 MacroEmissionCheckScope guard(this); 4695 ITScope it_scope(this, &cond); 4696 uhadd8(cond, rd, rn, rm); 4697 } 4698 void Uhadd8(Register rd, Register rn, Register rm) { Uhadd8(al, rd, rn, rm); } 4699 4700 void Uhasx(Condition cond, Register rd, Register rn, Register rm) { 4701 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4702 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4703 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4704 VIXL_ASSERT(allow_macro_instructions_); 4705 VIXL_ASSERT(OutsideITBlock()); 4706 MacroEmissionCheckScope guard(this); 4707 ITScope it_scope(this, &cond); 4708 uhasx(cond, rd, rn, rm); 4709 } 4710 void Uhasx(Register rd, Register rn, Register rm) { Uhasx(al, rd, rn, rm); } 4711 4712 void Uhsax(Condition cond, Register rd, Register rn, Register rm) { 4713 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4714 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4715 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4716 VIXL_ASSERT(allow_macro_instructions_); 4717 VIXL_ASSERT(OutsideITBlock()); 4718 MacroEmissionCheckScope guard(this); 4719 ITScope it_scope(this, &cond); 4720 uhsax(cond, rd, rn, rm); 4721 } 4722 void Uhsax(Register rd, Register rn, Register rm) { Uhsax(al, rd, rn, rm); } 4723 4724 void Uhsub16(Condition cond, Register rd, Register rn, Register rm) { 4725 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4726 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4727 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4728 VIXL_ASSERT(allow_macro_instructions_); 4729 VIXL_ASSERT(OutsideITBlock()); 4730 MacroEmissionCheckScope guard(this); 4731 ITScope it_scope(this, &cond); 4732 uhsub16(cond, rd, rn, rm); 4733 } 4734 void Uhsub16(Register rd, Register rn, Register rm) { 4735 Uhsub16(al, rd, rn, rm); 4736 } 4737 4738 void Uhsub8(Condition cond, Register rd, Register rn, Register rm) { 4739 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4740 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4741 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4742 VIXL_ASSERT(allow_macro_instructions_); 4743 VIXL_ASSERT(OutsideITBlock()); 4744 MacroEmissionCheckScope guard(this); 4745 ITScope it_scope(this, &cond); 4746 uhsub8(cond, rd, rn, rm); 4747 } 4748 void Uhsub8(Register rd, Register rn, Register rm) { Uhsub8(al, rd, rn, rm); } 4749 4750 void Umaal( 4751 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4752 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4753 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4754 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4755 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4756 VIXL_ASSERT(allow_macro_instructions_); 4757 VIXL_ASSERT(OutsideITBlock()); 4758 MacroEmissionCheckScope guard(this); 4759 ITScope it_scope(this, &cond); 4760 umaal(cond, rdlo, rdhi, rn, rm); 4761 } 4762 void Umaal(Register rdlo, Register rdhi, Register rn, Register rm) { 4763 Umaal(al, rdlo, rdhi, rn, rm); 4764 } 4765 4766 void Umlal( 4767 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4768 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4769 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4770 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4771 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4772 VIXL_ASSERT(allow_macro_instructions_); 4773 VIXL_ASSERT(OutsideITBlock()); 4774 MacroEmissionCheckScope guard(this); 4775 ITScope it_scope(this, &cond); 4776 umlal(cond, rdlo, rdhi, rn, rm); 4777 } 4778 void Umlal(Register rdlo, Register rdhi, Register rn, Register rm) { 4779 Umlal(al, rdlo, rdhi, rn, rm); 4780 } 4781 void Umlal(FlagsUpdate flags, 4782 Condition cond, 4783 Register rdlo, 4784 Register rdhi, 4785 Register rn, 4786 Register rm) { 4787 switch (flags) { 4788 case LeaveFlags: 4789 Umlal(cond, rdlo, rdhi, rn, rm); 4790 break; 4791 case SetFlags: 4792 Umlals(cond, rdlo, rdhi, rn, rm); 4793 break; 4794 case DontCare: 4795 Umlal(cond, rdlo, rdhi, rn, rm); 4796 break; 4797 } 4798 } 4799 void Umlal(FlagsUpdate flags, 4800 Register rdlo, 4801 Register rdhi, 4802 Register rn, 4803 Register rm) { 4804 Umlal(flags, al, rdlo, rdhi, rn, rm); 4805 } 4806 4807 void Umlals( 4808 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4809 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4810 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4811 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4812 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4813 VIXL_ASSERT(allow_macro_instructions_); 4814 VIXL_ASSERT(OutsideITBlock()); 4815 MacroEmissionCheckScope guard(this); 4816 ITScope it_scope(this, &cond); 4817 umlals(cond, rdlo, rdhi, rn, rm); 4818 } 4819 void Umlals(Register rdlo, Register rdhi, Register rn, Register rm) { 4820 Umlals(al, rdlo, rdhi, rn, rm); 4821 } 4822 4823 void Umull( 4824 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4825 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4826 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4827 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4828 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4829 VIXL_ASSERT(allow_macro_instructions_); 4830 VIXL_ASSERT(OutsideITBlock()); 4831 MacroEmissionCheckScope guard(this); 4832 ITScope it_scope(this, &cond); 4833 umull(cond, rdlo, rdhi, rn, rm); 4834 } 4835 void Umull(Register rdlo, Register rdhi, Register rn, Register rm) { 4836 Umull(al, rdlo, rdhi, rn, rm); 4837 } 4838 void Umull(FlagsUpdate flags, 4839 Condition cond, 4840 Register rdlo, 4841 Register rdhi, 4842 Register rn, 4843 Register rm) { 4844 switch (flags) { 4845 case LeaveFlags: 4846 Umull(cond, rdlo, rdhi, rn, rm); 4847 break; 4848 case SetFlags: 4849 Umulls(cond, rdlo, rdhi, rn, rm); 4850 break; 4851 case DontCare: 4852 Umull(cond, rdlo, rdhi, rn, rm); 4853 break; 4854 } 4855 } 4856 void Umull(FlagsUpdate flags, 4857 Register rdlo, 4858 Register rdhi, 4859 Register rn, 4860 Register rm) { 4861 Umull(flags, al, rdlo, rdhi, rn, rm); 4862 } 4863 4864 void Umulls( 4865 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4867 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4868 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4869 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4870 VIXL_ASSERT(allow_macro_instructions_); 4871 VIXL_ASSERT(OutsideITBlock()); 4872 MacroEmissionCheckScope guard(this); 4873 ITScope it_scope(this, &cond); 4874 umulls(cond, rdlo, rdhi, rn, rm); 4875 } 4876 void Umulls(Register rdlo, Register rdhi, Register rn, Register rm) { 4877 Umulls(al, rdlo, rdhi, rn, rm); 4878 } 4879 4880 void Uqadd16(Condition cond, Register rd, Register rn, Register rm) { 4881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4882 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4883 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4884 VIXL_ASSERT(allow_macro_instructions_); 4885 VIXL_ASSERT(OutsideITBlock()); 4886 MacroEmissionCheckScope guard(this); 4887 ITScope it_scope(this, &cond); 4888 uqadd16(cond, rd, rn, rm); 4889 } 4890 void Uqadd16(Register rd, Register rn, Register rm) { 4891 Uqadd16(al, rd, rn, rm); 4892 } 4893 4894 void Uqadd8(Condition cond, Register rd, Register rn, Register rm) { 4895 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4896 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4897 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4898 VIXL_ASSERT(allow_macro_instructions_); 4899 VIXL_ASSERT(OutsideITBlock()); 4900 MacroEmissionCheckScope guard(this); 4901 ITScope it_scope(this, &cond); 4902 uqadd8(cond, rd, rn, rm); 4903 } 4904 void Uqadd8(Register rd, Register rn, Register rm) { Uqadd8(al, rd, rn, rm); } 4905 4906 void Uqasx(Condition cond, Register rd, Register rn, Register rm) { 4907 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4908 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4909 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4910 VIXL_ASSERT(allow_macro_instructions_); 4911 VIXL_ASSERT(OutsideITBlock()); 4912 MacroEmissionCheckScope guard(this); 4913 ITScope it_scope(this, &cond); 4914 uqasx(cond, rd, rn, rm); 4915 } 4916 void Uqasx(Register rd, Register rn, Register rm) { Uqasx(al, rd, rn, rm); } 4917 4918 void Uqsax(Condition cond, Register rd, Register rn, Register rm) { 4919 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4920 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4921 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4922 VIXL_ASSERT(allow_macro_instructions_); 4923 VIXL_ASSERT(OutsideITBlock()); 4924 MacroEmissionCheckScope guard(this); 4925 ITScope it_scope(this, &cond); 4926 uqsax(cond, rd, rn, rm); 4927 } 4928 void Uqsax(Register rd, Register rn, Register rm) { Uqsax(al, rd, rn, rm); } 4929 4930 void Uqsub16(Condition cond, Register rd, Register rn, Register rm) { 4931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4932 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4933 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4934 VIXL_ASSERT(allow_macro_instructions_); 4935 VIXL_ASSERT(OutsideITBlock()); 4936 MacroEmissionCheckScope guard(this); 4937 ITScope it_scope(this, &cond); 4938 uqsub16(cond, rd, rn, rm); 4939 } 4940 void Uqsub16(Register rd, Register rn, Register rm) { 4941 Uqsub16(al, rd, rn, rm); 4942 } 4943 4944 void Uqsub8(Condition cond, Register rd, Register rn, Register rm) { 4945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4947 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4948 VIXL_ASSERT(allow_macro_instructions_); 4949 VIXL_ASSERT(OutsideITBlock()); 4950 MacroEmissionCheckScope guard(this); 4951 ITScope it_scope(this, &cond); 4952 uqsub8(cond, rd, rn, rm); 4953 } 4954 void Uqsub8(Register rd, Register rn, Register rm) { Uqsub8(al, rd, rn, rm); } 4955 4956 void Usad8(Condition cond, Register rd, Register rn, Register rm) { 4957 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4958 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4959 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4960 VIXL_ASSERT(allow_macro_instructions_); 4961 VIXL_ASSERT(OutsideITBlock()); 4962 MacroEmissionCheckScope guard(this); 4963 ITScope it_scope(this, &cond); 4964 usad8(cond, rd, rn, rm); 4965 } 4966 void Usad8(Register rd, Register rn, Register rm) { Usad8(al, rd, rn, rm); } 4967 4968 void Usada8( 4969 Condition cond, Register rd, Register rn, Register rm, Register ra) { 4970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4971 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4972 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4973 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 4974 VIXL_ASSERT(allow_macro_instructions_); 4975 VIXL_ASSERT(OutsideITBlock()); 4976 MacroEmissionCheckScope guard(this); 4977 ITScope it_scope(this, &cond); 4978 usada8(cond, rd, rn, rm, ra); 4979 } 4980 void Usada8(Register rd, Register rn, Register rm, Register ra) { 4981 Usada8(al, rd, rn, rm, ra); 4982 } 4983 4984 void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) { 4985 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4986 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4987 VIXL_ASSERT(allow_macro_instructions_); 4988 VIXL_ASSERT(OutsideITBlock()); 4989 MacroEmissionCheckScope guard(this); 4990 ITScope it_scope(this, &cond); 4991 usat(cond, rd, imm, operand); 4992 } 4993 void Usat(Register rd, uint32_t imm, const Operand& operand) { 4994 Usat(al, rd, imm, operand); 4995 } 4996 4997 void Usat16(Condition cond, Register rd, uint32_t imm, Register rn) { 4998 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4999 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5000 VIXL_ASSERT(allow_macro_instructions_); 5001 VIXL_ASSERT(OutsideITBlock()); 5002 MacroEmissionCheckScope guard(this); 5003 ITScope it_scope(this, &cond); 5004 usat16(cond, rd, imm, rn); 5005 } 5006 void Usat16(Register rd, uint32_t imm, Register rn) { 5007 Usat16(al, rd, imm, rn); 5008 } 5009 5010 void Usax(Condition cond, Register rd, Register rn, Register rm) { 5011 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5012 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5013 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5014 VIXL_ASSERT(allow_macro_instructions_); 5015 VIXL_ASSERT(OutsideITBlock()); 5016 MacroEmissionCheckScope guard(this); 5017 ITScope it_scope(this, &cond); 5018 usax(cond, rd, rn, rm); 5019 } 5020 void Usax(Register rd, Register rn, Register rm) { Usax(al, rd, rn, rm); } 5021 5022 void Usub16(Condition cond, Register rd, Register rn, Register rm) { 5023 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5024 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5025 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5026 VIXL_ASSERT(allow_macro_instructions_); 5027 VIXL_ASSERT(OutsideITBlock()); 5028 MacroEmissionCheckScope guard(this); 5029 ITScope it_scope(this, &cond); 5030 usub16(cond, rd, rn, rm); 5031 } 5032 void Usub16(Register rd, Register rn, Register rm) { Usub16(al, rd, rn, rm); } 5033 5034 void Usub8(Condition cond, Register rd, Register rn, Register rm) { 5035 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5036 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5037 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5038 VIXL_ASSERT(allow_macro_instructions_); 5039 VIXL_ASSERT(OutsideITBlock()); 5040 MacroEmissionCheckScope guard(this); 5041 ITScope it_scope(this, &cond); 5042 usub8(cond, rd, rn, rm); 5043 } 5044 void Usub8(Register rd, Register rn, Register rm) { Usub8(al, rd, rn, rm); } 5045 5046 void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) { 5047 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5048 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5049 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5050 VIXL_ASSERT(allow_macro_instructions_); 5051 VIXL_ASSERT(OutsideITBlock()); 5052 MacroEmissionCheckScope guard(this); 5053 ITScope it_scope(this, &cond); 5054 uxtab(cond, rd, rn, operand); 5055 } 5056 void Uxtab(Register rd, Register rn, const Operand& operand) { 5057 Uxtab(al, rd, rn, operand); 5058 } 5059 5060 void Uxtab16(Condition cond, 5061 Register rd, 5062 Register rn, 5063 const Operand& operand) { 5064 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5065 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5066 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5067 VIXL_ASSERT(allow_macro_instructions_); 5068 VIXL_ASSERT(OutsideITBlock()); 5069 MacroEmissionCheckScope guard(this); 5070 ITScope it_scope(this, &cond); 5071 uxtab16(cond, rd, rn, operand); 5072 } 5073 void Uxtab16(Register rd, Register rn, const Operand& operand) { 5074 Uxtab16(al, rd, rn, operand); 5075 } 5076 5077 void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) { 5078 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5079 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5080 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5081 VIXL_ASSERT(allow_macro_instructions_); 5082 VIXL_ASSERT(OutsideITBlock()); 5083 MacroEmissionCheckScope guard(this); 5084 ITScope it_scope(this, &cond); 5085 uxtah(cond, rd, rn, operand); 5086 } 5087 void Uxtah(Register rd, Register rn, const Operand& operand) { 5088 Uxtah(al, rd, rn, operand); 5089 } 5090 5091 void Uxtb(Condition cond, Register rd, const Operand& operand) { 5092 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5093 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5094 VIXL_ASSERT(allow_macro_instructions_); 5095 VIXL_ASSERT(OutsideITBlock()); 5096 MacroEmissionCheckScope guard(this); 5097 ITScope it_scope(this, &cond); 5098 uxtb(cond, rd, operand); 5099 } 5100 void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); } 5101 5102 void Uxtb16(Condition cond, Register rd, const Operand& operand) { 5103 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5104 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5105 VIXL_ASSERT(allow_macro_instructions_); 5106 VIXL_ASSERT(OutsideITBlock()); 5107 MacroEmissionCheckScope guard(this); 5108 ITScope it_scope(this, &cond); 5109 uxtb16(cond, rd, operand); 5110 } 5111 void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); } 5112 5113 void Uxth(Condition cond, Register rd, const Operand& operand) { 5114 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5115 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5116 VIXL_ASSERT(allow_macro_instructions_); 5117 VIXL_ASSERT(OutsideITBlock()); 5118 MacroEmissionCheckScope guard(this); 5119 ITScope it_scope(this, &cond); 5120 uxth(cond, rd, operand); 5121 } 5122 void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); } 5123 5124 void Vaba( 5125 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5126 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5127 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5128 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5129 VIXL_ASSERT(allow_macro_instructions_); 5130 VIXL_ASSERT(OutsideITBlock()); 5131 MacroEmissionCheckScope guard(this); 5132 ITScope it_scope(this, &cond); 5133 vaba(cond, dt, rd, rn, rm); 5134 } 5135 void Vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5136 Vaba(al, dt, rd, rn, rm); 5137 } 5138 5139 void Vaba( 5140 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5141 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5142 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5143 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5144 VIXL_ASSERT(allow_macro_instructions_); 5145 VIXL_ASSERT(OutsideITBlock()); 5146 MacroEmissionCheckScope guard(this); 5147 ITScope it_scope(this, &cond); 5148 vaba(cond, dt, rd, rn, rm); 5149 } 5150 void Vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5151 Vaba(al, dt, rd, rn, rm); 5152 } 5153 5154 void Vabal( 5155 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5156 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5157 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5158 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5159 VIXL_ASSERT(allow_macro_instructions_); 5160 VIXL_ASSERT(OutsideITBlock()); 5161 MacroEmissionCheckScope guard(this); 5162 ITScope it_scope(this, &cond); 5163 vabal(cond, dt, rd, rn, rm); 5164 } 5165 void Vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5166 Vabal(al, dt, rd, rn, rm); 5167 } 5168 5169 void Vabd( 5170 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5171 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5172 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5173 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5174 VIXL_ASSERT(allow_macro_instructions_); 5175 VIXL_ASSERT(OutsideITBlock()); 5176 MacroEmissionCheckScope guard(this); 5177 ITScope it_scope(this, &cond); 5178 vabd(cond, dt, rd, rn, rm); 5179 } 5180 void Vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5181 Vabd(al, dt, rd, rn, rm); 5182 } 5183 5184 void Vabd( 5185 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5186 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5187 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5189 VIXL_ASSERT(allow_macro_instructions_); 5190 VIXL_ASSERT(OutsideITBlock()); 5191 MacroEmissionCheckScope guard(this); 5192 ITScope it_scope(this, &cond); 5193 vabd(cond, dt, rd, rn, rm); 5194 } 5195 void Vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5196 Vabd(al, dt, rd, rn, rm); 5197 } 5198 5199 void Vabdl( 5200 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5201 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5202 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5203 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5204 VIXL_ASSERT(allow_macro_instructions_); 5205 VIXL_ASSERT(OutsideITBlock()); 5206 MacroEmissionCheckScope guard(this); 5207 ITScope it_scope(this, &cond); 5208 vabdl(cond, dt, rd, rn, rm); 5209 } 5210 void Vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5211 Vabdl(al, dt, rd, rn, rm); 5212 } 5213 5214 void Vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5215 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5216 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5217 VIXL_ASSERT(allow_macro_instructions_); 5218 VIXL_ASSERT(OutsideITBlock()); 5219 MacroEmissionCheckScope guard(this); 5220 ITScope it_scope(this, &cond); 5221 vabs(cond, dt, rd, rm); 5222 } 5223 void Vabs(DataType dt, DRegister rd, DRegister rm) { Vabs(al, dt, rd, rm); } 5224 5225 void Vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { 5226 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5227 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5228 VIXL_ASSERT(allow_macro_instructions_); 5229 VIXL_ASSERT(OutsideITBlock()); 5230 MacroEmissionCheckScope guard(this); 5231 ITScope it_scope(this, &cond); 5232 vabs(cond, dt, rd, rm); 5233 } 5234 void Vabs(DataType dt, QRegister rd, QRegister rm) { Vabs(al, dt, rd, rm); } 5235 5236 void Vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) { 5237 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5238 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5239 VIXL_ASSERT(allow_macro_instructions_); 5240 VIXL_ASSERT(OutsideITBlock()); 5241 MacroEmissionCheckScope guard(this); 5242 ITScope it_scope(this, &cond); 5243 vabs(cond, dt, rd, rm); 5244 } 5245 void Vabs(DataType dt, SRegister rd, SRegister rm) { Vabs(al, dt, rd, rm); } 5246 5247 void Vacge( 5248 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5249 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5250 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5251 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5252 VIXL_ASSERT(allow_macro_instructions_); 5253 VIXL_ASSERT(OutsideITBlock()); 5254 MacroEmissionCheckScope guard(this); 5255 ITScope it_scope(this, &cond); 5256 vacge(cond, dt, rd, rn, rm); 5257 } 5258 void Vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5259 Vacge(al, dt, rd, rn, rm); 5260 } 5261 5262 void Vacge( 5263 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5264 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5265 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5266 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5267 VIXL_ASSERT(allow_macro_instructions_); 5268 VIXL_ASSERT(OutsideITBlock()); 5269 MacroEmissionCheckScope guard(this); 5270 ITScope it_scope(this, &cond); 5271 vacge(cond, dt, rd, rn, rm); 5272 } 5273 void Vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5274 Vacge(al, dt, rd, rn, rm); 5275 } 5276 5277 void Vacgt( 5278 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5279 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5280 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5281 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5282 VIXL_ASSERT(allow_macro_instructions_); 5283 VIXL_ASSERT(OutsideITBlock()); 5284 MacroEmissionCheckScope guard(this); 5285 ITScope it_scope(this, &cond); 5286 vacgt(cond, dt, rd, rn, rm); 5287 } 5288 void Vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5289 Vacgt(al, dt, rd, rn, rm); 5290 } 5291 5292 void Vacgt( 5293 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5294 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5295 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5296 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5297 VIXL_ASSERT(allow_macro_instructions_); 5298 VIXL_ASSERT(OutsideITBlock()); 5299 MacroEmissionCheckScope guard(this); 5300 ITScope it_scope(this, &cond); 5301 vacgt(cond, dt, rd, rn, rm); 5302 } 5303 void Vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5304 Vacgt(al, dt, rd, rn, rm); 5305 } 5306 5307 void Vacle( 5308 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5310 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5311 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5312 VIXL_ASSERT(allow_macro_instructions_); 5313 VIXL_ASSERT(OutsideITBlock()); 5314 MacroEmissionCheckScope guard(this); 5315 ITScope it_scope(this, &cond); 5316 vacle(cond, dt, rd, rn, rm); 5317 } 5318 void Vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5319 Vacle(al, dt, rd, rn, rm); 5320 } 5321 5322 void Vacle( 5323 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5324 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5325 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5326 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5327 VIXL_ASSERT(allow_macro_instructions_); 5328 VIXL_ASSERT(OutsideITBlock()); 5329 MacroEmissionCheckScope guard(this); 5330 ITScope it_scope(this, &cond); 5331 vacle(cond, dt, rd, rn, rm); 5332 } 5333 void Vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5334 Vacle(al, dt, rd, rn, rm); 5335 } 5336 5337 void Vaclt( 5338 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5339 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5340 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5341 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5342 VIXL_ASSERT(allow_macro_instructions_); 5343 VIXL_ASSERT(OutsideITBlock()); 5344 MacroEmissionCheckScope guard(this); 5345 ITScope it_scope(this, &cond); 5346 vaclt(cond, dt, rd, rn, rm); 5347 } 5348 void Vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5349 Vaclt(al, dt, rd, rn, rm); 5350 } 5351 5352 void Vaclt( 5353 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5354 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5355 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5356 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5357 VIXL_ASSERT(allow_macro_instructions_); 5358 VIXL_ASSERT(OutsideITBlock()); 5359 MacroEmissionCheckScope guard(this); 5360 ITScope it_scope(this, &cond); 5361 vaclt(cond, dt, rd, rn, rm); 5362 } 5363 void Vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5364 Vaclt(al, dt, rd, rn, rm); 5365 } 5366 5367 void Vadd( 5368 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5369 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5370 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5371 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5372 VIXL_ASSERT(allow_macro_instructions_); 5373 VIXL_ASSERT(OutsideITBlock()); 5374 MacroEmissionCheckScope guard(this); 5375 ITScope it_scope(this, &cond); 5376 vadd(cond, dt, rd, rn, rm); 5377 } 5378 void Vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5379 Vadd(al, dt, rd, rn, rm); 5380 } 5381 5382 void Vadd( 5383 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5384 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5385 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5386 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5387 VIXL_ASSERT(allow_macro_instructions_); 5388 VIXL_ASSERT(OutsideITBlock()); 5389 MacroEmissionCheckScope guard(this); 5390 ITScope it_scope(this, &cond); 5391 vadd(cond, dt, rd, rn, rm); 5392 } 5393 void Vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5394 Vadd(al, dt, rd, rn, rm); 5395 } 5396 5397 void Vadd( 5398 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5399 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5400 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5401 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5402 VIXL_ASSERT(allow_macro_instructions_); 5403 VIXL_ASSERT(OutsideITBlock()); 5404 MacroEmissionCheckScope guard(this); 5405 ITScope it_scope(this, &cond); 5406 vadd(cond, dt, rd, rn, rm); 5407 } 5408 void Vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5409 Vadd(al, dt, rd, rn, rm); 5410 } 5411 5412 void Vaddhn( 5413 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5414 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5415 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5416 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5417 VIXL_ASSERT(allow_macro_instructions_); 5418 VIXL_ASSERT(OutsideITBlock()); 5419 MacroEmissionCheckScope guard(this); 5420 ITScope it_scope(this, &cond); 5421 vaddhn(cond, dt, rd, rn, rm); 5422 } 5423 void Vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5424 Vaddhn(al, dt, rd, rn, rm); 5425 } 5426 5427 void Vaddl( 5428 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5429 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5430 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5431 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5432 VIXL_ASSERT(allow_macro_instructions_); 5433 VIXL_ASSERT(OutsideITBlock()); 5434 MacroEmissionCheckScope guard(this); 5435 ITScope it_scope(this, &cond); 5436 vaddl(cond, dt, rd, rn, rm); 5437 } 5438 void Vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5439 Vaddl(al, dt, rd, rn, rm); 5440 } 5441 5442 void Vaddw( 5443 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { 5444 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5445 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5446 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5447 VIXL_ASSERT(allow_macro_instructions_); 5448 VIXL_ASSERT(OutsideITBlock()); 5449 MacroEmissionCheckScope guard(this); 5450 ITScope it_scope(this, &cond); 5451 vaddw(cond, dt, rd, rn, rm); 5452 } 5453 void Vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 5454 Vaddw(al, dt, rd, rn, rm); 5455 } 5456 5457 void Vand(Condition cond, 5458 DataType dt, 5459 DRegister rd, 5460 DRegister rn, 5461 const DOperand& operand) { 5462 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5463 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5464 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5465 VIXL_ASSERT(allow_macro_instructions_); 5466 VIXL_ASSERT(OutsideITBlock()); 5467 MacroEmissionCheckScope guard(this); 5468 ITScope it_scope(this, &cond); 5469 vand(cond, dt, rd, rn, operand); 5470 } 5471 void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5472 Vand(al, dt, rd, rn, operand); 5473 } 5474 5475 void Vand(Condition cond, 5476 DataType dt, 5477 QRegister rd, 5478 QRegister rn, 5479 const QOperand& operand) { 5480 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5481 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5482 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5483 VIXL_ASSERT(allow_macro_instructions_); 5484 VIXL_ASSERT(OutsideITBlock()); 5485 MacroEmissionCheckScope guard(this); 5486 ITScope it_scope(this, &cond); 5487 vand(cond, dt, rd, rn, operand); 5488 } 5489 void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5490 Vand(al, dt, rd, rn, operand); 5491 } 5492 5493 void Vbic(Condition cond, 5494 DataType dt, 5495 DRegister rd, 5496 DRegister rn, 5497 const DOperand& operand) { 5498 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5499 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5500 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5501 VIXL_ASSERT(allow_macro_instructions_); 5502 VIXL_ASSERT(OutsideITBlock()); 5503 MacroEmissionCheckScope guard(this); 5504 ITScope it_scope(this, &cond); 5505 vbic(cond, dt, rd, rn, operand); 5506 } 5507 void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5508 Vbic(al, dt, rd, rn, operand); 5509 } 5510 5511 void Vbic(Condition cond, 5512 DataType dt, 5513 QRegister rd, 5514 QRegister rn, 5515 const QOperand& operand) { 5516 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5517 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5518 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5519 VIXL_ASSERT(allow_macro_instructions_); 5520 VIXL_ASSERT(OutsideITBlock()); 5521 MacroEmissionCheckScope guard(this); 5522 ITScope it_scope(this, &cond); 5523 vbic(cond, dt, rd, rn, operand); 5524 } 5525 void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5526 Vbic(al, dt, rd, rn, operand); 5527 } 5528 5529 void Vbif( 5530 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5531 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5532 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5533 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5534 VIXL_ASSERT(allow_macro_instructions_); 5535 VIXL_ASSERT(OutsideITBlock()); 5536 MacroEmissionCheckScope guard(this); 5537 ITScope it_scope(this, &cond); 5538 vbif(cond, dt, rd, rn, rm); 5539 } 5540 void Vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5541 Vbif(al, dt, rd, rn, rm); 5542 } 5543 void Vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5544 Vbif(cond, kDataTypeValueNone, rd, rn, rm); 5545 } 5546 void Vbif(DRegister rd, DRegister rn, DRegister rm) { 5547 Vbif(al, kDataTypeValueNone, rd, rn, rm); 5548 } 5549 5550 void Vbif( 5551 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5553 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5554 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5555 VIXL_ASSERT(allow_macro_instructions_); 5556 VIXL_ASSERT(OutsideITBlock()); 5557 MacroEmissionCheckScope guard(this); 5558 ITScope it_scope(this, &cond); 5559 vbif(cond, dt, rd, rn, rm); 5560 } 5561 void Vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5562 Vbif(al, dt, rd, rn, rm); 5563 } 5564 void Vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5565 Vbif(cond, kDataTypeValueNone, rd, rn, rm); 5566 } 5567 void Vbif(QRegister rd, QRegister rn, QRegister rm) { 5568 Vbif(al, kDataTypeValueNone, rd, rn, rm); 5569 } 5570 5571 void Vbit( 5572 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5573 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5574 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5575 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5576 VIXL_ASSERT(allow_macro_instructions_); 5577 VIXL_ASSERT(OutsideITBlock()); 5578 MacroEmissionCheckScope guard(this); 5579 ITScope it_scope(this, &cond); 5580 vbit(cond, dt, rd, rn, rm); 5581 } 5582 void Vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5583 Vbit(al, dt, rd, rn, rm); 5584 } 5585 void Vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5586 Vbit(cond, kDataTypeValueNone, rd, rn, rm); 5587 } 5588 void Vbit(DRegister rd, DRegister rn, DRegister rm) { 5589 Vbit(al, kDataTypeValueNone, rd, rn, rm); 5590 } 5591 5592 void Vbit( 5593 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5594 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5595 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5596 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5597 VIXL_ASSERT(allow_macro_instructions_); 5598 VIXL_ASSERT(OutsideITBlock()); 5599 MacroEmissionCheckScope guard(this); 5600 ITScope it_scope(this, &cond); 5601 vbit(cond, dt, rd, rn, rm); 5602 } 5603 void Vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5604 Vbit(al, dt, rd, rn, rm); 5605 } 5606 void Vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5607 Vbit(cond, kDataTypeValueNone, rd, rn, rm); 5608 } 5609 void Vbit(QRegister rd, QRegister rn, QRegister rm) { 5610 Vbit(al, kDataTypeValueNone, rd, rn, rm); 5611 } 5612 5613 void Vbsl( 5614 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5615 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5616 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5617 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5618 VIXL_ASSERT(allow_macro_instructions_); 5619 VIXL_ASSERT(OutsideITBlock()); 5620 MacroEmissionCheckScope guard(this); 5621 ITScope it_scope(this, &cond); 5622 vbsl(cond, dt, rd, rn, rm); 5623 } 5624 void Vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5625 Vbsl(al, dt, rd, rn, rm); 5626 } 5627 void Vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5628 Vbsl(cond, kDataTypeValueNone, rd, rn, rm); 5629 } 5630 void Vbsl(DRegister rd, DRegister rn, DRegister rm) { 5631 Vbsl(al, kDataTypeValueNone, rd, rn, rm); 5632 } 5633 5634 void Vbsl( 5635 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5636 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5637 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5638 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5639 VIXL_ASSERT(allow_macro_instructions_); 5640 VIXL_ASSERT(OutsideITBlock()); 5641 MacroEmissionCheckScope guard(this); 5642 ITScope it_scope(this, &cond); 5643 vbsl(cond, dt, rd, rn, rm); 5644 } 5645 void Vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5646 Vbsl(al, dt, rd, rn, rm); 5647 } 5648 void Vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5649 Vbsl(cond, kDataTypeValueNone, rd, rn, rm); 5650 } 5651 void Vbsl(QRegister rd, QRegister rn, QRegister rm) { 5652 Vbsl(al, kDataTypeValueNone, rd, rn, rm); 5653 } 5654 5655 void Vceq(Condition cond, 5656 DataType dt, 5657 DRegister rd, 5658 DRegister rm, 5659 const DOperand& operand) { 5660 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5661 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5662 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5663 VIXL_ASSERT(allow_macro_instructions_); 5664 VIXL_ASSERT(OutsideITBlock()); 5665 MacroEmissionCheckScope guard(this); 5666 ITScope it_scope(this, &cond); 5667 vceq(cond, dt, rd, rm, operand); 5668 } 5669 void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5670 Vceq(al, dt, rd, rm, operand); 5671 } 5672 5673 void Vceq(Condition cond, 5674 DataType dt, 5675 QRegister rd, 5676 QRegister rm, 5677 const QOperand& operand) { 5678 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5680 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5681 VIXL_ASSERT(allow_macro_instructions_); 5682 VIXL_ASSERT(OutsideITBlock()); 5683 MacroEmissionCheckScope guard(this); 5684 ITScope it_scope(this, &cond); 5685 vceq(cond, dt, rd, rm, operand); 5686 } 5687 void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5688 Vceq(al, dt, rd, rm, operand); 5689 } 5690 5691 void Vceq( 5692 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5693 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5694 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5695 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5696 VIXL_ASSERT(allow_macro_instructions_); 5697 VIXL_ASSERT(OutsideITBlock()); 5698 MacroEmissionCheckScope guard(this); 5699 ITScope it_scope(this, &cond); 5700 vceq(cond, dt, rd, rn, rm); 5701 } 5702 void Vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5703 Vceq(al, dt, rd, rn, rm); 5704 } 5705 5706 void Vceq( 5707 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5708 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5709 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5710 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5711 VIXL_ASSERT(allow_macro_instructions_); 5712 VIXL_ASSERT(OutsideITBlock()); 5713 MacroEmissionCheckScope guard(this); 5714 ITScope it_scope(this, &cond); 5715 vceq(cond, dt, rd, rn, rm); 5716 } 5717 void Vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5718 Vceq(al, dt, rd, rn, rm); 5719 } 5720 5721 void Vcge(Condition cond, 5722 DataType dt, 5723 DRegister rd, 5724 DRegister rm, 5725 const DOperand& operand) { 5726 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5727 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5728 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5729 VIXL_ASSERT(allow_macro_instructions_); 5730 VIXL_ASSERT(OutsideITBlock()); 5731 MacroEmissionCheckScope guard(this); 5732 ITScope it_scope(this, &cond); 5733 vcge(cond, dt, rd, rm, operand); 5734 } 5735 void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5736 Vcge(al, dt, rd, rm, operand); 5737 } 5738 5739 void Vcge(Condition cond, 5740 DataType dt, 5741 QRegister rd, 5742 QRegister rm, 5743 const QOperand& operand) { 5744 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5745 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5746 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5747 VIXL_ASSERT(allow_macro_instructions_); 5748 VIXL_ASSERT(OutsideITBlock()); 5749 MacroEmissionCheckScope guard(this); 5750 ITScope it_scope(this, &cond); 5751 vcge(cond, dt, rd, rm, operand); 5752 } 5753 void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5754 Vcge(al, dt, rd, rm, operand); 5755 } 5756 5757 void Vcge( 5758 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5759 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5760 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5761 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5762 VIXL_ASSERT(allow_macro_instructions_); 5763 VIXL_ASSERT(OutsideITBlock()); 5764 MacroEmissionCheckScope guard(this); 5765 ITScope it_scope(this, &cond); 5766 vcge(cond, dt, rd, rn, rm); 5767 } 5768 void Vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5769 Vcge(al, dt, rd, rn, rm); 5770 } 5771 5772 void Vcge( 5773 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5774 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5775 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5777 VIXL_ASSERT(allow_macro_instructions_); 5778 VIXL_ASSERT(OutsideITBlock()); 5779 MacroEmissionCheckScope guard(this); 5780 ITScope it_scope(this, &cond); 5781 vcge(cond, dt, rd, rn, rm); 5782 } 5783 void Vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5784 Vcge(al, dt, rd, rn, rm); 5785 } 5786 5787 void Vcgt(Condition cond, 5788 DataType dt, 5789 DRegister rd, 5790 DRegister rm, 5791 const DOperand& operand) { 5792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5793 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5794 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5795 VIXL_ASSERT(allow_macro_instructions_); 5796 VIXL_ASSERT(OutsideITBlock()); 5797 MacroEmissionCheckScope guard(this); 5798 ITScope it_scope(this, &cond); 5799 vcgt(cond, dt, rd, rm, operand); 5800 } 5801 void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5802 Vcgt(al, dt, rd, rm, operand); 5803 } 5804 5805 void Vcgt(Condition cond, 5806 DataType dt, 5807 QRegister rd, 5808 QRegister rm, 5809 const QOperand& operand) { 5810 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5811 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5812 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5813 VIXL_ASSERT(allow_macro_instructions_); 5814 VIXL_ASSERT(OutsideITBlock()); 5815 MacroEmissionCheckScope guard(this); 5816 ITScope it_scope(this, &cond); 5817 vcgt(cond, dt, rd, rm, operand); 5818 } 5819 void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5820 Vcgt(al, dt, rd, rm, operand); 5821 } 5822 5823 void Vcgt( 5824 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5825 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5826 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5827 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5828 VIXL_ASSERT(allow_macro_instructions_); 5829 VIXL_ASSERT(OutsideITBlock()); 5830 MacroEmissionCheckScope guard(this); 5831 ITScope it_scope(this, &cond); 5832 vcgt(cond, dt, rd, rn, rm); 5833 } 5834 void Vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5835 Vcgt(al, dt, rd, rn, rm); 5836 } 5837 5838 void Vcgt( 5839 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5840 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5841 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5842 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5843 VIXL_ASSERT(allow_macro_instructions_); 5844 VIXL_ASSERT(OutsideITBlock()); 5845 MacroEmissionCheckScope guard(this); 5846 ITScope it_scope(this, &cond); 5847 vcgt(cond, dt, rd, rn, rm); 5848 } 5849 void Vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5850 Vcgt(al, dt, rd, rn, rm); 5851 } 5852 5853 void Vcle(Condition cond, 5854 DataType dt, 5855 DRegister rd, 5856 DRegister rm, 5857 const DOperand& operand) { 5858 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5859 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5860 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5861 VIXL_ASSERT(allow_macro_instructions_); 5862 VIXL_ASSERT(OutsideITBlock()); 5863 MacroEmissionCheckScope guard(this); 5864 ITScope it_scope(this, &cond); 5865 vcle(cond, dt, rd, rm, operand); 5866 } 5867 void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5868 Vcle(al, dt, rd, rm, operand); 5869 } 5870 5871 void Vcle(Condition cond, 5872 DataType dt, 5873 QRegister rd, 5874 QRegister rm, 5875 const QOperand& operand) { 5876 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5877 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5878 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5879 VIXL_ASSERT(allow_macro_instructions_); 5880 VIXL_ASSERT(OutsideITBlock()); 5881 MacroEmissionCheckScope guard(this); 5882 ITScope it_scope(this, &cond); 5883 vcle(cond, dt, rd, rm, operand); 5884 } 5885 void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5886 Vcle(al, dt, rd, rm, operand); 5887 } 5888 5889 void Vcle( 5890 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5891 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5892 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5893 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5894 VIXL_ASSERT(allow_macro_instructions_); 5895 VIXL_ASSERT(OutsideITBlock()); 5896 MacroEmissionCheckScope guard(this); 5897 ITScope it_scope(this, &cond); 5898 vcle(cond, dt, rd, rn, rm); 5899 } 5900 void Vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5901 Vcle(al, dt, rd, rn, rm); 5902 } 5903 5904 void Vcle( 5905 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5906 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5907 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5908 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5909 VIXL_ASSERT(allow_macro_instructions_); 5910 VIXL_ASSERT(OutsideITBlock()); 5911 MacroEmissionCheckScope guard(this); 5912 ITScope it_scope(this, &cond); 5913 vcle(cond, dt, rd, rn, rm); 5914 } 5915 void Vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5916 Vcle(al, dt, rd, rn, rm); 5917 } 5918 5919 void Vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5920 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5921 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5922 VIXL_ASSERT(allow_macro_instructions_); 5923 VIXL_ASSERT(OutsideITBlock()); 5924 MacroEmissionCheckScope guard(this); 5925 ITScope it_scope(this, &cond); 5926 vcls(cond, dt, rd, rm); 5927 } 5928 void Vcls(DataType dt, DRegister rd, DRegister rm) { Vcls(al, dt, rd, rm); } 5929 5930 void Vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) { 5931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5932 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5933 VIXL_ASSERT(allow_macro_instructions_); 5934 VIXL_ASSERT(OutsideITBlock()); 5935 MacroEmissionCheckScope guard(this); 5936 ITScope it_scope(this, &cond); 5937 vcls(cond, dt, rd, rm); 5938 } 5939 void Vcls(DataType dt, QRegister rd, QRegister rm) { Vcls(al, dt, rd, rm); } 5940 5941 void Vclt(Condition cond, 5942 DataType dt, 5943 DRegister rd, 5944 DRegister rm, 5945 const DOperand& operand) { 5946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5947 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5948 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5949 VIXL_ASSERT(allow_macro_instructions_); 5950 VIXL_ASSERT(OutsideITBlock()); 5951 MacroEmissionCheckScope guard(this); 5952 ITScope it_scope(this, &cond); 5953 vclt(cond, dt, rd, rm, operand); 5954 } 5955 void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5956 Vclt(al, dt, rd, rm, operand); 5957 } 5958 5959 void Vclt(Condition cond, 5960 DataType dt, 5961 QRegister rd, 5962 QRegister rm, 5963 const QOperand& operand) { 5964 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5965 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5966 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5967 VIXL_ASSERT(allow_macro_instructions_); 5968 VIXL_ASSERT(OutsideITBlock()); 5969 MacroEmissionCheckScope guard(this); 5970 ITScope it_scope(this, &cond); 5971 vclt(cond, dt, rd, rm, operand); 5972 } 5973 void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5974 Vclt(al, dt, rd, rm, operand); 5975 } 5976 5977 void Vclt( 5978 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5979 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5980 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5981 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5982 VIXL_ASSERT(allow_macro_instructions_); 5983 VIXL_ASSERT(OutsideITBlock()); 5984 MacroEmissionCheckScope guard(this); 5985 ITScope it_scope(this, &cond); 5986 vclt(cond, dt, rd, rn, rm); 5987 } 5988 void Vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5989 Vclt(al, dt, rd, rn, rm); 5990 } 5991 5992 void Vclt( 5993 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5994 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5995 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5996 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5997 VIXL_ASSERT(allow_macro_instructions_); 5998 VIXL_ASSERT(OutsideITBlock()); 5999 MacroEmissionCheckScope guard(this); 6000 ITScope it_scope(this, &cond); 6001 vclt(cond, dt, rd, rn, rm); 6002 } 6003 void Vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6004 Vclt(al, dt, rd, rn, rm); 6005 } 6006 6007 void Vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6008 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6009 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6010 VIXL_ASSERT(allow_macro_instructions_); 6011 VIXL_ASSERT(OutsideITBlock()); 6012 MacroEmissionCheckScope guard(this); 6013 ITScope it_scope(this, &cond); 6014 vclz(cond, dt, rd, rm); 6015 } 6016 void Vclz(DataType dt, DRegister rd, DRegister rm) { Vclz(al, dt, rd, rm); } 6017 6018 void Vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6019 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6020 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6021 VIXL_ASSERT(allow_macro_instructions_); 6022 VIXL_ASSERT(OutsideITBlock()); 6023 MacroEmissionCheckScope guard(this); 6024 ITScope it_scope(this, &cond); 6025 vclz(cond, dt, rd, rm); 6026 } 6027 void Vclz(DataType dt, QRegister rd, QRegister rm) { Vclz(al, dt, rd, rm); } 6028 6029 void Vcmp(Condition cond, DataType dt, SRegister rd, SRegister rm) { 6030 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6031 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6032 VIXL_ASSERT(allow_macro_instructions_); 6033 VIXL_ASSERT(OutsideITBlock()); 6034 MacroEmissionCheckScope guard(this); 6035 ITScope it_scope(this, &cond); 6036 vcmp(cond, dt, rd, rm); 6037 } 6038 void Vcmp(DataType dt, SRegister rd, SRegister rm) { Vcmp(al, dt, rd, rm); } 6039 6040 void Vcmp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6042 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6043 VIXL_ASSERT(allow_macro_instructions_); 6044 VIXL_ASSERT(OutsideITBlock()); 6045 MacroEmissionCheckScope guard(this); 6046 ITScope it_scope(this, &cond); 6047 vcmp(cond, dt, rd, rm); 6048 } 6049 void Vcmp(DataType dt, DRegister rd, DRegister rm) { Vcmp(al, dt, rd, rm); } 6050 6051 void Vcmp(Condition cond, DataType dt, SRegister rd, double imm) { 6052 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6053 VIXL_ASSERT(allow_macro_instructions_); 6054 VIXL_ASSERT(OutsideITBlock()); 6055 MacroEmissionCheckScope guard(this); 6056 ITScope it_scope(this, &cond); 6057 vcmp(cond, dt, rd, imm); 6058 } 6059 void Vcmp(DataType dt, SRegister rd, double imm) { Vcmp(al, dt, rd, imm); } 6060 6061 void Vcmp(Condition cond, DataType dt, DRegister rd, double imm) { 6062 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6063 VIXL_ASSERT(allow_macro_instructions_); 6064 VIXL_ASSERT(OutsideITBlock()); 6065 MacroEmissionCheckScope guard(this); 6066 ITScope it_scope(this, &cond); 6067 vcmp(cond, dt, rd, imm); 6068 } 6069 void Vcmp(DataType dt, DRegister rd, double imm) { Vcmp(al, dt, rd, imm); } 6070 6071 void Vcmpe(Condition cond, DataType dt, SRegister rd, SRegister rm) { 6072 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6073 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6074 VIXL_ASSERT(allow_macro_instructions_); 6075 VIXL_ASSERT(OutsideITBlock()); 6076 MacroEmissionCheckScope guard(this); 6077 ITScope it_scope(this, &cond); 6078 vcmpe(cond, dt, rd, rm); 6079 } 6080 void Vcmpe(DataType dt, SRegister rd, SRegister rm) { Vcmpe(al, dt, rd, rm); } 6081 6082 void Vcmpe(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6083 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6084 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6085 VIXL_ASSERT(allow_macro_instructions_); 6086 VIXL_ASSERT(OutsideITBlock()); 6087 MacroEmissionCheckScope guard(this); 6088 ITScope it_scope(this, &cond); 6089 vcmpe(cond, dt, rd, rm); 6090 } 6091 void Vcmpe(DataType dt, DRegister rd, DRegister rm) { Vcmpe(al, dt, rd, rm); } 6092 6093 void Vcmpe(Condition cond, DataType dt, SRegister rd, double imm) { 6094 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6095 VIXL_ASSERT(allow_macro_instructions_); 6096 VIXL_ASSERT(OutsideITBlock()); 6097 MacroEmissionCheckScope guard(this); 6098 ITScope it_scope(this, &cond); 6099 vcmpe(cond, dt, rd, imm); 6100 } 6101 void Vcmpe(DataType dt, SRegister rd, double imm) { Vcmpe(al, dt, rd, imm); } 6102 6103 void Vcmpe(Condition cond, DataType dt, DRegister rd, double imm) { 6104 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6105 VIXL_ASSERT(allow_macro_instructions_); 6106 VIXL_ASSERT(OutsideITBlock()); 6107 MacroEmissionCheckScope guard(this); 6108 ITScope it_scope(this, &cond); 6109 vcmpe(cond, dt, rd, imm); 6110 } 6111 void Vcmpe(DataType dt, DRegister rd, double imm) { Vcmpe(al, dt, rd, imm); } 6112 6113 void Vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6114 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6115 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6116 VIXL_ASSERT(allow_macro_instructions_); 6117 VIXL_ASSERT(OutsideITBlock()); 6118 MacroEmissionCheckScope guard(this); 6119 ITScope it_scope(this, &cond); 6120 vcnt(cond, dt, rd, rm); 6121 } 6122 void Vcnt(DataType dt, DRegister rd, DRegister rm) { Vcnt(al, dt, rd, rm); } 6123 6124 void Vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6125 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6126 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6127 VIXL_ASSERT(allow_macro_instructions_); 6128 VIXL_ASSERT(OutsideITBlock()); 6129 MacroEmissionCheckScope guard(this); 6130 ITScope it_scope(this, &cond); 6131 vcnt(cond, dt, rd, rm); 6132 } 6133 void Vcnt(DataType dt, QRegister rd, QRegister rm) { Vcnt(al, dt, rd, rm); } 6134 6135 void Vcvt( 6136 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6137 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6138 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6139 VIXL_ASSERT(allow_macro_instructions_); 6140 VIXL_ASSERT(OutsideITBlock()); 6141 MacroEmissionCheckScope guard(this); 6142 ITScope it_scope(this, &cond); 6143 vcvt(cond, dt1, dt2, rd, rm); 6144 } 6145 void Vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6146 Vcvt(al, dt1, dt2, rd, rm); 6147 } 6148 6149 void Vcvt( 6150 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6152 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6153 VIXL_ASSERT(allow_macro_instructions_); 6154 VIXL_ASSERT(OutsideITBlock()); 6155 MacroEmissionCheckScope guard(this); 6156 ITScope it_scope(this, &cond); 6157 vcvt(cond, dt1, dt2, rd, rm); 6158 } 6159 void Vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6160 Vcvt(al, dt1, dt2, rd, rm); 6161 } 6162 6163 void Vcvt(Condition cond, 6164 DataType dt1, 6165 DataType dt2, 6166 DRegister rd, 6167 DRegister rm, 6168 int32_t fbits) { 6169 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6170 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6171 VIXL_ASSERT(allow_macro_instructions_); 6172 VIXL_ASSERT(OutsideITBlock()); 6173 MacroEmissionCheckScope guard(this); 6174 ITScope it_scope(this, &cond); 6175 vcvt(cond, dt1, dt2, rd, rm, fbits); 6176 } 6177 void Vcvt( 6178 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { 6179 Vcvt(al, dt1, dt2, rd, rm, fbits); 6180 } 6181 6182 void Vcvt(Condition cond, 6183 DataType dt1, 6184 DataType dt2, 6185 QRegister rd, 6186 QRegister rm, 6187 int32_t fbits) { 6188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6189 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6190 VIXL_ASSERT(allow_macro_instructions_); 6191 VIXL_ASSERT(OutsideITBlock()); 6192 MacroEmissionCheckScope guard(this); 6193 ITScope it_scope(this, &cond); 6194 vcvt(cond, dt1, dt2, rd, rm, fbits); 6195 } 6196 void Vcvt( 6197 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { 6198 Vcvt(al, dt1, dt2, rd, rm, fbits); 6199 } 6200 6201 void Vcvt(Condition cond, 6202 DataType dt1, 6203 DataType dt2, 6204 SRegister rd, 6205 SRegister rm, 6206 int32_t fbits) { 6207 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6208 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6209 VIXL_ASSERT(allow_macro_instructions_); 6210 VIXL_ASSERT(OutsideITBlock()); 6211 MacroEmissionCheckScope guard(this); 6212 ITScope it_scope(this, &cond); 6213 vcvt(cond, dt1, dt2, rd, rm, fbits); 6214 } 6215 void Vcvt( 6216 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { 6217 Vcvt(al, dt1, dt2, rd, rm, fbits); 6218 } 6219 6220 void Vcvt( 6221 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6222 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6223 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6224 VIXL_ASSERT(allow_macro_instructions_); 6225 VIXL_ASSERT(OutsideITBlock()); 6226 MacroEmissionCheckScope guard(this); 6227 ITScope it_scope(this, &cond); 6228 vcvt(cond, dt1, dt2, rd, rm); 6229 } 6230 void Vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6231 Vcvt(al, dt1, dt2, rd, rm); 6232 } 6233 6234 void Vcvt( 6235 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6236 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6237 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6238 VIXL_ASSERT(allow_macro_instructions_); 6239 VIXL_ASSERT(OutsideITBlock()); 6240 MacroEmissionCheckScope guard(this); 6241 ITScope it_scope(this, &cond); 6242 vcvt(cond, dt1, dt2, rd, rm); 6243 } 6244 void Vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6245 Vcvt(al, dt1, dt2, rd, rm); 6246 } 6247 6248 void Vcvt( 6249 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 6250 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6251 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6252 VIXL_ASSERT(allow_macro_instructions_); 6253 VIXL_ASSERT(OutsideITBlock()); 6254 MacroEmissionCheckScope guard(this); 6255 ITScope it_scope(this, &cond); 6256 vcvt(cond, dt1, dt2, rd, rm); 6257 } 6258 void Vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 6259 Vcvt(al, dt1, dt2, rd, rm); 6260 } 6261 6262 void Vcvt( 6263 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 6264 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6265 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6266 VIXL_ASSERT(allow_macro_instructions_); 6267 VIXL_ASSERT(OutsideITBlock()); 6268 MacroEmissionCheckScope guard(this); 6269 ITScope it_scope(this, &cond); 6270 vcvt(cond, dt1, dt2, rd, rm); 6271 } 6272 void Vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 6273 Vcvt(al, dt1, dt2, rd, rm); 6274 } 6275 6276 void Vcvt( 6277 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6278 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6279 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6280 VIXL_ASSERT(allow_macro_instructions_); 6281 VIXL_ASSERT(OutsideITBlock()); 6282 MacroEmissionCheckScope guard(this); 6283 ITScope it_scope(this, &cond); 6284 vcvt(cond, dt1, dt2, rd, rm); 6285 } 6286 void Vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6287 Vcvt(al, dt1, dt2, rd, rm); 6288 } 6289 6290 void Vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6291 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6292 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6293 VIXL_ASSERT(allow_macro_instructions_); 6294 VIXL_ASSERT(OutsideITBlock()); 6295 MacroEmissionCheckScope guard(this); 6296 vcvta(dt1, dt2, rd, rm); 6297 } 6298 6299 void Vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6300 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6301 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6302 VIXL_ASSERT(allow_macro_instructions_); 6303 VIXL_ASSERT(OutsideITBlock()); 6304 MacroEmissionCheckScope guard(this); 6305 vcvta(dt1, dt2, rd, rm); 6306 } 6307 6308 void Vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6310 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6311 VIXL_ASSERT(allow_macro_instructions_); 6312 VIXL_ASSERT(OutsideITBlock()); 6313 MacroEmissionCheckScope guard(this); 6314 vcvta(dt1, dt2, rd, rm); 6315 } 6316 6317 void Vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6318 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6319 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6320 VIXL_ASSERT(allow_macro_instructions_); 6321 VIXL_ASSERT(OutsideITBlock()); 6322 MacroEmissionCheckScope guard(this); 6323 vcvta(dt1, dt2, rd, rm); 6324 } 6325 6326 void Vcvtb( 6327 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6330 VIXL_ASSERT(allow_macro_instructions_); 6331 VIXL_ASSERT(OutsideITBlock()); 6332 MacroEmissionCheckScope guard(this); 6333 ITScope it_scope(this, &cond); 6334 vcvtb(cond, dt1, dt2, rd, rm); 6335 } 6336 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6337 Vcvtb(al, dt1, dt2, rd, rm); 6338 } 6339 6340 void Vcvtb( 6341 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6342 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6343 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6344 VIXL_ASSERT(allow_macro_instructions_); 6345 VIXL_ASSERT(OutsideITBlock()); 6346 MacroEmissionCheckScope guard(this); 6347 ITScope it_scope(this, &cond); 6348 vcvtb(cond, dt1, dt2, rd, rm); 6349 } 6350 void Vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6351 Vcvtb(al, dt1, dt2, rd, rm); 6352 } 6353 6354 void Vcvtb( 6355 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6356 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6357 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6358 VIXL_ASSERT(allow_macro_instructions_); 6359 VIXL_ASSERT(OutsideITBlock()); 6360 MacroEmissionCheckScope guard(this); 6361 ITScope it_scope(this, &cond); 6362 vcvtb(cond, dt1, dt2, rd, rm); 6363 } 6364 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6365 Vcvtb(al, dt1, dt2, rd, rm); 6366 } 6367 6368 void Vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6369 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6370 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6371 VIXL_ASSERT(allow_macro_instructions_); 6372 VIXL_ASSERT(OutsideITBlock()); 6373 MacroEmissionCheckScope guard(this); 6374 vcvtm(dt1, dt2, rd, rm); 6375 } 6376 6377 void Vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6378 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6379 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6380 VIXL_ASSERT(allow_macro_instructions_); 6381 VIXL_ASSERT(OutsideITBlock()); 6382 MacroEmissionCheckScope guard(this); 6383 vcvtm(dt1, dt2, rd, rm); 6384 } 6385 6386 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6387 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6388 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6389 VIXL_ASSERT(allow_macro_instructions_); 6390 VIXL_ASSERT(OutsideITBlock()); 6391 MacroEmissionCheckScope guard(this); 6392 vcvtm(dt1, dt2, rd, rm); 6393 } 6394 6395 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6396 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6397 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6398 VIXL_ASSERT(allow_macro_instructions_); 6399 VIXL_ASSERT(OutsideITBlock()); 6400 MacroEmissionCheckScope guard(this); 6401 vcvtm(dt1, dt2, rd, rm); 6402 } 6403 6404 void Vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6405 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6406 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6407 VIXL_ASSERT(allow_macro_instructions_); 6408 VIXL_ASSERT(OutsideITBlock()); 6409 MacroEmissionCheckScope guard(this); 6410 vcvtn(dt1, dt2, rd, rm); 6411 } 6412 6413 void Vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6414 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6415 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6416 VIXL_ASSERT(allow_macro_instructions_); 6417 VIXL_ASSERT(OutsideITBlock()); 6418 MacroEmissionCheckScope guard(this); 6419 vcvtn(dt1, dt2, rd, rm); 6420 } 6421 6422 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6423 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6424 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6425 VIXL_ASSERT(allow_macro_instructions_); 6426 VIXL_ASSERT(OutsideITBlock()); 6427 MacroEmissionCheckScope guard(this); 6428 vcvtn(dt1, dt2, rd, rm); 6429 } 6430 6431 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6432 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6433 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6434 VIXL_ASSERT(allow_macro_instructions_); 6435 VIXL_ASSERT(OutsideITBlock()); 6436 MacroEmissionCheckScope guard(this); 6437 vcvtn(dt1, dt2, rd, rm); 6438 } 6439 6440 void Vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6441 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6442 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6443 VIXL_ASSERT(allow_macro_instructions_); 6444 VIXL_ASSERT(OutsideITBlock()); 6445 MacroEmissionCheckScope guard(this); 6446 vcvtp(dt1, dt2, rd, rm); 6447 } 6448 6449 void Vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6450 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6451 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6452 VIXL_ASSERT(allow_macro_instructions_); 6453 VIXL_ASSERT(OutsideITBlock()); 6454 MacroEmissionCheckScope guard(this); 6455 vcvtp(dt1, dt2, rd, rm); 6456 } 6457 6458 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6459 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6460 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6461 VIXL_ASSERT(allow_macro_instructions_); 6462 VIXL_ASSERT(OutsideITBlock()); 6463 MacroEmissionCheckScope guard(this); 6464 vcvtp(dt1, dt2, rd, rm); 6465 } 6466 6467 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6468 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6469 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6470 VIXL_ASSERT(allow_macro_instructions_); 6471 VIXL_ASSERT(OutsideITBlock()); 6472 MacroEmissionCheckScope guard(this); 6473 vcvtp(dt1, dt2, rd, rm); 6474 } 6475 6476 void Vcvtr( 6477 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6478 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6479 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6480 VIXL_ASSERT(allow_macro_instructions_); 6481 VIXL_ASSERT(OutsideITBlock()); 6482 MacroEmissionCheckScope guard(this); 6483 ITScope it_scope(this, &cond); 6484 vcvtr(cond, dt1, dt2, rd, rm); 6485 } 6486 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6487 Vcvtr(al, dt1, dt2, rd, rm); 6488 } 6489 6490 void Vcvtr( 6491 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6492 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6493 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6494 VIXL_ASSERT(allow_macro_instructions_); 6495 VIXL_ASSERT(OutsideITBlock()); 6496 MacroEmissionCheckScope guard(this); 6497 ITScope it_scope(this, &cond); 6498 vcvtr(cond, dt1, dt2, rd, rm); 6499 } 6500 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6501 Vcvtr(al, dt1, dt2, rd, rm); 6502 } 6503 6504 void Vcvtt( 6505 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6506 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6507 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6508 VIXL_ASSERT(allow_macro_instructions_); 6509 VIXL_ASSERT(OutsideITBlock()); 6510 MacroEmissionCheckScope guard(this); 6511 ITScope it_scope(this, &cond); 6512 vcvtt(cond, dt1, dt2, rd, rm); 6513 } 6514 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6515 Vcvtt(al, dt1, dt2, rd, rm); 6516 } 6517 6518 void Vcvtt( 6519 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6520 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6521 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6522 VIXL_ASSERT(allow_macro_instructions_); 6523 VIXL_ASSERT(OutsideITBlock()); 6524 MacroEmissionCheckScope guard(this); 6525 ITScope it_scope(this, &cond); 6526 vcvtt(cond, dt1, dt2, rd, rm); 6527 } 6528 void Vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6529 Vcvtt(al, dt1, dt2, rd, rm); 6530 } 6531 6532 void Vcvtt( 6533 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6534 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6535 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6536 VIXL_ASSERT(allow_macro_instructions_); 6537 VIXL_ASSERT(OutsideITBlock()); 6538 MacroEmissionCheckScope guard(this); 6539 ITScope it_scope(this, &cond); 6540 vcvtt(cond, dt1, dt2, rd, rm); 6541 } 6542 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6543 Vcvtt(al, dt1, dt2, rd, rm); 6544 } 6545 6546 void Vdiv( 6547 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6548 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6549 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6550 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6551 VIXL_ASSERT(allow_macro_instructions_); 6552 VIXL_ASSERT(OutsideITBlock()); 6553 MacroEmissionCheckScope guard(this); 6554 ITScope it_scope(this, &cond); 6555 vdiv(cond, dt, rd, rn, rm); 6556 } 6557 void Vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6558 Vdiv(al, dt, rd, rn, rm); 6559 } 6560 6561 void Vdiv( 6562 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6564 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6565 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6566 VIXL_ASSERT(allow_macro_instructions_); 6567 VIXL_ASSERT(OutsideITBlock()); 6568 MacroEmissionCheckScope guard(this); 6569 ITScope it_scope(this, &cond); 6570 vdiv(cond, dt, rd, rn, rm); 6571 } 6572 void Vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6573 Vdiv(al, dt, rd, rn, rm); 6574 } 6575 6576 void Vdup(Condition cond, DataType dt, QRegister rd, Register rt) { 6577 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6578 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 6579 VIXL_ASSERT(allow_macro_instructions_); 6580 VIXL_ASSERT(OutsideITBlock()); 6581 MacroEmissionCheckScope guard(this); 6582 ITScope it_scope(this, &cond); 6583 vdup(cond, dt, rd, rt); 6584 } 6585 void Vdup(DataType dt, QRegister rd, Register rt) { Vdup(al, dt, rd, rt); } 6586 6587 void Vdup(Condition cond, DataType dt, DRegister rd, Register rt) { 6588 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6589 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 6590 VIXL_ASSERT(allow_macro_instructions_); 6591 VIXL_ASSERT(OutsideITBlock()); 6592 MacroEmissionCheckScope guard(this); 6593 ITScope it_scope(this, &cond); 6594 vdup(cond, dt, rd, rt); 6595 } 6596 void Vdup(DataType dt, DRegister rd, Register rt) { Vdup(al, dt, rd, rt); } 6597 6598 void Vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm) { 6599 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6600 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6601 VIXL_ASSERT(allow_macro_instructions_); 6602 VIXL_ASSERT(OutsideITBlock()); 6603 MacroEmissionCheckScope guard(this); 6604 ITScope it_scope(this, &cond); 6605 vdup(cond, dt, rd, rm); 6606 } 6607 void Vdup(DataType dt, DRegister rd, DRegisterLane rm) { 6608 Vdup(al, dt, rd, rm); 6609 } 6610 6611 void Vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm) { 6612 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6614 VIXL_ASSERT(allow_macro_instructions_); 6615 VIXL_ASSERT(OutsideITBlock()); 6616 MacroEmissionCheckScope guard(this); 6617 ITScope it_scope(this, &cond); 6618 vdup(cond, dt, rd, rm); 6619 } 6620 void Vdup(DataType dt, QRegister rd, DRegisterLane rm) { 6621 Vdup(al, dt, rd, rm); 6622 } 6623 6624 void Veor( 6625 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6626 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6627 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6628 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6629 VIXL_ASSERT(allow_macro_instructions_); 6630 VIXL_ASSERT(OutsideITBlock()); 6631 MacroEmissionCheckScope guard(this); 6632 ITScope it_scope(this, &cond); 6633 veor(cond, dt, rd, rn, rm); 6634 } 6635 void Veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6636 Veor(al, dt, rd, rn, rm); 6637 } 6638 void Veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 6639 Veor(cond, kDataTypeValueNone, rd, rn, rm); 6640 } 6641 void Veor(DRegister rd, DRegister rn, DRegister rm) { 6642 Veor(al, kDataTypeValueNone, rd, rn, rm); 6643 } 6644 6645 void Veor( 6646 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6647 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6648 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6649 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6650 VIXL_ASSERT(allow_macro_instructions_); 6651 VIXL_ASSERT(OutsideITBlock()); 6652 MacroEmissionCheckScope guard(this); 6653 ITScope it_scope(this, &cond); 6654 veor(cond, dt, rd, rn, rm); 6655 } 6656 void Veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6657 Veor(al, dt, rd, rn, rm); 6658 } 6659 void Veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 6660 Veor(cond, kDataTypeValueNone, rd, rn, rm); 6661 } 6662 void Veor(QRegister rd, QRegister rn, QRegister rm) { 6663 Veor(al, kDataTypeValueNone, rd, rn, rm); 6664 } 6665 6666 void Vext(Condition cond, 6667 DataType dt, 6668 DRegister rd, 6669 DRegister rn, 6670 DRegister rm, 6671 const DOperand& operand) { 6672 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6673 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6674 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6675 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6676 VIXL_ASSERT(allow_macro_instructions_); 6677 VIXL_ASSERT(OutsideITBlock()); 6678 MacroEmissionCheckScope guard(this); 6679 ITScope it_scope(this, &cond); 6680 vext(cond, dt, rd, rn, rm, operand); 6681 } 6682 void Vext(DataType dt, 6683 DRegister rd, 6684 DRegister rn, 6685 DRegister rm, 6686 const DOperand& operand) { 6687 Vext(al, dt, rd, rn, rm, operand); 6688 } 6689 6690 void Vext(Condition cond, 6691 DataType dt, 6692 QRegister rd, 6693 QRegister rn, 6694 QRegister rm, 6695 const QOperand& operand) { 6696 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6697 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6698 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6699 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6700 VIXL_ASSERT(allow_macro_instructions_); 6701 VIXL_ASSERT(OutsideITBlock()); 6702 MacroEmissionCheckScope guard(this); 6703 ITScope it_scope(this, &cond); 6704 vext(cond, dt, rd, rn, rm, operand); 6705 } 6706 void Vext(DataType dt, 6707 QRegister rd, 6708 QRegister rn, 6709 QRegister rm, 6710 const QOperand& operand) { 6711 Vext(al, dt, rd, rn, rm, operand); 6712 } 6713 6714 void Vfma( 6715 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6716 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6717 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6718 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6719 VIXL_ASSERT(allow_macro_instructions_); 6720 VIXL_ASSERT(OutsideITBlock()); 6721 MacroEmissionCheckScope guard(this); 6722 ITScope it_scope(this, &cond); 6723 vfma(cond, dt, rd, rn, rm); 6724 } 6725 void Vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6726 Vfma(al, dt, rd, rn, rm); 6727 } 6728 6729 void Vfma( 6730 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6731 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6732 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6733 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6734 VIXL_ASSERT(allow_macro_instructions_); 6735 VIXL_ASSERT(OutsideITBlock()); 6736 MacroEmissionCheckScope guard(this); 6737 ITScope it_scope(this, &cond); 6738 vfma(cond, dt, rd, rn, rm); 6739 } 6740 void Vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6741 Vfma(al, dt, rd, rn, rm); 6742 } 6743 6744 void Vfma( 6745 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6746 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6747 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6748 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6749 VIXL_ASSERT(allow_macro_instructions_); 6750 VIXL_ASSERT(OutsideITBlock()); 6751 MacroEmissionCheckScope guard(this); 6752 ITScope it_scope(this, &cond); 6753 vfma(cond, dt, rd, rn, rm); 6754 } 6755 void Vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6756 Vfma(al, dt, rd, rn, rm); 6757 } 6758 6759 void Vfms( 6760 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6761 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6762 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6763 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6764 VIXL_ASSERT(allow_macro_instructions_); 6765 VIXL_ASSERT(OutsideITBlock()); 6766 MacroEmissionCheckScope guard(this); 6767 ITScope it_scope(this, &cond); 6768 vfms(cond, dt, rd, rn, rm); 6769 } 6770 void Vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6771 Vfms(al, dt, rd, rn, rm); 6772 } 6773 6774 void Vfms( 6775 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6779 VIXL_ASSERT(allow_macro_instructions_); 6780 VIXL_ASSERT(OutsideITBlock()); 6781 MacroEmissionCheckScope guard(this); 6782 ITScope it_scope(this, &cond); 6783 vfms(cond, dt, rd, rn, rm); 6784 } 6785 void Vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6786 Vfms(al, dt, rd, rn, rm); 6787 } 6788 6789 void Vfms( 6790 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6791 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6793 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6794 VIXL_ASSERT(allow_macro_instructions_); 6795 VIXL_ASSERT(OutsideITBlock()); 6796 MacroEmissionCheckScope guard(this); 6797 ITScope it_scope(this, &cond); 6798 vfms(cond, dt, rd, rn, rm); 6799 } 6800 void Vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6801 Vfms(al, dt, rd, rn, rm); 6802 } 6803 6804 void Vfnma( 6805 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6806 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6807 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6808 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6809 VIXL_ASSERT(allow_macro_instructions_); 6810 VIXL_ASSERT(OutsideITBlock()); 6811 MacroEmissionCheckScope guard(this); 6812 ITScope it_scope(this, &cond); 6813 vfnma(cond, dt, rd, rn, rm); 6814 } 6815 void Vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6816 Vfnma(al, dt, rd, rn, rm); 6817 } 6818 6819 void Vfnma( 6820 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6821 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6822 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6823 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6824 VIXL_ASSERT(allow_macro_instructions_); 6825 VIXL_ASSERT(OutsideITBlock()); 6826 MacroEmissionCheckScope guard(this); 6827 ITScope it_scope(this, &cond); 6828 vfnma(cond, dt, rd, rn, rm); 6829 } 6830 void Vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6831 Vfnma(al, dt, rd, rn, rm); 6832 } 6833 6834 void Vfnms( 6835 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6837 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6838 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6839 VIXL_ASSERT(allow_macro_instructions_); 6840 VIXL_ASSERT(OutsideITBlock()); 6841 MacroEmissionCheckScope guard(this); 6842 ITScope it_scope(this, &cond); 6843 vfnms(cond, dt, rd, rn, rm); 6844 } 6845 void Vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6846 Vfnms(al, dt, rd, rn, rm); 6847 } 6848 6849 void Vfnms( 6850 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6851 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6852 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6853 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6854 VIXL_ASSERT(allow_macro_instructions_); 6855 VIXL_ASSERT(OutsideITBlock()); 6856 MacroEmissionCheckScope guard(this); 6857 ITScope it_scope(this, &cond); 6858 vfnms(cond, dt, rd, rn, rm); 6859 } 6860 void Vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6861 Vfnms(al, dt, rd, rn, rm); 6862 } 6863 6864 void Vhadd( 6865 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6867 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6868 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6869 VIXL_ASSERT(allow_macro_instructions_); 6870 VIXL_ASSERT(OutsideITBlock()); 6871 MacroEmissionCheckScope guard(this); 6872 ITScope it_scope(this, &cond); 6873 vhadd(cond, dt, rd, rn, rm); 6874 } 6875 void Vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6876 Vhadd(al, dt, rd, rn, rm); 6877 } 6878 6879 void Vhadd( 6880 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6882 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6883 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6884 VIXL_ASSERT(allow_macro_instructions_); 6885 VIXL_ASSERT(OutsideITBlock()); 6886 MacroEmissionCheckScope guard(this); 6887 ITScope it_scope(this, &cond); 6888 vhadd(cond, dt, rd, rn, rm); 6889 } 6890 void Vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6891 Vhadd(al, dt, rd, rn, rm); 6892 } 6893 6894 void Vhsub( 6895 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6896 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6897 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6898 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6899 VIXL_ASSERT(allow_macro_instructions_); 6900 VIXL_ASSERT(OutsideITBlock()); 6901 MacroEmissionCheckScope guard(this); 6902 ITScope it_scope(this, &cond); 6903 vhsub(cond, dt, rd, rn, rm); 6904 } 6905 void Vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6906 Vhsub(al, dt, rd, rn, rm); 6907 } 6908 6909 void Vhsub( 6910 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6911 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6912 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6913 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6914 VIXL_ASSERT(allow_macro_instructions_); 6915 VIXL_ASSERT(OutsideITBlock()); 6916 MacroEmissionCheckScope guard(this); 6917 ITScope it_scope(this, &cond); 6918 vhsub(cond, dt, rd, rn, rm); 6919 } 6920 void Vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6921 Vhsub(al, dt, rd, rn, rm); 6922 } 6923 6924 void Vld1(Condition cond, 6925 DataType dt, 6926 const NeonRegisterList& nreglist, 6927 const AlignedMemOperand& operand) { 6928 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 6929 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6930 VIXL_ASSERT(allow_macro_instructions_); 6931 VIXL_ASSERT(OutsideITBlock()); 6932 MacroEmissionCheckScope guard(this); 6933 ITScope it_scope(this, &cond); 6934 vld1(cond, dt, nreglist, operand); 6935 } 6936 void Vld1(DataType dt, 6937 const NeonRegisterList& nreglist, 6938 const AlignedMemOperand& operand) { 6939 Vld1(al, dt, nreglist, operand); 6940 } 6941 6942 void Vld2(Condition cond, 6943 DataType dt, 6944 const NeonRegisterList& nreglist, 6945 const AlignedMemOperand& operand) { 6946 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 6947 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6948 VIXL_ASSERT(allow_macro_instructions_); 6949 VIXL_ASSERT(OutsideITBlock()); 6950 MacroEmissionCheckScope guard(this); 6951 ITScope it_scope(this, &cond); 6952 vld2(cond, dt, nreglist, operand); 6953 } 6954 void Vld2(DataType dt, 6955 const NeonRegisterList& nreglist, 6956 const AlignedMemOperand& operand) { 6957 Vld2(al, dt, nreglist, operand); 6958 } 6959 6960 void Vld3(Condition cond, 6961 DataType dt, 6962 const NeonRegisterList& nreglist, 6963 const AlignedMemOperand& operand) { 6964 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 6965 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6966 VIXL_ASSERT(allow_macro_instructions_); 6967 VIXL_ASSERT(OutsideITBlock()); 6968 MacroEmissionCheckScope guard(this); 6969 ITScope it_scope(this, &cond); 6970 vld3(cond, dt, nreglist, operand); 6971 } 6972 void Vld3(DataType dt, 6973 const NeonRegisterList& nreglist, 6974 const AlignedMemOperand& operand) { 6975 Vld3(al, dt, nreglist, operand); 6976 } 6977 6978 void Vld3(Condition cond, 6979 DataType dt, 6980 const NeonRegisterList& nreglist, 6981 const MemOperand& operand) { 6982 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 6983 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6984 VIXL_ASSERT(allow_macro_instructions_); 6985 VIXL_ASSERT(OutsideITBlock()); 6986 MacroEmissionCheckScope guard(this); 6987 ITScope it_scope(this, &cond); 6988 vld3(cond, dt, nreglist, operand); 6989 } 6990 void Vld3(DataType dt, 6991 const NeonRegisterList& nreglist, 6992 const MemOperand& operand) { 6993 Vld3(al, dt, nreglist, operand); 6994 } 6995 6996 void Vld4(Condition cond, 6997 DataType dt, 6998 const NeonRegisterList& nreglist, 6999 const AlignedMemOperand& operand) { 7000 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 7001 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7002 VIXL_ASSERT(allow_macro_instructions_); 7003 VIXL_ASSERT(OutsideITBlock()); 7004 MacroEmissionCheckScope guard(this); 7005 ITScope it_scope(this, &cond); 7006 vld4(cond, dt, nreglist, operand); 7007 } 7008 void Vld4(DataType dt, 7009 const NeonRegisterList& nreglist, 7010 const AlignedMemOperand& operand) { 7011 Vld4(al, dt, nreglist, operand); 7012 } 7013 7014 void Vldm(Condition cond, 7015 DataType dt, 7016 Register rn, 7017 WriteBack write_back, 7018 DRegisterList dreglist) { 7019 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7020 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 7021 VIXL_ASSERT(allow_macro_instructions_); 7022 VIXL_ASSERT(OutsideITBlock()); 7023 MacroEmissionCheckScope guard(this); 7024 ITScope it_scope(this, &cond); 7025 vldm(cond, dt, rn, write_back, dreglist); 7026 } 7027 void Vldm(DataType dt, 7028 Register rn, 7029 WriteBack write_back, 7030 DRegisterList dreglist) { 7031 Vldm(al, dt, rn, write_back, dreglist); 7032 } 7033 void Vldm(Condition cond, 7034 Register rn, 7035 WriteBack write_back, 7036 DRegisterList dreglist) { 7037 Vldm(cond, kDataTypeValueNone, rn, write_back, dreglist); 7038 } 7039 void Vldm(Register rn, WriteBack write_back, DRegisterList dreglist) { 7040 Vldm(al, kDataTypeValueNone, rn, write_back, dreglist); 7041 } 7042 7043 void Vldm(Condition cond, 7044 DataType dt, 7045 Register rn, 7046 WriteBack write_back, 7047 SRegisterList sreglist) { 7048 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7049 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 7050 VIXL_ASSERT(allow_macro_instructions_); 7051 VIXL_ASSERT(OutsideITBlock()); 7052 MacroEmissionCheckScope guard(this); 7053 ITScope it_scope(this, &cond); 7054 vldm(cond, dt, rn, write_back, sreglist); 7055 } 7056 void Vldm(DataType dt, 7057 Register rn, 7058 WriteBack write_back, 7059 SRegisterList sreglist) { 7060 Vldm(al, dt, rn, write_back, sreglist); 7061 } 7062 void Vldm(Condition cond, 7063 Register rn, 7064 WriteBack write_back, 7065 SRegisterList sreglist) { 7066 Vldm(cond, kDataTypeValueNone, rn, write_back, sreglist); 7067 } 7068 void Vldm(Register rn, WriteBack write_back, SRegisterList sreglist) { 7069 Vldm(al, kDataTypeValueNone, rn, write_back, sreglist); 7070 } 7071 7072 void Vldmdb(Condition cond, 7073 DataType dt, 7074 Register rn, 7075 WriteBack write_back, 7076 DRegisterList dreglist) { 7077 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7078 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 7079 VIXL_ASSERT(allow_macro_instructions_); 7080 VIXL_ASSERT(OutsideITBlock()); 7081 MacroEmissionCheckScope guard(this); 7082 ITScope it_scope(this, &cond); 7083 vldmdb(cond, dt, rn, write_back, dreglist); 7084 } 7085 void Vldmdb(DataType dt, 7086 Register rn, 7087 WriteBack write_back, 7088 DRegisterList dreglist) { 7089 Vldmdb(al, dt, rn, write_back, dreglist); 7090 } 7091 void Vldmdb(Condition cond, 7092 Register rn, 7093 WriteBack write_back, 7094 DRegisterList dreglist) { 7095 Vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 7096 } 7097 void Vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 7098 Vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 7099 } 7100 7101 void Vldmdb(Condition cond, 7102 DataType dt, 7103 Register rn, 7104 WriteBack write_back, 7105 SRegisterList sreglist) { 7106 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7107 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 7108 VIXL_ASSERT(allow_macro_instructions_); 7109 VIXL_ASSERT(OutsideITBlock()); 7110 MacroEmissionCheckScope guard(this); 7111 ITScope it_scope(this, &cond); 7112 vldmdb(cond, dt, rn, write_back, sreglist); 7113 } 7114 void Vldmdb(DataType dt, 7115 Register rn, 7116 WriteBack write_back, 7117 SRegisterList sreglist) { 7118 Vldmdb(al, dt, rn, write_back, sreglist); 7119 } 7120 void Vldmdb(Condition cond, 7121 Register rn, 7122 WriteBack write_back, 7123 SRegisterList sreglist) { 7124 Vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 7125 } 7126 void Vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 7127 Vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 7128 } 7129 7130 void Vldmia(Condition cond, 7131 DataType dt, 7132 Register rn, 7133 WriteBack write_back, 7134 DRegisterList dreglist) { 7135 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7136 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 7137 VIXL_ASSERT(allow_macro_instructions_); 7138 VIXL_ASSERT(OutsideITBlock()); 7139 MacroEmissionCheckScope guard(this); 7140 ITScope it_scope(this, &cond); 7141 vldmia(cond, dt, rn, write_back, dreglist); 7142 } 7143 void Vldmia(DataType dt, 7144 Register rn, 7145 WriteBack write_back, 7146 DRegisterList dreglist) { 7147 Vldmia(al, dt, rn, write_back, dreglist); 7148 } 7149 void Vldmia(Condition cond, 7150 Register rn, 7151 WriteBack write_back, 7152 DRegisterList dreglist) { 7153 Vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 7154 } 7155 void Vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 7156 Vldmia(al, kDataTypeValueNone, rn, write_back, dreglist); 7157 } 7158 7159 void Vldmia(Condition cond, 7160 DataType dt, 7161 Register rn, 7162 WriteBack write_back, 7163 SRegisterList sreglist) { 7164 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7165 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 7166 VIXL_ASSERT(allow_macro_instructions_); 7167 VIXL_ASSERT(OutsideITBlock()); 7168 MacroEmissionCheckScope guard(this); 7169 ITScope it_scope(this, &cond); 7170 vldmia(cond, dt, rn, write_back, sreglist); 7171 } 7172 void Vldmia(DataType dt, 7173 Register rn, 7174 WriteBack write_back, 7175 SRegisterList sreglist) { 7176 Vldmia(al, dt, rn, write_back, sreglist); 7177 } 7178 void Vldmia(Condition cond, 7179 Register rn, 7180 WriteBack write_back, 7181 SRegisterList sreglist) { 7182 Vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 7183 } 7184 void Vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 7185 Vldmia(al, kDataTypeValueNone, rn, write_back, sreglist); 7186 } 7187 7188 void Vldr(Condition cond, DataType dt, DRegister rd, Label* label) { 7189 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7190 VIXL_ASSERT(allow_macro_instructions_); 7191 VIXL_ASSERT(OutsideITBlock()); 7192 MacroEmissionCheckScope guard(this); 7193 ITScope it_scope(this, &cond); 7194 vldr(cond, dt, rd, label); 7195 } 7196 void Vldr(DataType dt, DRegister rd, Label* label) { 7197 Vldr(al, dt, rd, label); 7198 } 7199 void Vldr(Condition cond, DRegister rd, Label* label) { 7200 Vldr(cond, Untyped64, rd, label); 7201 } 7202 void Vldr(DRegister rd, Label* label) { Vldr(al, Untyped64, rd, label); } 7203 7204 void Vldr(Condition cond, 7205 DataType dt, 7206 DRegister rd, 7207 const MemOperand& operand) { 7208 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7209 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7210 VIXL_ASSERT(allow_macro_instructions_); 7211 VIXL_ASSERT(OutsideITBlock()); 7212 MacroEmissionCheckScope guard(this); 7213 ITScope it_scope(this, &cond); 7214 vldr(cond, dt, rd, operand); 7215 } 7216 void Vldr(DataType dt, DRegister rd, const MemOperand& operand) { 7217 Vldr(al, dt, rd, operand); 7218 } 7219 void Vldr(Condition cond, DRegister rd, const MemOperand& operand) { 7220 Vldr(cond, Untyped64, rd, operand); 7221 } 7222 void Vldr(DRegister rd, const MemOperand& operand) { 7223 Vldr(al, Untyped64, rd, operand); 7224 } 7225 7226 void Vldr(Condition cond, DataType dt, SRegister rd, Label* label) { 7227 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7228 VIXL_ASSERT(allow_macro_instructions_); 7229 VIXL_ASSERT(OutsideITBlock()); 7230 MacroEmissionCheckScope guard(this); 7231 ITScope it_scope(this, &cond); 7232 vldr(cond, dt, rd, label); 7233 } 7234 void Vldr(DataType dt, SRegister rd, Label* label) { 7235 Vldr(al, dt, rd, label); 7236 } 7237 void Vldr(Condition cond, SRegister rd, Label* label) { 7238 Vldr(cond, Untyped32, rd, label); 7239 } 7240 void Vldr(SRegister rd, Label* label) { Vldr(al, Untyped32, rd, label); } 7241 7242 void Vldr(Condition cond, 7243 DataType dt, 7244 SRegister rd, 7245 const MemOperand& operand) { 7246 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7247 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7248 VIXL_ASSERT(allow_macro_instructions_); 7249 VIXL_ASSERT(OutsideITBlock()); 7250 MacroEmissionCheckScope guard(this); 7251 ITScope it_scope(this, &cond); 7252 vldr(cond, dt, rd, operand); 7253 } 7254 void Vldr(DataType dt, SRegister rd, const MemOperand& operand) { 7255 Vldr(al, dt, rd, operand); 7256 } 7257 void Vldr(Condition cond, SRegister rd, const MemOperand& operand) { 7258 Vldr(cond, Untyped32, rd, operand); 7259 } 7260 void Vldr(SRegister rd, const MemOperand& operand) { 7261 Vldr(al, Untyped32, rd, operand); 7262 } 7263 7264 void Vmax( 7265 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7266 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7267 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7268 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7269 VIXL_ASSERT(allow_macro_instructions_); 7270 VIXL_ASSERT(OutsideITBlock()); 7271 MacroEmissionCheckScope guard(this); 7272 ITScope it_scope(this, &cond); 7273 vmax(cond, dt, rd, rn, rm); 7274 } 7275 void Vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7276 Vmax(al, dt, rd, rn, rm); 7277 } 7278 7279 void Vmax( 7280 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7281 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7282 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7283 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7284 VIXL_ASSERT(allow_macro_instructions_); 7285 VIXL_ASSERT(OutsideITBlock()); 7286 MacroEmissionCheckScope guard(this); 7287 ITScope it_scope(this, &cond); 7288 vmax(cond, dt, rd, rn, rm); 7289 } 7290 void Vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7291 Vmax(al, dt, rd, rn, rm); 7292 } 7293 7294 void Vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7295 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7296 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7297 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7298 VIXL_ASSERT(allow_macro_instructions_); 7299 VIXL_ASSERT(OutsideITBlock()); 7300 MacroEmissionCheckScope guard(this); 7301 vmaxnm(dt, rd, rn, rm); 7302 } 7303 7304 void Vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7305 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7306 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7307 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7308 VIXL_ASSERT(allow_macro_instructions_); 7309 VIXL_ASSERT(OutsideITBlock()); 7310 MacroEmissionCheckScope guard(this); 7311 vmaxnm(dt, rd, rn, rm); 7312 } 7313 7314 void Vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7315 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7316 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7317 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7318 VIXL_ASSERT(allow_macro_instructions_); 7319 VIXL_ASSERT(OutsideITBlock()); 7320 MacroEmissionCheckScope guard(this); 7321 vmaxnm(dt, rd, rn, rm); 7322 } 7323 7324 void Vmin( 7325 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7326 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7327 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7329 VIXL_ASSERT(allow_macro_instructions_); 7330 VIXL_ASSERT(OutsideITBlock()); 7331 MacroEmissionCheckScope guard(this); 7332 ITScope it_scope(this, &cond); 7333 vmin(cond, dt, rd, rn, rm); 7334 } 7335 void Vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7336 Vmin(al, dt, rd, rn, rm); 7337 } 7338 7339 void Vmin( 7340 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7341 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7342 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7343 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7344 VIXL_ASSERT(allow_macro_instructions_); 7345 VIXL_ASSERT(OutsideITBlock()); 7346 MacroEmissionCheckScope guard(this); 7347 ITScope it_scope(this, &cond); 7348 vmin(cond, dt, rd, rn, rm); 7349 } 7350 void Vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7351 Vmin(al, dt, rd, rn, rm); 7352 } 7353 7354 void Vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7355 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7356 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7357 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7358 VIXL_ASSERT(allow_macro_instructions_); 7359 VIXL_ASSERT(OutsideITBlock()); 7360 MacroEmissionCheckScope guard(this); 7361 vminnm(dt, rd, rn, rm); 7362 } 7363 7364 void Vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7365 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7366 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7367 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7368 VIXL_ASSERT(allow_macro_instructions_); 7369 VIXL_ASSERT(OutsideITBlock()); 7370 MacroEmissionCheckScope guard(this); 7371 vminnm(dt, rd, rn, rm); 7372 } 7373 7374 void Vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7375 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7376 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7377 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7378 VIXL_ASSERT(allow_macro_instructions_); 7379 VIXL_ASSERT(OutsideITBlock()); 7380 MacroEmissionCheckScope guard(this); 7381 vminnm(dt, rd, rn, rm); 7382 } 7383 7384 void Vmla(Condition cond, 7385 DataType dt, 7386 DRegister rd, 7387 DRegister rn, 7388 DRegisterLane rm) { 7389 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7390 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7391 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7392 VIXL_ASSERT(allow_macro_instructions_); 7393 VIXL_ASSERT(OutsideITBlock()); 7394 MacroEmissionCheckScope guard(this); 7395 ITScope it_scope(this, &cond); 7396 vmla(cond, dt, rd, rn, rm); 7397 } 7398 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 7399 Vmla(al, dt, rd, rn, rm); 7400 } 7401 7402 void Vmla(Condition cond, 7403 DataType dt, 7404 QRegister rd, 7405 QRegister rn, 7406 DRegisterLane rm) { 7407 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7408 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7409 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7410 VIXL_ASSERT(allow_macro_instructions_); 7411 VIXL_ASSERT(OutsideITBlock()); 7412 MacroEmissionCheckScope guard(this); 7413 ITScope it_scope(this, &cond); 7414 vmla(cond, dt, rd, rn, rm); 7415 } 7416 void Vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 7417 Vmla(al, dt, rd, rn, rm); 7418 } 7419 7420 void Vmla( 7421 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7422 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7423 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7424 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7425 VIXL_ASSERT(allow_macro_instructions_); 7426 VIXL_ASSERT(OutsideITBlock()); 7427 MacroEmissionCheckScope guard(this); 7428 ITScope it_scope(this, &cond); 7429 vmla(cond, dt, rd, rn, rm); 7430 } 7431 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7432 Vmla(al, dt, rd, rn, rm); 7433 } 7434 7435 void Vmla( 7436 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7437 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7438 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7439 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7440 VIXL_ASSERT(allow_macro_instructions_); 7441 VIXL_ASSERT(OutsideITBlock()); 7442 MacroEmissionCheckScope guard(this); 7443 ITScope it_scope(this, &cond); 7444 vmla(cond, dt, rd, rn, rm); 7445 } 7446 void Vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7447 Vmla(al, dt, rd, rn, rm); 7448 } 7449 7450 void Vmla( 7451 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7452 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7453 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7454 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7455 VIXL_ASSERT(allow_macro_instructions_); 7456 VIXL_ASSERT(OutsideITBlock()); 7457 MacroEmissionCheckScope guard(this); 7458 ITScope it_scope(this, &cond); 7459 vmla(cond, dt, rd, rn, rm); 7460 } 7461 void Vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7462 Vmla(al, dt, rd, rn, rm); 7463 } 7464 7465 void Vmlal(Condition cond, 7466 DataType dt, 7467 QRegister rd, 7468 DRegister rn, 7469 DRegisterLane rm) { 7470 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7472 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7473 VIXL_ASSERT(allow_macro_instructions_); 7474 VIXL_ASSERT(OutsideITBlock()); 7475 MacroEmissionCheckScope guard(this); 7476 ITScope it_scope(this, &cond); 7477 vmlal(cond, dt, rd, rn, rm); 7478 } 7479 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 7480 Vmlal(al, dt, rd, rn, rm); 7481 } 7482 7483 void Vmlal( 7484 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7486 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7487 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7488 VIXL_ASSERT(allow_macro_instructions_); 7489 VIXL_ASSERT(OutsideITBlock()); 7490 MacroEmissionCheckScope guard(this); 7491 ITScope it_scope(this, &cond); 7492 vmlal(cond, dt, rd, rn, rm); 7493 } 7494 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7495 Vmlal(al, dt, rd, rn, rm); 7496 } 7497 7498 void Vmls(Condition cond, 7499 DataType dt, 7500 DRegister rd, 7501 DRegister rn, 7502 DRegisterLane rm) { 7503 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7504 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7505 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7506 VIXL_ASSERT(allow_macro_instructions_); 7507 VIXL_ASSERT(OutsideITBlock()); 7508 MacroEmissionCheckScope guard(this); 7509 ITScope it_scope(this, &cond); 7510 vmls(cond, dt, rd, rn, rm); 7511 } 7512 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 7513 Vmls(al, dt, rd, rn, rm); 7514 } 7515 7516 void Vmls(Condition cond, 7517 DataType dt, 7518 QRegister rd, 7519 QRegister rn, 7520 DRegisterLane rm) { 7521 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7522 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7523 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7524 VIXL_ASSERT(allow_macro_instructions_); 7525 VIXL_ASSERT(OutsideITBlock()); 7526 MacroEmissionCheckScope guard(this); 7527 ITScope it_scope(this, &cond); 7528 vmls(cond, dt, rd, rn, rm); 7529 } 7530 void Vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 7531 Vmls(al, dt, rd, rn, rm); 7532 } 7533 7534 void Vmls( 7535 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7536 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7537 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7538 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7539 VIXL_ASSERT(allow_macro_instructions_); 7540 VIXL_ASSERT(OutsideITBlock()); 7541 MacroEmissionCheckScope guard(this); 7542 ITScope it_scope(this, &cond); 7543 vmls(cond, dt, rd, rn, rm); 7544 } 7545 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7546 Vmls(al, dt, rd, rn, rm); 7547 } 7548 7549 void Vmls( 7550 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7551 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7553 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7554 VIXL_ASSERT(allow_macro_instructions_); 7555 VIXL_ASSERT(OutsideITBlock()); 7556 MacroEmissionCheckScope guard(this); 7557 ITScope it_scope(this, &cond); 7558 vmls(cond, dt, rd, rn, rm); 7559 } 7560 void Vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7561 Vmls(al, dt, rd, rn, rm); 7562 } 7563 7564 void Vmls( 7565 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7566 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7567 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7568 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7569 VIXL_ASSERT(allow_macro_instructions_); 7570 VIXL_ASSERT(OutsideITBlock()); 7571 MacroEmissionCheckScope guard(this); 7572 ITScope it_scope(this, &cond); 7573 vmls(cond, dt, rd, rn, rm); 7574 } 7575 void Vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7576 Vmls(al, dt, rd, rn, rm); 7577 } 7578 7579 void Vmlsl(Condition cond, 7580 DataType dt, 7581 QRegister rd, 7582 DRegister rn, 7583 DRegisterLane rm) { 7584 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7585 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7586 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7587 VIXL_ASSERT(allow_macro_instructions_); 7588 VIXL_ASSERT(OutsideITBlock()); 7589 MacroEmissionCheckScope guard(this); 7590 ITScope it_scope(this, &cond); 7591 vmlsl(cond, dt, rd, rn, rm); 7592 } 7593 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 7594 Vmlsl(al, dt, rd, rn, rm); 7595 } 7596 7597 void Vmlsl( 7598 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7599 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7600 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7601 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7602 VIXL_ASSERT(allow_macro_instructions_); 7603 VIXL_ASSERT(OutsideITBlock()); 7604 MacroEmissionCheckScope guard(this); 7605 ITScope it_scope(this, &cond); 7606 vmlsl(cond, dt, rd, rn, rm); 7607 } 7608 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7609 Vmlsl(al, dt, rd, rn, rm); 7610 } 7611 7612 void Vmov(Condition cond, Register rt, SRegister rn) { 7613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7614 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7615 VIXL_ASSERT(allow_macro_instructions_); 7616 VIXL_ASSERT(OutsideITBlock()); 7617 MacroEmissionCheckScope guard(this); 7618 ITScope it_scope(this, &cond); 7619 vmov(cond, rt, rn); 7620 } 7621 void Vmov(Register rt, SRegister rn) { Vmov(al, rt, rn); } 7622 7623 void Vmov(Condition cond, SRegister rn, Register rt) { 7624 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7625 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7626 VIXL_ASSERT(allow_macro_instructions_); 7627 VIXL_ASSERT(OutsideITBlock()); 7628 MacroEmissionCheckScope guard(this); 7629 ITScope it_scope(this, &cond); 7630 vmov(cond, rn, rt); 7631 } 7632 void Vmov(SRegister rn, Register rt) { Vmov(al, rn, rt); } 7633 7634 void Vmov(Condition cond, Register rt, Register rt2, DRegister rm) { 7635 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7636 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7637 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7638 VIXL_ASSERT(allow_macro_instructions_); 7639 VIXL_ASSERT(OutsideITBlock()); 7640 MacroEmissionCheckScope guard(this); 7641 ITScope it_scope(this, &cond); 7642 vmov(cond, rt, rt2, rm); 7643 } 7644 void Vmov(Register rt, Register rt2, DRegister rm) { Vmov(al, rt, rt2, rm); } 7645 7646 void Vmov(Condition cond, DRegister rm, Register rt, Register rt2) { 7647 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7648 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7649 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7650 VIXL_ASSERT(allow_macro_instructions_); 7651 VIXL_ASSERT(OutsideITBlock()); 7652 MacroEmissionCheckScope guard(this); 7653 ITScope it_scope(this, &cond); 7654 vmov(cond, rm, rt, rt2); 7655 } 7656 void Vmov(DRegister rm, Register rt, Register rt2) { Vmov(al, rm, rt, rt2); } 7657 7658 void Vmov( 7659 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) { 7660 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7661 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7662 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm1)); 7664 VIXL_ASSERT(allow_macro_instructions_); 7665 VIXL_ASSERT(OutsideITBlock()); 7666 MacroEmissionCheckScope guard(this); 7667 ITScope it_scope(this, &cond); 7668 vmov(cond, rt, rt2, rm, rm1); 7669 } 7670 void Vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) { 7671 Vmov(al, rt, rt2, rm, rm1); 7672 } 7673 7674 void Vmov( 7675 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) { 7676 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm1)); 7678 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7680 VIXL_ASSERT(allow_macro_instructions_); 7681 VIXL_ASSERT(OutsideITBlock()); 7682 MacroEmissionCheckScope guard(this); 7683 ITScope it_scope(this, &cond); 7684 vmov(cond, rm, rm1, rt, rt2); 7685 } 7686 void Vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) { 7687 Vmov(al, rm, rm1, rt, rt2); 7688 } 7689 7690 void Vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt) { 7691 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7692 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7693 VIXL_ASSERT(allow_macro_instructions_); 7694 VIXL_ASSERT(OutsideITBlock()); 7695 MacroEmissionCheckScope guard(this); 7696 ITScope it_scope(this, &cond); 7697 vmov(cond, dt, rd, rt); 7698 } 7699 void Vmov(DataType dt, DRegisterLane rd, Register rt) { 7700 Vmov(al, dt, rd, rt); 7701 } 7702 void Vmov(Condition cond, DRegisterLane rd, Register rt) { 7703 Vmov(cond, kDataTypeValueNone, rd, rt); 7704 } 7705 void Vmov(DRegisterLane rd, Register rt) { 7706 Vmov(al, kDataTypeValueNone, rd, rt); 7707 } 7708 7709 void Vmov(Condition cond, 7710 DataType dt, 7711 DRegister rd, 7712 const DOperand& operand) { 7713 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7714 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7715 VIXL_ASSERT(allow_macro_instructions_); 7716 VIXL_ASSERT(OutsideITBlock()); 7717 MacroEmissionCheckScope guard(this); 7718 ITScope it_scope(this, &cond); 7719 vmov(cond, dt, rd, operand); 7720 } 7721 void Vmov(DataType dt, DRegister rd, const DOperand& operand) { 7722 Vmov(al, dt, rd, operand); 7723 } 7724 7725 void Vmov(Condition cond, 7726 DataType dt, 7727 QRegister rd, 7728 const QOperand& operand) { 7729 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7730 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7731 VIXL_ASSERT(allow_macro_instructions_); 7732 VIXL_ASSERT(OutsideITBlock()); 7733 MacroEmissionCheckScope guard(this); 7734 ITScope it_scope(this, &cond); 7735 vmov(cond, dt, rd, operand); 7736 } 7737 void Vmov(DataType dt, QRegister rd, const QOperand& operand) { 7738 Vmov(al, dt, rd, operand); 7739 } 7740 7741 void Vmov(Condition cond, 7742 DataType dt, 7743 SRegister rd, 7744 const SOperand& operand) { 7745 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7746 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7747 VIXL_ASSERT(allow_macro_instructions_); 7748 VIXL_ASSERT(OutsideITBlock()); 7749 MacroEmissionCheckScope guard(this); 7750 ITScope it_scope(this, &cond); 7751 vmov(cond, dt, rd, operand); 7752 } 7753 void Vmov(DataType dt, SRegister rd, const SOperand& operand) { 7754 Vmov(al, dt, rd, operand); 7755 } 7756 7757 void Vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn) { 7758 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7759 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7760 VIXL_ASSERT(allow_macro_instructions_); 7761 VIXL_ASSERT(OutsideITBlock()); 7762 MacroEmissionCheckScope guard(this); 7763 ITScope it_scope(this, &cond); 7764 vmov(cond, dt, rt, rn); 7765 } 7766 void Vmov(DataType dt, Register rt, DRegisterLane rn) { 7767 Vmov(al, dt, rt, rn); 7768 } 7769 void Vmov(Condition cond, Register rt, DRegisterLane rn) { 7770 Vmov(cond, kDataTypeValueNone, rt, rn); 7771 } 7772 void Vmov(Register rt, DRegisterLane rn) { 7773 Vmov(al, kDataTypeValueNone, rt, rn); 7774 } 7775 7776 void Vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) { 7777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7779 VIXL_ASSERT(allow_macro_instructions_); 7780 VIXL_ASSERT(OutsideITBlock()); 7781 MacroEmissionCheckScope guard(this); 7782 ITScope it_scope(this, &cond); 7783 vmovl(cond, dt, rd, rm); 7784 } 7785 void Vmovl(DataType dt, QRegister rd, DRegister rm) { Vmovl(al, dt, rd, rm); } 7786 7787 void Vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) { 7788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7789 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7790 VIXL_ASSERT(allow_macro_instructions_); 7791 VIXL_ASSERT(OutsideITBlock()); 7792 MacroEmissionCheckScope guard(this); 7793 ITScope it_scope(this, &cond); 7794 vmovn(cond, dt, rd, rm); 7795 } 7796 void Vmovn(DataType dt, DRegister rd, QRegister rm) { Vmovn(al, dt, rd, rm); } 7797 7798 void Vmrs(Condition cond, 7799 RegisterOrAPSR_nzcv rt, 7800 SpecialFPRegister spec_reg) { 7801 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7802 VIXL_ASSERT(allow_macro_instructions_); 7803 VIXL_ASSERT(OutsideITBlock()); 7804 MacroEmissionCheckScope guard(this); 7805 ITScope it_scope(this, &cond); 7806 vmrs(cond, rt, spec_reg); 7807 } 7808 void Vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) { 7809 Vmrs(al, rt, spec_reg); 7810 } 7811 7812 void Vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) { 7813 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7814 VIXL_ASSERT(allow_macro_instructions_); 7815 VIXL_ASSERT(OutsideITBlock()); 7816 MacroEmissionCheckScope guard(this); 7817 ITScope it_scope(this, &cond); 7818 vmsr(cond, spec_reg, rt); 7819 } 7820 void Vmsr(SpecialFPRegister spec_reg, Register rt) { Vmsr(al, spec_reg, rt); } 7821 7822 void Vmul(Condition cond, 7823 DataType dt, 7824 DRegister rd, 7825 DRegister rn, 7826 DRegister dm, 7827 unsigned index) { 7828 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7829 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7830 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 7831 VIXL_ASSERT(allow_macro_instructions_); 7832 VIXL_ASSERT(OutsideITBlock()); 7833 MacroEmissionCheckScope guard(this); 7834 ITScope it_scope(this, &cond); 7835 vmul(cond, dt, rd, rn, dm, index); 7836 } 7837 void Vmul( 7838 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) { 7839 Vmul(al, dt, rd, rn, dm, index); 7840 } 7841 7842 void Vmul(Condition cond, 7843 DataType dt, 7844 QRegister rd, 7845 QRegister rn, 7846 DRegister dm, 7847 unsigned index) { 7848 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7849 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7850 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 7851 VIXL_ASSERT(allow_macro_instructions_); 7852 VIXL_ASSERT(OutsideITBlock()); 7853 MacroEmissionCheckScope guard(this); 7854 ITScope it_scope(this, &cond); 7855 vmul(cond, dt, rd, rn, dm, index); 7856 } 7857 void Vmul( 7858 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) { 7859 Vmul(al, dt, rd, rn, dm, index); 7860 } 7861 7862 void Vmul( 7863 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7864 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7865 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7867 VIXL_ASSERT(allow_macro_instructions_); 7868 VIXL_ASSERT(OutsideITBlock()); 7869 MacroEmissionCheckScope guard(this); 7870 ITScope it_scope(this, &cond); 7871 vmul(cond, dt, rd, rn, rm); 7872 } 7873 void Vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7874 Vmul(al, dt, rd, rn, rm); 7875 } 7876 7877 void Vmul( 7878 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7879 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7880 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7882 VIXL_ASSERT(allow_macro_instructions_); 7883 VIXL_ASSERT(OutsideITBlock()); 7884 MacroEmissionCheckScope guard(this); 7885 ITScope it_scope(this, &cond); 7886 vmul(cond, dt, rd, rn, rm); 7887 } 7888 void Vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7889 Vmul(al, dt, rd, rn, rm); 7890 } 7891 7892 void Vmul( 7893 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7894 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7895 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7896 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7897 VIXL_ASSERT(allow_macro_instructions_); 7898 VIXL_ASSERT(OutsideITBlock()); 7899 MacroEmissionCheckScope guard(this); 7900 ITScope it_scope(this, &cond); 7901 vmul(cond, dt, rd, rn, rm); 7902 } 7903 void Vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7904 Vmul(al, dt, rd, rn, rm); 7905 } 7906 7907 void Vmull(Condition cond, 7908 DataType dt, 7909 QRegister rd, 7910 DRegister rn, 7911 DRegister dm, 7912 unsigned index) { 7913 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7914 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7915 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 7916 VIXL_ASSERT(allow_macro_instructions_); 7917 VIXL_ASSERT(OutsideITBlock()); 7918 MacroEmissionCheckScope guard(this); 7919 ITScope it_scope(this, &cond); 7920 vmull(cond, dt, rd, rn, dm, index); 7921 } 7922 void Vmull( 7923 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 7924 Vmull(al, dt, rd, rn, dm, index); 7925 } 7926 7927 void Vmull( 7928 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7929 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7930 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7932 VIXL_ASSERT(allow_macro_instructions_); 7933 VIXL_ASSERT(OutsideITBlock()); 7934 MacroEmissionCheckScope guard(this); 7935 ITScope it_scope(this, &cond); 7936 vmull(cond, dt, rd, rn, rm); 7937 } 7938 void Vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7939 Vmull(al, dt, rd, rn, rm); 7940 } 7941 7942 void Vmvn(Condition cond, 7943 DataType dt, 7944 DRegister rd, 7945 const DOperand& operand) { 7946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7947 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7948 VIXL_ASSERT(allow_macro_instructions_); 7949 VIXL_ASSERT(OutsideITBlock()); 7950 MacroEmissionCheckScope guard(this); 7951 ITScope it_scope(this, &cond); 7952 vmvn(cond, dt, rd, operand); 7953 } 7954 void Vmvn(DataType dt, DRegister rd, const DOperand& operand) { 7955 Vmvn(al, dt, rd, operand); 7956 } 7957 7958 void Vmvn(Condition cond, 7959 DataType dt, 7960 QRegister rd, 7961 const QOperand& operand) { 7962 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7963 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7964 VIXL_ASSERT(allow_macro_instructions_); 7965 VIXL_ASSERT(OutsideITBlock()); 7966 MacroEmissionCheckScope guard(this); 7967 ITScope it_scope(this, &cond); 7968 vmvn(cond, dt, rd, operand); 7969 } 7970 void Vmvn(DataType dt, QRegister rd, const QOperand& operand) { 7971 Vmvn(al, dt, rd, operand); 7972 } 7973 7974 void Vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7975 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7976 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7977 VIXL_ASSERT(allow_macro_instructions_); 7978 VIXL_ASSERT(OutsideITBlock()); 7979 MacroEmissionCheckScope guard(this); 7980 ITScope it_scope(this, &cond); 7981 vneg(cond, dt, rd, rm); 7982 } 7983 void Vneg(DataType dt, DRegister rd, DRegister rm) { Vneg(al, dt, rd, rm); } 7984 7985 void Vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7986 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7987 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7988 VIXL_ASSERT(allow_macro_instructions_); 7989 VIXL_ASSERT(OutsideITBlock()); 7990 MacroEmissionCheckScope guard(this); 7991 ITScope it_scope(this, &cond); 7992 vneg(cond, dt, rd, rm); 7993 } 7994 void Vneg(DataType dt, QRegister rd, QRegister rm) { Vneg(al, dt, rd, rm); } 7995 7996 void Vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) { 7997 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7998 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7999 VIXL_ASSERT(allow_macro_instructions_); 8000 VIXL_ASSERT(OutsideITBlock()); 8001 MacroEmissionCheckScope guard(this); 8002 ITScope it_scope(this, &cond); 8003 vneg(cond, dt, rd, rm); 8004 } 8005 void Vneg(DataType dt, SRegister rd, SRegister rm) { Vneg(al, dt, rd, rm); } 8006 8007 void Vnmla( 8008 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8009 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8010 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8011 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8012 VIXL_ASSERT(allow_macro_instructions_); 8013 VIXL_ASSERT(OutsideITBlock()); 8014 MacroEmissionCheckScope guard(this); 8015 ITScope it_scope(this, &cond); 8016 vnmla(cond, dt, rd, rn, rm); 8017 } 8018 void Vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8019 Vnmla(al, dt, rd, rn, rm); 8020 } 8021 8022 void Vnmla( 8023 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8024 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8025 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8026 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8027 VIXL_ASSERT(allow_macro_instructions_); 8028 VIXL_ASSERT(OutsideITBlock()); 8029 MacroEmissionCheckScope guard(this); 8030 ITScope it_scope(this, &cond); 8031 vnmla(cond, dt, rd, rn, rm); 8032 } 8033 void Vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8034 Vnmla(al, dt, rd, rn, rm); 8035 } 8036 8037 void Vnmls( 8038 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8040 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8042 VIXL_ASSERT(allow_macro_instructions_); 8043 VIXL_ASSERT(OutsideITBlock()); 8044 MacroEmissionCheckScope guard(this); 8045 ITScope it_scope(this, &cond); 8046 vnmls(cond, dt, rd, rn, rm); 8047 } 8048 void Vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8049 Vnmls(al, dt, rd, rn, rm); 8050 } 8051 8052 void Vnmls( 8053 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8054 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8055 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8056 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8057 VIXL_ASSERT(allow_macro_instructions_); 8058 VIXL_ASSERT(OutsideITBlock()); 8059 MacroEmissionCheckScope guard(this); 8060 ITScope it_scope(this, &cond); 8061 vnmls(cond, dt, rd, rn, rm); 8062 } 8063 void Vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8064 Vnmls(al, dt, rd, rn, rm); 8065 } 8066 8067 void Vnmul( 8068 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8069 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8070 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8071 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8072 VIXL_ASSERT(allow_macro_instructions_); 8073 VIXL_ASSERT(OutsideITBlock()); 8074 MacroEmissionCheckScope guard(this); 8075 ITScope it_scope(this, &cond); 8076 vnmul(cond, dt, rd, rn, rm); 8077 } 8078 void Vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8079 Vnmul(al, dt, rd, rn, rm); 8080 } 8081 8082 void Vnmul( 8083 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8084 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8085 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8086 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8087 VIXL_ASSERT(allow_macro_instructions_); 8088 VIXL_ASSERT(OutsideITBlock()); 8089 MacroEmissionCheckScope guard(this); 8090 ITScope it_scope(this, &cond); 8091 vnmul(cond, dt, rd, rn, rm); 8092 } 8093 void Vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8094 Vnmul(al, dt, rd, rn, rm); 8095 } 8096 8097 void Vorn(Condition cond, 8098 DataType dt, 8099 DRegister rd, 8100 DRegister rn, 8101 const DOperand& operand) { 8102 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8103 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8104 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8105 VIXL_ASSERT(allow_macro_instructions_); 8106 VIXL_ASSERT(OutsideITBlock()); 8107 MacroEmissionCheckScope guard(this); 8108 ITScope it_scope(this, &cond); 8109 vorn(cond, dt, rd, rn, operand); 8110 } 8111 void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 8112 Vorn(al, dt, rd, rn, operand); 8113 } 8114 8115 void Vorn(Condition cond, 8116 DataType dt, 8117 QRegister rd, 8118 QRegister rn, 8119 const QOperand& operand) { 8120 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8121 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8122 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8123 VIXL_ASSERT(allow_macro_instructions_); 8124 VIXL_ASSERT(OutsideITBlock()); 8125 MacroEmissionCheckScope guard(this); 8126 ITScope it_scope(this, &cond); 8127 vorn(cond, dt, rd, rn, operand); 8128 } 8129 void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 8130 Vorn(al, dt, rd, rn, operand); 8131 } 8132 8133 void Vorr(Condition cond, 8134 DataType dt, 8135 DRegister rd, 8136 DRegister rn, 8137 const DOperand& operand) { 8138 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8139 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8140 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8141 VIXL_ASSERT(allow_macro_instructions_); 8142 VIXL_ASSERT(OutsideITBlock()); 8143 MacroEmissionCheckScope guard(this); 8144 ITScope it_scope(this, &cond); 8145 vorr(cond, dt, rd, rn, operand); 8146 } 8147 void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 8148 Vorr(al, dt, rd, rn, operand); 8149 } 8150 void Vorr(Condition cond, 8151 DRegister rd, 8152 DRegister rn, 8153 const DOperand& operand) { 8154 Vorr(cond, kDataTypeValueNone, rd, rn, operand); 8155 } 8156 void Vorr(DRegister rd, DRegister rn, const DOperand& operand) { 8157 Vorr(al, kDataTypeValueNone, rd, rn, operand); 8158 } 8159 8160 void Vorr(Condition cond, 8161 DataType dt, 8162 QRegister rd, 8163 QRegister rn, 8164 const QOperand& operand) { 8165 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8166 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8167 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8168 VIXL_ASSERT(allow_macro_instructions_); 8169 VIXL_ASSERT(OutsideITBlock()); 8170 MacroEmissionCheckScope guard(this); 8171 ITScope it_scope(this, &cond); 8172 vorr(cond, dt, rd, rn, operand); 8173 } 8174 void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 8175 Vorr(al, dt, rd, rn, operand); 8176 } 8177 void Vorr(Condition cond, 8178 QRegister rd, 8179 QRegister rn, 8180 const QOperand& operand) { 8181 Vorr(cond, kDataTypeValueNone, rd, rn, operand); 8182 } 8183 void Vorr(QRegister rd, QRegister rn, const QOperand& operand) { 8184 Vorr(al, kDataTypeValueNone, rd, rn, operand); 8185 } 8186 8187 void Vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8189 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8190 VIXL_ASSERT(allow_macro_instructions_); 8191 VIXL_ASSERT(OutsideITBlock()); 8192 MacroEmissionCheckScope guard(this); 8193 ITScope it_scope(this, &cond); 8194 vpadal(cond, dt, rd, rm); 8195 } 8196 void Vpadal(DataType dt, DRegister rd, DRegister rm) { 8197 Vpadal(al, dt, rd, rm); 8198 } 8199 8200 void Vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8201 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8202 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8203 VIXL_ASSERT(allow_macro_instructions_); 8204 VIXL_ASSERT(OutsideITBlock()); 8205 MacroEmissionCheckScope guard(this); 8206 ITScope it_scope(this, &cond); 8207 vpadal(cond, dt, rd, rm); 8208 } 8209 void Vpadal(DataType dt, QRegister rd, QRegister rm) { 8210 Vpadal(al, dt, rd, rm); 8211 } 8212 8213 void Vpadd( 8214 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8215 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8216 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8217 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8218 VIXL_ASSERT(allow_macro_instructions_); 8219 VIXL_ASSERT(OutsideITBlock()); 8220 MacroEmissionCheckScope guard(this); 8221 ITScope it_scope(this, &cond); 8222 vpadd(cond, dt, rd, rn, rm); 8223 } 8224 void Vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8225 Vpadd(al, dt, rd, rn, rm); 8226 } 8227 8228 void Vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8229 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8230 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8231 VIXL_ASSERT(allow_macro_instructions_); 8232 VIXL_ASSERT(OutsideITBlock()); 8233 MacroEmissionCheckScope guard(this); 8234 ITScope it_scope(this, &cond); 8235 vpaddl(cond, dt, rd, rm); 8236 } 8237 void Vpaddl(DataType dt, DRegister rd, DRegister rm) { 8238 Vpaddl(al, dt, rd, rm); 8239 } 8240 8241 void Vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8242 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8243 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8244 VIXL_ASSERT(allow_macro_instructions_); 8245 VIXL_ASSERT(OutsideITBlock()); 8246 MacroEmissionCheckScope guard(this); 8247 ITScope it_scope(this, &cond); 8248 vpaddl(cond, dt, rd, rm); 8249 } 8250 void Vpaddl(DataType dt, QRegister rd, QRegister rm) { 8251 Vpaddl(al, dt, rd, rm); 8252 } 8253 8254 void Vpmax( 8255 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8256 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8257 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8258 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8259 VIXL_ASSERT(allow_macro_instructions_); 8260 VIXL_ASSERT(OutsideITBlock()); 8261 MacroEmissionCheckScope guard(this); 8262 ITScope it_scope(this, &cond); 8263 vpmax(cond, dt, rd, rn, rm); 8264 } 8265 void Vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8266 Vpmax(al, dt, rd, rn, rm); 8267 } 8268 8269 void Vpmin( 8270 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8271 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8272 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8273 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8274 VIXL_ASSERT(allow_macro_instructions_); 8275 VIXL_ASSERT(OutsideITBlock()); 8276 MacroEmissionCheckScope guard(this); 8277 ITScope it_scope(this, &cond); 8278 vpmin(cond, dt, rd, rn, rm); 8279 } 8280 void Vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8281 Vpmin(al, dt, rd, rn, rm); 8282 } 8283 8284 void Vpop(Condition cond, DataType dt, DRegisterList dreglist) { 8285 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 8286 VIXL_ASSERT(allow_macro_instructions_); 8287 VIXL_ASSERT(OutsideITBlock()); 8288 MacroEmissionCheckScope guard(this); 8289 ITScope it_scope(this, &cond); 8290 vpop(cond, dt, dreglist); 8291 } 8292 void Vpop(DataType dt, DRegisterList dreglist) { Vpop(al, dt, dreglist); } 8293 void Vpop(Condition cond, DRegisterList dreglist) { 8294 Vpop(cond, kDataTypeValueNone, dreglist); 8295 } 8296 void Vpop(DRegisterList dreglist) { Vpop(al, kDataTypeValueNone, dreglist); } 8297 8298 void Vpop(Condition cond, DataType dt, SRegisterList sreglist) { 8299 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 8300 VIXL_ASSERT(allow_macro_instructions_); 8301 VIXL_ASSERT(OutsideITBlock()); 8302 MacroEmissionCheckScope guard(this); 8303 ITScope it_scope(this, &cond); 8304 vpop(cond, dt, sreglist); 8305 } 8306 void Vpop(DataType dt, SRegisterList sreglist) { Vpop(al, dt, sreglist); } 8307 void Vpop(Condition cond, SRegisterList sreglist) { 8308 Vpop(cond, kDataTypeValueNone, sreglist); 8309 } 8310 void Vpop(SRegisterList sreglist) { Vpop(al, kDataTypeValueNone, sreglist); } 8311 8312 void Vpush(Condition cond, DataType dt, DRegisterList dreglist) { 8313 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 8314 VIXL_ASSERT(allow_macro_instructions_); 8315 VIXL_ASSERT(OutsideITBlock()); 8316 MacroEmissionCheckScope guard(this); 8317 ITScope it_scope(this, &cond); 8318 vpush(cond, dt, dreglist); 8319 } 8320 void Vpush(DataType dt, DRegisterList dreglist) { Vpush(al, dt, dreglist); } 8321 void Vpush(Condition cond, DRegisterList dreglist) { 8322 Vpush(cond, kDataTypeValueNone, dreglist); 8323 } 8324 void Vpush(DRegisterList dreglist) { 8325 Vpush(al, kDataTypeValueNone, dreglist); 8326 } 8327 8328 void Vpush(Condition cond, DataType dt, SRegisterList sreglist) { 8329 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 8330 VIXL_ASSERT(allow_macro_instructions_); 8331 VIXL_ASSERT(OutsideITBlock()); 8332 MacroEmissionCheckScope guard(this); 8333 ITScope it_scope(this, &cond); 8334 vpush(cond, dt, sreglist); 8335 } 8336 void Vpush(DataType dt, SRegisterList sreglist) { Vpush(al, dt, sreglist); } 8337 void Vpush(Condition cond, SRegisterList sreglist) { 8338 Vpush(cond, kDataTypeValueNone, sreglist); 8339 } 8340 void Vpush(SRegisterList sreglist) { 8341 Vpush(al, kDataTypeValueNone, sreglist); 8342 } 8343 8344 void Vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8345 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8346 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8347 VIXL_ASSERT(allow_macro_instructions_); 8348 VIXL_ASSERT(OutsideITBlock()); 8349 MacroEmissionCheckScope guard(this); 8350 ITScope it_scope(this, &cond); 8351 vqabs(cond, dt, rd, rm); 8352 } 8353 void Vqabs(DataType dt, DRegister rd, DRegister rm) { Vqabs(al, dt, rd, rm); } 8354 8355 void Vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8356 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8357 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8358 VIXL_ASSERT(allow_macro_instructions_); 8359 VIXL_ASSERT(OutsideITBlock()); 8360 MacroEmissionCheckScope guard(this); 8361 ITScope it_scope(this, &cond); 8362 vqabs(cond, dt, rd, rm); 8363 } 8364 void Vqabs(DataType dt, QRegister rd, QRegister rm) { Vqabs(al, dt, rd, rm); } 8365 8366 void Vqadd( 8367 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8368 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8369 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8370 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8371 VIXL_ASSERT(allow_macro_instructions_); 8372 VIXL_ASSERT(OutsideITBlock()); 8373 MacroEmissionCheckScope guard(this); 8374 ITScope it_scope(this, &cond); 8375 vqadd(cond, dt, rd, rn, rm); 8376 } 8377 void Vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8378 Vqadd(al, dt, rd, rn, rm); 8379 } 8380 8381 void Vqadd( 8382 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8383 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8384 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8385 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8386 VIXL_ASSERT(allow_macro_instructions_); 8387 VIXL_ASSERT(OutsideITBlock()); 8388 MacroEmissionCheckScope guard(this); 8389 ITScope it_scope(this, &cond); 8390 vqadd(cond, dt, rd, rn, rm); 8391 } 8392 void Vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8393 Vqadd(al, dt, rd, rn, rm); 8394 } 8395 8396 void Vqdmlal( 8397 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8398 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8399 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8400 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8401 VIXL_ASSERT(allow_macro_instructions_); 8402 VIXL_ASSERT(OutsideITBlock()); 8403 MacroEmissionCheckScope guard(this); 8404 ITScope it_scope(this, &cond); 8405 vqdmlal(cond, dt, rd, rn, rm); 8406 } 8407 void Vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8408 Vqdmlal(al, dt, rd, rn, rm); 8409 } 8410 8411 void Vqdmlal(Condition cond, 8412 DataType dt, 8413 QRegister rd, 8414 DRegister rn, 8415 DRegister dm, 8416 unsigned index) { 8417 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8418 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8419 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 8420 VIXL_ASSERT(allow_macro_instructions_); 8421 VIXL_ASSERT(OutsideITBlock()); 8422 MacroEmissionCheckScope guard(this); 8423 ITScope it_scope(this, &cond); 8424 vqdmlal(cond, dt, rd, rn, dm, index); 8425 } 8426 void Vqdmlal( 8427 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 8428 Vqdmlal(al, dt, rd, rn, dm, index); 8429 } 8430 8431 void Vqdmlsl( 8432 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8433 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8434 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8435 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8436 VIXL_ASSERT(allow_macro_instructions_); 8437 VIXL_ASSERT(OutsideITBlock()); 8438 MacroEmissionCheckScope guard(this); 8439 ITScope it_scope(this, &cond); 8440 vqdmlsl(cond, dt, rd, rn, rm); 8441 } 8442 void Vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8443 Vqdmlsl(al, dt, rd, rn, rm); 8444 } 8445 8446 void Vqdmlsl(Condition cond, 8447 DataType dt, 8448 QRegister rd, 8449 DRegister rn, 8450 DRegister dm, 8451 unsigned index) { 8452 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8453 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8454 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 8455 VIXL_ASSERT(allow_macro_instructions_); 8456 VIXL_ASSERT(OutsideITBlock()); 8457 MacroEmissionCheckScope guard(this); 8458 ITScope it_scope(this, &cond); 8459 vqdmlsl(cond, dt, rd, rn, dm, index); 8460 } 8461 void Vqdmlsl( 8462 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 8463 Vqdmlsl(al, dt, rd, rn, dm, index); 8464 } 8465 8466 void Vqdmulh( 8467 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8468 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8469 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8470 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8471 VIXL_ASSERT(allow_macro_instructions_); 8472 VIXL_ASSERT(OutsideITBlock()); 8473 MacroEmissionCheckScope guard(this); 8474 ITScope it_scope(this, &cond); 8475 vqdmulh(cond, dt, rd, rn, rm); 8476 } 8477 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8478 Vqdmulh(al, dt, rd, rn, rm); 8479 } 8480 8481 void Vqdmulh( 8482 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8483 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8484 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8486 VIXL_ASSERT(allow_macro_instructions_); 8487 VIXL_ASSERT(OutsideITBlock()); 8488 MacroEmissionCheckScope guard(this); 8489 ITScope it_scope(this, &cond); 8490 vqdmulh(cond, dt, rd, rn, rm); 8491 } 8492 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8493 Vqdmulh(al, dt, rd, rn, rm); 8494 } 8495 8496 void Vqdmulh(Condition cond, 8497 DataType dt, 8498 DRegister rd, 8499 DRegister rn, 8500 DRegisterLane rm) { 8501 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8502 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8503 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8504 VIXL_ASSERT(allow_macro_instructions_); 8505 VIXL_ASSERT(OutsideITBlock()); 8506 MacroEmissionCheckScope guard(this); 8507 ITScope it_scope(this, &cond); 8508 vqdmulh(cond, dt, rd, rn, rm); 8509 } 8510 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 8511 Vqdmulh(al, dt, rd, rn, rm); 8512 } 8513 8514 void Vqdmulh(Condition cond, 8515 DataType dt, 8516 QRegister rd, 8517 QRegister rn, 8518 DRegisterLane rm) { 8519 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8520 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8521 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8522 VIXL_ASSERT(allow_macro_instructions_); 8523 VIXL_ASSERT(OutsideITBlock()); 8524 MacroEmissionCheckScope guard(this); 8525 ITScope it_scope(this, &cond); 8526 vqdmulh(cond, dt, rd, rn, rm); 8527 } 8528 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 8529 Vqdmulh(al, dt, rd, rn, rm); 8530 } 8531 8532 void Vqdmull( 8533 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8534 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8535 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8536 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8537 VIXL_ASSERT(allow_macro_instructions_); 8538 VIXL_ASSERT(OutsideITBlock()); 8539 MacroEmissionCheckScope guard(this); 8540 ITScope it_scope(this, &cond); 8541 vqdmull(cond, dt, rd, rn, rm); 8542 } 8543 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8544 Vqdmull(al, dt, rd, rn, rm); 8545 } 8546 8547 void Vqdmull(Condition cond, 8548 DataType dt, 8549 QRegister rd, 8550 DRegister rn, 8551 DRegisterLane rm) { 8552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8553 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8554 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8555 VIXL_ASSERT(allow_macro_instructions_); 8556 VIXL_ASSERT(OutsideITBlock()); 8557 MacroEmissionCheckScope guard(this); 8558 ITScope it_scope(this, &cond); 8559 vqdmull(cond, dt, rd, rn, rm); 8560 } 8561 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 8562 Vqdmull(al, dt, rd, rn, rm); 8563 } 8564 8565 void Vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) { 8566 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8567 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8568 VIXL_ASSERT(allow_macro_instructions_); 8569 VIXL_ASSERT(OutsideITBlock()); 8570 MacroEmissionCheckScope guard(this); 8571 ITScope it_scope(this, &cond); 8572 vqmovn(cond, dt, rd, rm); 8573 } 8574 void Vqmovn(DataType dt, DRegister rd, QRegister rm) { 8575 Vqmovn(al, dt, rd, rm); 8576 } 8577 8578 void Vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm) { 8579 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8580 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8581 VIXL_ASSERT(allow_macro_instructions_); 8582 VIXL_ASSERT(OutsideITBlock()); 8583 MacroEmissionCheckScope guard(this); 8584 ITScope it_scope(this, &cond); 8585 vqmovun(cond, dt, rd, rm); 8586 } 8587 void Vqmovun(DataType dt, DRegister rd, QRegister rm) { 8588 Vqmovun(al, dt, rd, rm); 8589 } 8590 8591 void Vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8592 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8593 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8594 VIXL_ASSERT(allow_macro_instructions_); 8595 VIXL_ASSERT(OutsideITBlock()); 8596 MacroEmissionCheckScope guard(this); 8597 ITScope it_scope(this, &cond); 8598 vqneg(cond, dt, rd, rm); 8599 } 8600 void Vqneg(DataType dt, DRegister rd, DRegister rm) { Vqneg(al, dt, rd, rm); } 8601 8602 void Vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8603 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8604 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8605 VIXL_ASSERT(allow_macro_instructions_); 8606 VIXL_ASSERT(OutsideITBlock()); 8607 MacroEmissionCheckScope guard(this); 8608 ITScope it_scope(this, &cond); 8609 vqneg(cond, dt, rd, rm); 8610 } 8611 void Vqneg(DataType dt, QRegister rd, QRegister rm) { Vqneg(al, dt, rd, rm); } 8612 8613 void Vqrdmulh( 8614 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8615 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8616 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8617 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8618 VIXL_ASSERT(allow_macro_instructions_); 8619 VIXL_ASSERT(OutsideITBlock()); 8620 MacroEmissionCheckScope guard(this); 8621 ITScope it_scope(this, &cond); 8622 vqrdmulh(cond, dt, rd, rn, rm); 8623 } 8624 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8625 Vqrdmulh(al, dt, rd, rn, rm); 8626 } 8627 8628 void Vqrdmulh( 8629 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8630 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8631 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8632 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8633 VIXL_ASSERT(allow_macro_instructions_); 8634 VIXL_ASSERT(OutsideITBlock()); 8635 MacroEmissionCheckScope guard(this); 8636 ITScope it_scope(this, &cond); 8637 vqrdmulh(cond, dt, rd, rn, rm); 8638 } 8639 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8640 Vqrdmulh(al, dt, rd, rn, rm); 8641 } 8642 8643 void Vqrdmulh(Condition cond, 8644 DataType dt, 8645 DRegister rd, 8646 DRegister rn, 8647 DRegisterLane rm) { 8648 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8649 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8650 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8651 VIXL_ASSERT(allow_macro_instructions_); 8652 VIXL_ASSERT(OutsideITBlock()); 8653 MacroEmissionCheckScope guard(this); 8654 ITScope it_scope(this, &cond); 8655 vqrdmulh(cond, dt, rd, rn, rm); 8656 } 8657 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 8658 Vqrdmulh(al, dt, rd, rn, rm); 8659 } 8660 8661 void Vqrdmulh(Condition cond, 8662 DataType dt, 8663 QRegister rd, 8664 QRegister rn, 8665 DRegisterLane rm) { 8666 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8667 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8668 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8669 VIXL_ASSERT(allow_macro_instructions_); 8670 VIXL_ASSERT(OutsideITBlock()); 8671 MacroEmissionCheckScope guard(this); 8672 ITScope it_scope(this, &cond); 8673 vqrdmulh(cond, dt, rd, rn, rm); 8674 } 8675 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 8676 Vqrdmulh(al, dt, rd, rn, rm); 8677 } 8678 8679 void Vqrshl( 8680 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { 8681 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8682 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8683 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8684 VIXL_ASSERT(allow_macro_instructions_); 8685 VIXL_ASSERT(OutsideITBlock()); 8686 MacroEmissionCheckScope guard(this); 8687 ITScope it_scope(this, &cond); 8688 vqrshl(cond, dt, rd, rm, rn); 8689 } 8690 void Vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 8691 Vqrshl(al, dt, rd, rm, rn); 8692 } 8693 8694 void Vqrshl( 8695 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { 8696 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8697 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8698 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8699 VIXL_ASSERT(allow_macro_instructions_); 8700 VIXL_ASSERT(OutsideITBlock()); 8701 MacroEmissionCheckScope guard(this); 8702 ITScope it_scope(this, &cond); 8703 vqrshl(cond, dt, rd, rm, rn); 8704 } 8705 void Vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 8706 Vqrshl(al, dt, rd, rm, rn); 8707 } 8708 8709 void Vqrshrn(Condition cond, 8710 DataType dt, 8711 DRegister rd, 8712 QRegister rm, 8713 const QOperand& operand) { 8714 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8715 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8716 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8717 VIXL_ASSERT(allow_macro_instructions_); 8718 VIXL_ASSERT(OutsideITBlock()); 8719 MacroEmissionCheckScope guard(this); 8720 ITScope it_scope(this, &cond); 8721 vqrshrn(cond, dt, rd, rm, operand); 8722 } 8723 void Vqrshrn(DataType dt, 8724 DRegister rd, 8725 QRegister rm, 8726 const QOperand& operand) { 8727 Vqrshrn(al, dt, rd, rm, operand); 8728 } 8729 8730 void Vqrshrun(Condition cond, 8731 DataType dt, 8732 DRegister rd, 8733 QRegister rm, 8734 const QOperand& operand) { 8735 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8736 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8737 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8738 VIXL_ASSERT(allow_macro_instructions_); 8739 VIXL_ASSERT(OutsideITBlock()); 8740 MacroEmissionCheckScope guard(this); 8741 ITScope it_scope(this, &cond); 8742 vqrshrun(cond, dt, rd, rm, operand); 8743 } 8744 void Vqrshrun(DataType dt, 8745 DRegister rd, 8746 QRegister rm, 8747 const QOperand& operand) { 8748 Vqrshrun(al, dt, rd, rm, operand); 8749 } 8750 8751 void Vqshl(Condition cond, 8752 DataType dt, 8753 DRegister rd, 8754 DRegister rm, 8755 const DOperand& operand) { 8756 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8757 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8758 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8759 VIXL_ASSERT(allow_macro_instructions_); 8760 VIXL_ASSERT(OutsideITBlock()); 8761 MacroEmissionCheckScope guard(this); 8762 ITScope it_scope(this, &cond); 8763 vqshl(cond, dt, rd, rm, operand); 8764 } 8765 void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8766 Vqshl(al, dt, rd, rm, operand); 8767 } 8768 8769 void Vqshl(Condition cond, 8770 DataType dt, 8771 QRegister rd, 8772 QRegister rm, 8773 const QOperand& operand) { 8774 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8775 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8776 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8777 VIXL_ASSERT(allow_macro_instructions_); 8778 VIXL_ASSERT(OutsideITBlock()); 8779 MacroEmissionCheckScope guard(this); 8780 ITScope it_scope(this, &cond); 8781 vqshl(cond, dt, rd, rm, operand); 8782 } 8783 void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8784 Vqshl(al, dt, rd, rm, operand); 8785 } 8786 8787 void Vqshlu(Condition cond, 8788 DataType dt, 8789 DRegister rd, 8790 DRegister rm, 8791 const DOperand& operand) { 8792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8793 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8794 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8795 VIXL_ASSERT(allow_macro_instructions_); 8796 VIXL_ASSERT(OutsideITBlock()); 8797 MacroEmissionCheckScope guard(this); 8798 ITScope it_scope(this, &cond); 8799 vqshlu(cond, dt, rd, rm, operand); 8800 } 8801 void Vqshlu(DataType dt, 8802 DRegister rd, 8803 DRegister rm, 8804 const DOperand& operand) { 8805 Vqshlu(al, dt, rd, rm, operand); 8806 } 8807 8808 void Vqshlu(Condition cond, 8809 DataType dt, 8810 QRegister rd, 8811 QRegister rm, 8812 const QOperand& operand) { 8813 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8814 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8815 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8816 VIXL_ASSERT(allow_macro_instructions_); 8817 VIXL_ASSERT(OutsideITBlock()); 8818 MacroEmissionCheckScope guard(this); 8819 ITScope it_scope(this, &cond); 8820 vqshlu(cond, dt, rd, rm, operand); 8821 } 8822 void Vqshlu(DataType dt, 8823 QRegister rd, 8824 QRegister rm, 8825 const QOperand& operand) { 8826 Vqshlu(al, dt, rd, rm, operand); 8827 } 8828 8829 void Vqshrn(Condition cond, 8830 DataType dt, 8831 DRegister rd, 8832 QRegister rm, 8833 const QOperand& operand) { 8834 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8835 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8836 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8837 VIXL_ASSERT(allow_macro_instructions_); 8838 VIXL_ASSERT(OutsideITBlock()); 8839 MacroEmissionCheckScope guard(this); 8840 ITScope it_scope(this, &cond); 8841 vqshrn(cond, dt, rd, rm, operand); 8842 } 8843 void Vqshrn(DataType dt, 8844 DRegister rd, 8845 QRegister rm, 8846 const QOperand& operand) { 8847 Vqshrn(al, dt, rd, rm, operand); 8848 } 8849 8850 void Vqshrun(Condition cond, 8851 DataType dt, 8852 DRegister rd, 8853 QRegister rm, 8854 const QOperand& operand) { 8855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8856 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8857 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8858 VIXL_ASSERT(allow_macro_instructions_); 8859 VIXL_ASSERT(OutsideITBlock()); 8860 MacroEmissionCheckScope guard(this); 8861 ITScope it_scope(this, &cond); 8862 vqshrun(cond, dt, rd, rm, operand); 8863 } 8864 void Vqshrun(DataType dt, 8865 DRegister rd, 8866 QRegister rm, 8867 const QOperand& operand) { 8868 Vqshrun(al, dt, rd, rm, operand); 8869 } 8870 8871 void Vqsub( 8872 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8873 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8874 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8875 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8876 VIXL_ASSERT(allow_macro_instructions_); 8877 VIXL_ASSERT(OutsideITBlock()); 8878 MacroEmissionCheckScope guard(this); 8879 ITScope it_scope(this, &cond); 8880 vqsub(cond, dt, rd, rn, rm); 8881 } 8882 void Vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8883 Vqsub(al, dt, rd, rn, rm); 8884 } 8885 8886 void Vqsub( 8887 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8888 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8889 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8890 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8891 VIXL_ASSERT(allow_macro_instructions_); 8892 VIXL_ASSERT(OutsideITBlock()); 8893 MacroEmissionCheckScope guard(this); 8894 ITScope it_scope(this, &cond); 8895 vqsub(cond, dt, rd, rn, rm); 8896 } 8897 void Vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8898 Vqsub(al, dt, rd, rn, rm); 8899 } 8900 8901 void Vraddhn( 8902 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 8903 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8904 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8905 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8906 VIXL_ASSERT(allow_macro_instructions_); 8907 VIXL_ASSERT(OutsideITBlock()); 8908 MacroEmissionCheckScope guard(this); 8909 ITScope it_scope(this, &cond); 8910 vraddhn(cond, dt, rd, rn, rm); 8911 } 8912 void Vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 8913 Vraddhn(al, dt, rd, rn, rm); 8914 } 8915 8916 void Vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8917 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8918 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8919 VIXL_ASSERT(allow_macro_instructions_); 8920 VIXL_ASSERT(OutsideITBlock()); 8921 MacroEmissionCheckScope guard(this); 8922 ITScope it_scope(this, &cond); 8923 vrecpe(cond, dt, rd, rm); 8924 } 8925 void Vrecpe(DataType dt, DRegister rd, DRegister rm) { 8926 Vrecpe(al, dt, rd, rm); 8927 } 8928 8929 void Vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8930 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8932 VIXL_ASSERT(allow_macro_instructions_); 8933 VIXL_ASSERT(OutsideITBlock()); 8934 MacroEmissionCheckScope guard(this); 8935 ITScope it_scope(this, &cond); 8936 vrecpe(cond, dt, rd, rm); 8937 } 8938 void Vrecpe(DataType dt, QRegister rd, QRegister rm) { 8939 Vrecpe(al, dt, rd, rm); 8940 } 8941 8942 void Vrecps( 8943 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8944 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8947 VIXL_ASSERT(allow_macro_instructions_); 8948 VIXL_ASSERT(OutsideITBlock()); 8949 MacroEmissionCheckScope guard(this); 8950 ITScope it_scope(this, &cond); 8951 vrecps(cond, dt, rd, rn, rm); 8952 } 8953 void Vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8954 Vrecps(al, dt, rd, rn, rm); 8955 } 8956 8957 void Vrecps( 8958 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8959 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8960 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8961 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8962 VIXL_ASSERT(allow_macro_instructions_); 8963 VIXL_ASSERT(OutsideITBlock()); 8964 MacroEmissionCheckScope guard(this); 8965 ITScope it_scope(this, &cond); 8966 vrecps(cond, dt, rd, rn, rm); 8967 } 8968 void Vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8969 Vrecps(al, dt, rd, rn, rm); 8970 } 8971 8972 void Vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8973 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8974 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8975 VIXL_ASSERT(allow_macro_instructions_); 8976 VIXL_ASSERT(OutsideITBlock()); 8977 MacroEmissionCheckScope guard(this); 8978 ITScope it_scope(this, &cond); 8979 vrev16(cond, dt, rd, rm); 8980 } 8981 void Vrev16(DataType dt, DRegister rd, DRegister rm) { 8982 Vrev16(al, dt, rd, rm); 8983 } 8984 8985 void Vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8986 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8987 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8988 VIXL_ASSERT(allow_macro_instructions_); 8989 VIXL_ASSERT(OutsideITBlock()); 8990 MacroEmissionCheckScope guard(this); 8991 ITScope it_scope(this, &cond); 8992 vrev16(cond, dt, rd, rm); 8993 } 8994 void Vrev16(DataType dt, QRegister rd, QRegister rm) { 8995 Vrev16(al, dt, rd, rm); 8996 } 8997 8998 void Vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8999 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9000 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9001 VIXL_ASSERT(allow_macro_instructions_); 9002 VIXL_ASSERT(OutsideITBlock()); 9003 MacroEmissionCheckScope guard(this); 9004 ITScope it_scope(this, &cond); 9005 vrev32(cond, dt, rd, rm); 9006 } 9007 void Vrev32(DataType dt, DRegister rd, DRegister rm) { 9008 Vrev32(al, dt, rd, rm); 9009 } 9010 9011 void Vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9012 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9013 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9014 VIXL_ASSERT(allow_macro_instructions_); 9015 VIXL_ASSERT(OutsideITBlock()); 9016 MacroEmissionCheckScope guard(this); 9017 ITScope it_scope(this, &cond); 9018 vrev32(cond, dt, rd, rm); 9019 } 9020 void Vrev32(DataType dt, QRegister rd, QRegister rm) { 9021 Vrev32(al, dt, rd, rm); 9022 } 9023 9024 void Vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9025 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9026 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9027 VIXL_ASSERT(allow_macro_instructions_); 9028 VIXL_ASSERT(OutsideITBlock()); 9029 MacroEmissionCheckScope guard(this); 9030 ITScope it_scope(this, &cond); 9031 vrev64(cond, dt, rd, rm); 9032 } 9033 void Vrev64(DataType dt, DRegister rd, DRegister rm) { 9034 Vrev64(al, dt, rd, rm); 9035 } 9036 9037 void Vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9038 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9040 VIXL_ASSERT(allow_macro_instructions_); 9041 VIXL_ASSERT(OutsideITBlock()); 9042 MacroEmissionCheckScope guard(this); 9043 ITScope it_scope(this, &cond); 9044 vrev64(cond, dt, rd, rm); 9045 } 9046 void Vrev64(DataType dt, QRegister rd, QRegister rm) { 9047 Vrev64(al, dt, rd, rm); 9048 } 9049 9050 void Vrhadd( 9051 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9052 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9053 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9054 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9055 VIXL_ASSERT(allow_macro_instructions_); 9056 VIXL_ASSERT(OutsideITBlock()); 9057 MacroEmissionCheckScope guard(this); 9058 ITScope it_scope(this, &cond); 9059 vrhadd(cond, dt, rd, rn, rm); 9060 } 9061 void Vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9062 Vrhadd(al, dt, rd, rn, rm); 9063 } 9064 9065 void Vrhadd( 9066 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9067 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9068 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9069 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9070 VIXL_ASSERT(allow_macro_instructions_); 9071 VIXL_ASSERT(OutsideITBlock()); 9072 MacroEmissionCheckScope guard(this); 9073 ITScope it_scope(this, &cond); 9074 vrhadd(cond, dt, rd, rn, rm); 9075 } 9076 void Vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9077 Vrhadd(al, dt, rd, rn, rm); 9078 } 9079 9080 void Vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9081 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9082 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9083 VIXL_ASSERT(allow_macro_instructions_); 9084 VIXL_ASSERT(OutsideITBlock()); 9085 MacroEmissionCheckScope guard(this); 9086 vrinta(dt1, dt2, rd, rm); 9087 } 9088 9089 void Vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9090 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9091 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9092 VIXL_ASSERT(allow_macro_instructions_); 9093 VIXL_ASSERT(OutsideITBlock()); 9094 MacroEmissionCheckScope guard(this); 9095 vrinta(dt1, dt2, rd, rm); 9096 } 9097 9098 void Vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9099 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9100 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9101 VIXL_ASSERT(allow_macro_instructions_); 9102 VIXL_ASSERT(OutsideITBlock()); 9103 MacroEmissionCheckScope guard(this); 9104 vrinta(dt1, dt2, rd, rm); 9105 } 9106 9107 void Vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9108 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9109 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9110 VIXL_ASSERT(allow_macro_instructions_); 9111 VIXL_ASSERT(OutsideITBlock()); 9112 MacroEmissionCheckScope guard(this); 9113 vrintm(dt1, dt2, rd, rm); 9114 } 9115 9116 void Vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9117 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9118 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9119 VIXL_ASSERT(allow_macro_instructions_); 9120 VIXL_ASSERT(OutsideITBlock()); 9121 MacroEmissionCheckScope guard(this); 9122 vrintm(dt1, dt2, rd, rm); 9123 } 9124 9125 void Vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9126 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9127 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9128 VIXL_ASSERT(allow_macro_instructions_); 9129 VIXL_ASSERT(OutsideITBlock()); 9130 MacroEmissionCheckScope guard(this); 9131 vrintm(dt1, dt2, rd, rm); 9132 } 9133 9134 void Vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9135 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9136 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9137 VIXL_ASSERT(allow_macro_instructions_); 9138 VIXL_ASSERT(OutsideITBlock()); 9139 MacroEmissionCheckScope guard(this); 9140 vrintn(dt1, dt2, rd, rm); 9141 } 9142 9143 void Vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9144 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9145 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9146 VIXL_ASSERT(allow_macro_instructions_); 9147 VIXL_ASSERT(OutsideITBlock()); 9148 MacroEmissionCheckScope guard(this); 9149 vrintn(dt1, dt2, rd, rm); 9150 } 9151 9152 void Vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9153 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9154 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9155 VIXL_ASSERT(allow_macro_instructions_); 9156 VIXL_ASSERT(OutsideITBlock()); 9157 MacroEmissionCheckScope guard(this); 9158 vrintn(dt1, dt2, rd, rm); 9159 } 9160 9161 void Vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9162 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9163 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9164 VIXL_ASSERT(allow_macro_instructions_); 9165 VIXL_ASSERT(OutsideITBlock()); 9166 MacroEmissionCheckScope guard(this); 9167 vrintp(dt1, dt2, rd, rm); 9168 } 9169 9170 void Vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9171 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9172 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9173 VIXL_ASSERT(allow_macro_instructions_); 9174 VIXL_ASSERT(OutsideITBlock()); 9175 MacroEmissionCheckScope guard(this); 9176 vrintp(dt1, dt2, rd, rm); 9177 } 9178 9179 void Vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9180 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9181 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9182 VIXL_ASSERT(allow_macro_instructions_); 9183 VIXL_ASSERT(OutsideITBlock()); 9184 MacroEmissionCheckScope guard(this); 9185 vrintp(dt1, dt2, rd, rm); 9186 } 9187 9188 void Vrintr( 9189 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9190 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9191 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9192 VIXL_ASSERT(allow_macro_instructions_); 9193 VIXL_ASSERT(OutsideITBlock()); 9194 MacroEmissionCheckScope guard(this); 9195 ITScope it_scope(this, &cond); 9196 vrintr(cond, dt1, dt2, rd, rm); 9197 } 9198 void Vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9199 Vrintr(al, dt1, dt2, rd, rm); 9200 } 9201 9202 void Vrintr( 9203 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9204 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9205 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9206 VIXL_ASSERT(allow_macro_instructions_); 9207 VIXL_ASSERT(OutsideITBlock()); 9208 MacroEmissionCheckScope guard(this); 9209 ITScope it_scope(this, &cond); 9210 vrintr(cond, dt1, dt2, rd, rm); 9211 } 9212 void Vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9213 Vrintr(al, dt1, dt2, rd, rm); 9214 } 9215 9216 void Vrintx( 9217 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9218 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9219 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9220 VIXL_ASSERT(allow_macro_instructions_); 9221 VIXL_ASSERT(OutsideITBlock()); 9222 MacroEmissionCheckScope guard(this); 9223 ITScope it_scope(this, &cond); 9224 vrintx(cond, dt1, dt2, rd, rm); 9225 } 9226 void Vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9227 Vrintx(al, dt1, dt2, rd, rm); 9228 } 9229 9230 void Vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9231 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9232 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9233 VIXL_ASSERT(allow_macro_instructions_); 9234 VIXL_ASSERT(OutsideITBlock()); 9235 MacroEmissionCheckScope guard(this); 9236 vrintx(dt1, dt2, rd, rm); 9237 } 9238 9239 void Vrintx( 9240 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9241 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9242 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9243 VIXL_ASSERT(allow_macro_instructions_); 9244 VIXL_ASSERT(OutsideITBlock()); 9245 MacroEmissionCheckScope guard(this); 9246 ITScope it_scope(this, &cond); 9247 vrintx(cond, dt1, dt2, rd, rm); 9248 } 9249 void Vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9250 Vrintx(al, dt1, dt2, rd, rm); 9251 } 9252 9253 void Vrintz( 9254 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9255 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9256 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9257 VIXL_ASSERT(allow_macro_instructions_); 9258 VIXL_ASSERT(OutsideITBlock()); 9259 MacroEmissionCheckScope guard(this); 9260 ITScope it_scope(this, &cond); 9261 vrintz(cond, dt1, dt2, rd, rm); 9262 } 9263 void Vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9264 Vrintz(al, dt1, dt2, rd, rm); 9265 } 9266 9267 void Vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9268 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9269 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9270 VIXL_ASSERT(allow_macro_instructions_); 9271 VIXL_ASSERT(OutsideITBlock()); 9272 MacroEmissionCheckScope guard(this); 9273 vrintz(dt1, dt2, rd, rm); 9274 } 9275 9276 void Vrintz( 9277 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9278 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9279 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9280 VIXL_ASSERT(allow_macro_instructions_); 9281 VIXL_ASSERT(OutsideITBlock()); 9282 MacroEmissionCheckScope guard(this); 9283 ITScope it_scope(this, &cond); 9284 vrintz(cond, dt1, dt2, rd, rm); 9285 } 9286 void Vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9287 Vrintz(al, dt1, dt2, rd, rm); 9288 } 9289 9290 void Vrshl( 9291 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { 9292 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9293 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9294 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9295 VIXL_ASSERT(allow_macro_instructions_); 9296 VIXL_ASSERT(OutsideITBlock()); 9297 MacroEmissionCheckScope guard(this); 9298 ITScope it_scope(this, &cond); 9299 vrshl(cond, dt, rd, rm, rn); 9300 } 9301 void Vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 9302 Vrshl(al, dt, rd, rm, rn); 9303 } 9304 9305 void Vrshl( 9306 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { 9307 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9308 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9310 VIXL_ASSERT(allow_macro_instructions_); 9311 VIXL_ASSERT(OutsideITBlock()); 9312 MacroEmissionCheckScope guard(this); 9313 ITScope it_scope(this, &cond); 9314 vrshl(cond, dt, rd, rm, rn); 9315 } 9316 void Vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 9317 Vrshl(al, dt, rd, rm, rn); 9318 } 9319 9320 void Vrshr(Condition cond, 9321 DataType dt, 9322 DRegister rd, 9323 DRegister rm, 9324 const DOperand& operand) { 9325 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9326 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9327 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9328 VIXL_ASSERT(allow_macro_instructions_); 9329 VIXL_ASSERT(OutsideITBlock()); 9330 MacroEmissionCheckScope guard(this); 9331 ITScope it_scope(this, &cond); 9332 vrshr(cond, dt, rd, rm, operand); 9333 } 9334 void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9335 Vrshr(al, dt, rd, rm, operand); 9336 } 9337 9338 void Vrshr(Condition cond, 9339 DataType dt, 9340 QRegister rd, 9341 QRegister rm, 9342 const QOperand& operand) { 9343 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9344 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9345 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9346 VIXL_ASSERT(allow_macro_instructions_); 9347 VIXL_ASSERT(OutsideITBlock()); 9348 MacroEmissionCheckScope guard(this); 9349 ITScope it_scope(this, &cond); 9350 vrshr(cond, dt, rd, rm, operand); 9351 } 9352 void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9353 Vrshr(al, dt, rd, rm, operand); 9354 } 9355 9356 void Vrshrn(Condition cond, 9357 DataType dt, 9358 DRegister rd, 9359 QRegister rm, 9360 const QOperand& operand) { 9361 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9362 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9363 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9364 VIXL_ASSERT(allow_macro_instructions_); 9365 VIXL_ASSERT(OutsideITBlock()); 9366 MacroEmissionCheckScope guard(this); 9367 ITScope it_scope(this, &cond); 9368 vrshrn(cond, dt, rd, rm, operand); 9369 } 9370 void Vrshrn(DataType dt, 9371 DRegister rd, 9372 QRegister rm, 9373 const QOperand& operand) { 9374 Vrshrn(al, dt, rd, rm, operand); 9375 } 9376 9377 void Vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9378 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9379 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9380 VIXL_ASSERT(allow_macro_instructions_); 9381 VIXL_ASSERT(OutsideITBlock()); 9382 MacroEmissionCheckScope guard(this); 9383 ITScope it_scope(this, &cond); 9384 vrsqrte(cond, dt, rd, rm); 9385 } 9386 void Vrsqrte(DataType dt, DRegister rd, DRegister rm) { 9387 Vrsqrte(al, dt, rd, rm); 9388 } 9389 9390 void Vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9391 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9392 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9393 VIXL_ASSERT(allow_macro_instructions_); 9394 VIXL_ASSERT(OutsideITBlock()); 9395 MacroEmissionCheckScope guard(this); 9396 ITScope it_scope(this, &cond); 9397 vrsqrte(cond, dt, rd, rm); 9398 } 9399 void Vrsqrte(DataType dt, QRegister rd, QRegister rm) { 9400 Vrsqrte(al, dt, rd, rm); 9401 } 9402 9403 void Vrsqrts( 9404 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9405 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9406 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9407 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9408 VIXL_ASSERT(allow_macro_instructions_); 9409 VIXL_ASSERT(OutsideITBlock()); 9410 MacroEmissionCheckScope guard(this); 9411 ITScope it_scope(this, &cond); 9412 vrsqrts(cond, dt, rd, rn, rm); 9413 } 9414 void Vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9415 Vrsqrts(al, dt, rd, rn, rm); 9416 } 9417 9418 void Vrsqrts( 9419 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9420 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9421 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9422 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9423 VIXL_ASSERT(allow_macro_instructions_); 9424 VIXL_ASSERT(OutsideITBlock()); 9425 MacroEmissionCheckScope guard(this); 9426 ITScope it_scope(this, &cond); 9427 vrsqrts(cond, dt, rd, rn, rm); 9428 } 9429 void Vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9430 Vrsqrts(al, dt, rd, rn, rm); 9431 } 9432 9433 void Vrsra(Condition cond, 9434 DataType dt, 9435 DRegister rd, 9436 DRegister rm, 9437 const DOperand& operand) { 9438 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9439 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9440 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9441 VIXL_ASSERT(allow_macro_instructions_); 9442 VIXL_ASSERT(OutsideITBlock()); 9443 MacroEmissionCheckScope guard(this); 9444 ITScope it_scope(this, &cond); 9445 vrsra(cond, dt, rd, rm, operand); 9446 } 9447 void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9448 Vrsra(al, dt, rd, rm, operand); 9449 } 9450 9451 void Vrsra(Condition cond, 9452 DataType dt, 9453 QRegister rd, 9454 QRegister rm, 9455 const QOperand& operand) { 9456 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9457 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9458 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9459 VIXL_ASSERT(allow_macro_instructions_); 9460 VIXL_ASSERT(OutsideITBlock()); 9461 MacroEmissionCheckScope guard(this); 9462 ITScope it_scope(this, &cond); 9463 vrsra(cond, dt, rd, rm, operand); 9464 } 9465 void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9466 Vrsra(al, dt, rd, rm, operand); 9467 } 9468 9469 void Vrsubhn( 9470 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 9471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9472 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9473 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9474 VIXL_ASSERT(allow_macro_instructions_); 9475 VIXL_ASSERT(OutsideITBlock()); 9476 MacroEmissionCheckScope guard(this); 9477 ITScope it_scope(this, &cond); 9478 vrsubhn(cond, dt, rd, rn, rm); 9479 } 9480 void Vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 9481 Vrsubhn(al, dt, rd, rn, rm); 9482 } 9483 9484 void Vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9486 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9487 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9488 VIXL_ASSERT(allow_macro_instructions_); 9489 VIXL_ASSERT(OutsideITBlock()); 9490 MacroEmissionCheckScope guard(this); 9491 vseleq(dt, rd, rn, rm); 9492 } 9493 9494 void Vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9495 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9496 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9497 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9498 VIXL_ASSERT(allow_macro_instructions_); 9499 VIXL_ASSERT(OutsideITBlock()); 9500 MacroEmissionCheckScope guard(this); 9501 vseleq(dt, rd, rn, rm); 9502 } 9503 9504 void Vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9505 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9506 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9507 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9508 VIXL_ASSERT(allow_macro_instructions_); 9509 VIXL_ASSERT(OutsideITBlock()); 9510 MacroEmissionCheckScope guard(this); 9511 vselge(dt, rd, rn, rm); 9512 } 9513 9514 void Vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9515 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9516 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9517 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9518 VIXL_ASSERT(allow_macro_instructions_); 9519 VIXL_ASSERT(OutsideITBlock()); 9520 MacroEmissionCheckScope guard(this); 9521 vselge(dt, rd, rn, rm); 9522 } 9523 9524 void Vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9525 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9526 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9527 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9528 VIXL_ASSERT(allow_macro_instructions_); 9529 VIXL_ASSERT(OutsideITBlock()); 9530 MacroEmissionCheckScope guard(this); 9531 vselgt(dt, rd, rn, rm); 9532 } 9533 9534 void Vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9535 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9536 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9537 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9538 VIXL_ASSERT(allow_macro_instructions_); 9539 VIXL_ASSERT(OutsideITBlock()); 9540 MacroEmissionCheckScope guard(this); 9541 vselgt(dt, rd, rn, rm); 9542 } 9543 9544 void Vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9545 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9546 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9547 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9548 VIXL_ASSERT(allow_macro_instructions_); 9549 VIXL_ASSERT(OutsideITBlock()); 9550 MacroEmissionCheckScope guard(this); 9551 vselvs(dt, rd, rn, rm); 9552 } 9553 9554 void Vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9555 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9556 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9557 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9558 VIXL_ASSERT(allow_macro_instructions_); 9559 VIXL_ASSERT(OutsideITBlock()); 9560 MacroEmissionCheckScope guard(this); 9561 vselvs(dt, rd, rn, rm); 9562 } 9563 9564 void Vshl(Condition cond, 9565 DataType dt, 9566 DRegister rd, 9567 DRegister rm, 9568 const DOperand& operand) { 9569 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9570 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9571 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9572 VIXL_ASSERT(allow_macro_instructions_); 9573 VIXL_ASSERT(OutsideITBlock()); 9574 MacroEmissionCheckScope guard(this); 9575 ITScope it_scope(this, &cond); 9576 vshl(cond, dt, rd, rm, operand); 9577 } 9578 void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9579 Vshl(al, dt, rd, rm, operand); 9580 } 9581 9582 void Vshl(Condition cond, 9583 DataType dt, 9584 QRegister rd, 9585 QRegister rm, 9586 const QOperand& operand) { 9587 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9588 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9589 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9590 VIXL_ASSERT(allow_macro_instructions_); 9591 VIXL_ASSERT(OutsideITBlock()); 9592 MacroEmissionCheckScope guard(this); 9593 ITScope it_scope(this, &cond); 9594 vshl(cond, dt, rd, rm, operand); 9595 } 9596 void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9597 Vshl(al, dt, rd, rm, operand); 9598 } 9599 9600 void Vshll(Condition cond, 9601 DataType dt, 9602 QRegister rd, 9603 DRegister rm, 9604 const DOperand& operand) { 9605 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9606 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9607 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9608 VIXL_ASSERT(allow_macro_instructions_); 9609 VIXL_ASSERT(OutsideITBlock()); 9610 MacroEmissionCheckScope guard(this); 9611 ITScope it_scope(this, &cond); 9612 vshll(cond, dt, rd, rm, operand); 9613 } 9614 void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) { 9615 Vshll(al, dt, rd, rm, operand); 9616 } 9617 9618 void Vshr(Condition cond, 9619 DataType dt, 9620 DRegister rd, 9621 DRegister rm, 9622 const DOperand& operand) { 9623 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9624 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9625 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9626 VIXL_ASSERT(allow_macro_instructions_); 9627 VIXL_ASSERT(OutsideITBlock()); 9628 MacroEmissionCheckScope guard(this); 9629 ITScope it_scope(this, &cond); 9630 vshr(cond, dt, rd, rm, operand); 9631 } 9632 void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9633 Vshr(al, dt, rd, rm, operand); 9634 } 9635 9636 void Vshr(Condition cond, 9637 DataType dt, 9638 QRegister rd, 9639 QRegister rm, 9640 const QOperand& operand) { 9641 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9642 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9643 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9644 VIXL_ASSERT(allow_macro_instructions_); 9645 VIXL_ASSERT(OutsideITBlock()); 9646 MacroEmissionCheckScope guard(this); 9647 ITScope it_scope(this, &cond); 9648 vshr(cond, dt, rd, rm, operand); 9649 } 9650 void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9651 Vshr(al, dt, rd, rm, operand); 9652 } 9653 9654 void Vshrn(Condition cond, 9655 DataType dt, 9656 DRegister rd, 9657 QRegister rm, 9658 const QOperand& operand) { 9659 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9660 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9661 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9662 VIXL_ASSERT(allow_macro_instructions_); 9663 VIXL_ASSERT(OutsideITBlock()); 9664 MacroEmissionCheckScope guard(this); 9665 ITScope it_scope(this, &cond); 9666 vshrn(cond, dt, rd, rm, operand); 9667 } 9668 void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { 9669 Vshrn(al, dt, rd, rm, operand); 9670 } 9671 9672 void Vsli(Condition cond, 9673 DataType dt, 9674 DRegister rd, 9675 DRegister rm, 9676 const DOperand& operand) { 9677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9678 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9679 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9680 VIXL_ASSERT(allow_macro_instructions_); 9681 VIXL_ASSERT(OutsideITBlock()); 9682 MacroEmissionCheckScope guard(this); 9683 ITScope it_scope(this, &cond); 9684 vsli(cond, dt, rd, rm, operand); 9685 } 9686 void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9687 Vsli(al, dt, rd, rm, operand); 9688 } 9689 9690 void Vsli(Condition cond, 9691 DataType dt, 9692 QRegister rd, 9693 QRegister rm, 9694 const QOperand& operand) { 9695 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9696 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9697 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9698 VIXL_ASSERT(allow_macro_instructions_); 9699 VIXL_ASSERT(OutsideITBlock()); 9700 MacroEmissionCheckScope guard(this); 9701 ITScope it_scope(this, &cond); 9702 vsli(cond, dt, rd, rm, operand); 9703 } 9704 void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9705 Vsli(al, dt, rd, rm, operand); 9706 } 9707 9708 void Vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) { 9709 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9710 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9711 VIXL_ASSERT(allow_macro_instructions_); 9712 VIXL_ASSERT(OutsideITBlock()); 9713 MacroEmissionCheckScope guard(this); 9714 ITScope it_scope(this, &cond); 9715 vsqrt(cond, dt, rd, rm); 9716 } 9717 void Vsqrt(DataType dt, SRegister rd, SRegister rm) { Vsqrt(al, dt, rd, rm); } 9718 9719 void Vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9720 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9721 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9722 VIXL_ASSERT(allow_macro_instructions_); 9723 VIXL_ASSERT(OutsideITBlock()); 9724 MacroEmissionCheckScope guard(this); 9725 ITScope it_scope(this, &cond); 9726 vsqrt(cond, dt, rd, rm); 9727 } 9728 void Vsqrt(DataType dt, DRegister rd, DRegister rm) { Vsqrt(al, dt, rd, rm); } 9729 9730 void Vsra(Condition cond, 9731 DataType dt, 9732 DRegister rd, 9733 DRegister rm, 9734 const DOperand& operand) { 9735 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9736 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9737 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9738 VIXL_ASSERT(allow_macro_instructions_); 9739 VIXL_ASSERT(OutsideITBlock()); 9740 MacroEmissionCheckScope guard(this); 9741 ITScope it_scope(this, &cond); 9742 vsra(cond, dt, rd, rm, operand); 9743 } 9744 void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9745 Vsra(al, dt, rd, rm, operand); 9746 } 9747 9748 void Vsra(Condition cond, 9749 DataType dt, 9750 QRegister rd, 9751 QRegister rm, 9752 const QOperand& operand) { 9753 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9754 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9755 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9756 VIXL_ASSERT(allow_macro_instructions_); 9757 VIXL_ASSERT(OutsideITBlock()); 9758 MacroEmissionCheckScope guard(this); 9759 ITScope it_scope(this, &cond); 9760 vsra(cond, dt, rd, rm, operand); 9761 } 9762 void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9763 Vsra(al, dt, rd, rm, operand); 9764 } 9765 9766 void Vsri(Condition cond, 9767 DataType dt, 9768 DRegister rd, 9769 DRegister rm, 9770 const DOperand& operand) { 9771 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9772 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9773 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9774 VIXL_ASSERT(allow_macro_instructions_); 9775 VIXL_ASSERT(OutsideITBlock()); 9776 MacroEmissionCheckScope guard(this); 9777 ITScope it_scope(this, &cond); 9778 vsri(cond, dt, rd, rm, operand); 9779 } 9780 void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9781 Vsri(al, dt, rd, rm, operand); 9782 } 9783 9784 void Vsri(Condition cond, 9785 DataType dt, 9786 QRegister rd, 9787 QRegister rm, 9788 const QOperand& operand) { 9789 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9790 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9791 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9792 VIXL_ASSERT(allow_macro_instructions_); 9793 VIXL_ASSERT(OutsideITBlock()); 9794 MacroEmissionCheckScope guard(this); 9795 ITScope it_scope(this, &cond); 9796 vsri(cond, dt, rd, rm, operand); 9797 } 9798 void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9799 Vsri(al, dt, rd, rm, operand); 9800 } 9801 9802 void Vst1(Condition cond, 9803 DataType dt, 9804 const NeonRegisterList& nreglist, 9805 const AlignedMemOperand& operand) { 9806 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9807 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9808 VIXL_ASSERT(allow_macro_instructions_); 9809 VIXL_ASSERT(OutsideITBlock()); 9810 MacroEmissionCheckScope guard(this); 9811 ITScope it_scope(this, &cond); 9812 vst1(cond, dt, nreglist, operand); 9813 } 9814 void Vst1(DataType dt, 9815 const NeonRegisterList& nreglist, 9816 const AlignedMemOperand& operand) { 9817 Vst1(al, dt, nreglist, operand); 9818 } 9819 9820 void Vst2(Condition cond, 9821 DataType dt, 9822 const NeonRegisterList& nreglist, 9823 const AlignedMemOperand& operand) { 9824 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9825 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9826 VIXL_ASSERT(allow_macro_instructions_); 9827 VIXL_ASSERT(OutsideITBlock()); 9828 MacroEmissionCheckScope guard(this); 9829 ITScope it_scope(this, &cond); 9830 vst2(cond, dt, nreglist, operand); 9831 } 9832 void Vst2(DataType dt, 9833 const NeonRegisterList& nreglist, 9834 const AlignedMemOperand& operand) { 9835 Vst2(al, dt, nreglist, operand); 9836 } 9837 9838 void Vst3(Condition cond, 9839 DataType dt, 9840 const NeonRegisterList& nreglist, 9841 const AlignedMemOperand& operand) { 9842 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9843 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9844 VIXL_ASSERT(allow_macro_instructions_); 9845 VIXL_ASSERT(OutsideITBlock()); 9846 MacroEmissionCheckScope guard(this); 9847 ITScope it_scope(this, &cond); 9848 vst3(cond, dt, nreglist, operand); 9849 } 9850 void Vst3(DataType dt, 9851 const NeonRegisterList& nreglist, 9852 const AlignedMemOperand& operand) { 9853 Vst3(al, dt, nreglist, operand); 9854 } 9855 9856 void Vst3(Condition cond, 9857 DataType dt, 9858 const NeonRegisterList& nreglist, 9859 const MemOperand& operand) { 9860 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9861 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9862 VIXL_ASSERT(allow_macro_instructions_); 9863 VIXL_ASSERT(OutsideITBlock()); 9864 MacroEmissionCheckScope guard(this); 9865 ITScope it_scope(this, &cond); 9866 vst3(cond, dt, nreglist, operand); 9867 } 9868 void Vst3(DataType dt, 9869 const NeonRegisterList& nreglist, 9870 const MemOperand& operand) { 9871 Vst3(al, dt, nreglist, operand); 9872 } 9873 9874 void Vst4(Condition cond, 9875 DataType dt, 9876 const NeonRegisterList& nreglist, 9877 const AlignedMemOperand& operand) { 9878 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9879 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9880 VIXL_ASSERT(allow_macro_instructions_); 9881 VIXL_ASSERT(OutsideITBlock()); 9882 MacroEmissionCheckScope guard(this); 9883 ITScope it_scope(this, &cond); 9884 vst4(cond, dt, nreglist, operand); 9885 } 9886 void Vst4(DataType dt, 9887 const NeonRegisterList& nreglist, 9888 const AlignedMemOperand& operand) { 9889 Vst4(al, dt, nreglist, operand); 9890 } 9891 9892 void Vstm(Condition cond, 9893 DataType dt, 9894 Register rn, 9895 WriteBack write_back, 9896 DRegisterList dreglist) { 9897 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9898 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 9899 VIXL_ASSERT(allow_macro_instructions_); 9900 VIXL_ASSERT(OutsideITBlock()); 9901 MacroEmissionCheckScope guard(this); 9902 ITScope it_scope(this, &cond); 9903 vstm(cond, dt, rn, write_back, dreglist); 9904 } 9905 void Vstm(DataType dt, 9906 Register rn, 9907 WriteBack write_back, 9908 DRegisterList dreglist) { 9909 Vstm(al, dt, rn, write_back, dreglist); 9910 } 9911 void Vstm(Condition cond, 9912 Register rn, 9913 WriteBack write_back, 9914 DRegisterList dreglist) { 9915 Vstm(cond, kDataTypeValueNone, rn, write_back, dreglist); 9916 } 9917 void Vstm(Register rn, WriteBack write_back, DRegisterList dreglist) { 9918 Vstm(al, kDataTypeValueNone, rn, write_back, dreglist); 9919 } 9920 9921 void Vstm(Condition cond, 9922 DataType dt, 9923 Register rn, 9924 WriteBack write_back, 9925 SRegisterList sreglist) { 9926 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9927 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 9928 VIXL_ASSERT(allow_macro_instructions_); 9929 VIXL_ASSERT(OutsideITBlock()); 9930 MacroEmissionCheckScope guard(this); 9931 ITScope it_scope(this, &cond); 9932 vstm(cond, dt, rn, write_back, sreglist); 9933 } 9934 void Vstm(DataType dt, 9935 Register rn, 9936 WriteBack write_back, 9937 SRegisterList sreglist) { 9938 Vstm(al, dt, rn, write_back, sreglist); 9939 } 9940 void Vstm(Condition cond, 9941 Register rn, 9942 WriteBack write_back, 9943 SRegisterList sreglist) { 9944 Vstm(cond, kDataTypeValueNone, rn, write_back, sreglist); 9945 } 9946 void Vstm(Register rn, WriteBack write_back, SRegisterList sreglist) { 9947 Vstm(al, kDataTypeValueNone, rn, write_back, sreglist); 9948 } 9949 9950 void Vstmdb(Condition cond, 9951 DataType dt, 9952 Register rn, 9953 WriteBack write_back, 9954 DRegisterList dreglist) { 9955 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9956 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 9957 VIXL_ASSERT(allow_macro_instructions_); 9958 VIXL_ASSERT(OutsideITBlock()); 9959 MacroEmissionCheckScope guard(this); 9960 ITScope it_scope(this, &cond); 9961 vstmdb(cond, dt, rn, write_back, dreglist); 9962 } 9963 void Vstmdb(DataType dt, 9964 Register rn, 9965 WriteBack write_back, 9966 DRegisterList dreglist) { 9967 Vstmdb(al, dt, rn, write_back, dreglist); 9968 } 9969 void Vstmdb(Condition cond, 9970 Register rn, 9971 WriteBack write_back, 9972 DRegisterList dreglist) { 9973 Vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 9974 } 9975 void Vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 9976 Vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 9977 } 9978 9979 void Vstmdb(Condition cond, 9980 DataType dt, 9981 Register rn, 9982 WriteBack write_back, 9983 SRegisterList sreglist) { 9984 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9985 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 9986 VIXL_ASSERT(allow_macro_instructions_); 9987 VIXL_ASSERT(OutsideITBlock()); 9988 MacroEmissionCheckScope guard(this); 9989 ITScope it_scope(this, &cond); 9990 vstmdb(cond, dt, rn, write_back, sreglist); 9991 } 9992 void Vstmdb(DataType dt, 9993 Register rn, 9994 WriteBack write_back, 9995 SRegisterList sreglist) { 9996 Vstmdb(al, dt, rn, write_back, sreglist); 9997 } 9998 void Vstmdb(Condition cond, 9999 Register rn, 10000 WriteBack write_back, 10001 SRegisterList sreglist) { 10002 Vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 10003 } 10004 void Vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 10005 Vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 10006 } 10007 10008 void Vstmia(Condition cond, 10009 DataType dt, 10010 Register rn, 10011 WriteBack write_back, 10012 DRegisterList dreglist) { 10013 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10014 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 10015 VIXL_ASSERT(allow_macro_instructions_); 10016 VIXL_ASSERT(OutsideITBlock()); 10017 MacroEmissionCheckScope guard(this); 10018 ITScope it_scope(this, &cond); 10019 vstmia(cond, dt, rn, write_back, dreglist); 10020 } 10021 void Vstmia(DataType dt, 10022 Register rn, 10023 WriteBack write_back, 10024 DRegisterList dreglist) { 10025 Vstmia(al, dt, rn, write_back, dreglist); 10026 } 10027 void Vstmia(Condition cond, 10028 Register rn, 10029 WriteBack write_back, 10030 DRegisterList dreglist) { 10031 Vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 10032 } 10033 void Vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 10034 Vstmia(al, kDataTypeValueNone, rn, write_back, dreglist); 10035 } 10036 10037 void Vstmia(Condition cond, 10038 DataType dt, 10039 Register rn, 10040 WriteBack write_back, 10041 SRegisterList sreglist) { 10042 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10043 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 10044 VIXL_ASSERT(allow_macro_instructions_); 10045 VIXL_ASSERT(OutsideITBlock()); 10046 MacroEmissionCheckScope guard(this); 10047 ITScope it_scope(this, &cond); 10048 vstmia(cond, dt, rn, write_back, sreglist); 10049 } 10050 void Vstmia(DataType dt, 10051 Register rn, 10052 WriteBack write_back, 10053 SRegisterList sreglist) { 10054 Vstmia(al, dt, rn, write_back, sreglist); 10055 } 10056 void Vstmia(Condition cond, 10057 Register rn, 10058 WriteBack write_back, 10059 SRegisterList sreglist) { 10060 Vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 10061 } 10062 void Vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 10063 Vstmia(al, kDataTypeValueNone, rn, write_back, sreglist); 10064 } 10065 10066 void Vstr(Condition cond, 10067 DataType dt, 10068 DRegister rd, 10069 const MemOperand& operand) { 10070 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10071 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 10072 VIXL_ASSERT(allow_macro_instructions_); 10073 VIXL_ASSERT(OutsideITBlock()); 10074 MacroEmissionCheckScope guard(this); 10075 ITScope it_scope(this, &cond); 10076 vstr(cond, dt, rd, operand); 10077 } 10078 void Vstr(DataType dt, DRegister rd, const MemOperand& operand) { 10079 Vstr(al, dt, rd, operand); 10080 } 10081 void Vstr(Condition cond, DRegister rd, const MemOperand& operand) { 10082 Vstr(cond, Untyped64, rd, operand); 10083 } 10084 void Vstr(DRegister rd, const MemOperand& operand) { 10085 Vstr(al, Untyped64, rd, operand); 10086 } 10087 10088 void Vstr(Condition cond, 10089 DataType dt, 10090 SRegister rd, 10091 const MemOperand& operand) { 10092 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10093 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 10094 VIXL_ASSERT(allow_macro_instructions_); 10095 VIXL_ASSERT(OutsideITBlock()); 10096 MacroEmissionCheckScope guard(this); 10097 ITScope it_scope(this, &cond); 10098 vstr(cond, dt, rd, operand); 10099 } 10100 void Vstr(DataType dt, SRegister rd, const MemOperand& operand) { 10101 Vstr(al, dt, rd, operand); 10102 } 10103 void Vstr(Condition cond, SRegister rd, const MemOperand& operand) { 10104 Vstr(cond, Untyped32, rd, operand); 10105 } 10106 void Vstr(SRegister rd, const MemOperand& operand) { 10107 Vstr(al, Untyped32, rd, operand); 10108 } 10109 10110 void Vsub( 10111 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10112 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10113 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10114 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10115 VIXL_ASSERT(allow_macro_instructions_); 10116 VIXL_ASSERT(OutsideITBlock()); 10117 MacroEmissionCheckScope guard(this); 10118 ITScope it_scope(this, &cond); 10119 vsub(cond, dt, rd, rn, rm); 10120 } 10121 void Vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10122 Vsub(al, dt, rd, rn, rm); 10123 } 10124 10125 void Vsub( 10126 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10127 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10128 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10129 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10130 VIXL_ASSERT(allow_macro_instructions_); 10131 VIXL_ASSERT(OutsideITBlock()); 10132 MacroEmissionCheckScope guard(this); 10133 ITScope it_scope(this, &cond); 10134 vsub(cond, dt, rd, rn, rm); 10135 } 10136 void Vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10137 Vsub(al, dt, rd, rn, rm); 10138 } 10139 10140 void Vsub( 10141 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 10142 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10143 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10144 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10145 VIXL_ASSERT(allow_macro_instructions_); 10146 VIXL_ASSERT(OutsideITBlock()); 10147 MacroEmissionCheckScope guard(this); 10148 ITScope it_scope(this, &cond); 10149 vsub(cond, dt, rd, rn, rm); 10150 } 10151 void Vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 10152 Vsub(al, dt, rd, rn, rm); 10153 } 10154 10155 void Vsubhn( 10156 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 10157 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10158 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10159 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10160 VIXL_ASSERT(allow_macro_instructions_); 10161 VIXL_ASSERT(OutsideITBlock()); 10162 MacroEmissionCheckScope guard(this); 10163 ITScope it_scope(this, &cond); 10164 vsubhn(cond, dt, rd, rn, rm); 10165 } 10166 void Vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 10167 Vsubhn(al, dt, rd, rn, rm); 10168 } 10169 10170 void Vsubl( 10171 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 10172 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10173 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10174 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10175 VIXL_ASSERT(allow_macro_instructions_); 10176 VIXL_ASSERT(OutsideITBlock()); 10177 MacroEmissionCheckScope guard(this); 10178 ITScope it_scope(this, &cond); 10179 vsubl(cond, dt, rd, rn, rm); 10180 } 10181 void Vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 10182 Vsubl(al, dt, rd, rn, rm); 10183 } 10184 10185 void Vsubw( 10186 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { 10187 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10189 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10190 VIXL_ASSERT(allow_macro_instructions_); 10191 VIXL_ASSERT(OutsideITBlock()); 10192 MacroEmissionCheckScope guard(this); 10193 ITScope it_scope(this, &cond); 10194 vsubw(cond, dt, rd, rn, rm); 10195 } 10196 void Vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 10197 Vsubw(al, dt, rd, rn, rm); 10198 } 10199 10200 void Vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10201 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10202 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10203 VIXL_ASSERT(allow_macro_instructions_); 10204 VIXL_ASSERT(OutsideITBlock()); 10205 MacroEmissionCheckScope guard(this); 10206 ITScope it_scope(this, &cond); 10207 vswp(cond, dt, rd, rm); 10208 } 10209 void Vswp(DataType dt, DRegister rd, DRegister rm) { Vswp(al, dt, rd, rm); } 10210 void Vswp(Condition cond, DRegister rd, DRegister rm) { 10211 Vswp(cond, kDataTypeValueNone, rd, rm); 10212 } 10213 void Vswp(DRegister rd, DRegister rm) { 10214 Vswp(al, kDataTypeValueNone, rd, rm); 10215 } 10216 10217 void Vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10218 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10219 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10220 VIXL_ASSERT(allow_macro_instructions_); 10221 VIXL_ASSERT(OutsideITBlock()); 10222 MacroEmissionCheckScope guard(this); 10223 ITScope it_scope(this, &cond); 10224 vswp(cond, dt, rd, rm); 10225 } 10226 void Vswp(DataType dt, QRegister rd, QRegister rm) { Vswp(al, dt, rd, rm); } 10227 void Vswp(Condition cond, QRegister rd, QRegister rm) { 10228 Vswp(cond, kDataTypeValueNone, rd, rm); 10229 } 10230 void Vswp(QRegister rd, QRegister rm) { 10231 Vswp(al, kDataTypeValueNone, rd, rm); 10232 } 10233 10234 void Vtbl(Condition cond, 10235 DataType dt, 10236 DRegister rd, 10237 const NeonRegisterList& nreglist, 10238 DRegister rm) { 10239 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10240 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 10241 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10242 VIXL_ASSERT(allow_macro_instructions_); 10243 VIXL_ASSERT(OutsideITBlock()); 10244 MacroEmissionCheckScope guard(this); 10245 ITScope it_scope(this, &cond); 10246 vtbl(cond, dt, rd, nreglist, rm); 10247 } 10248 void Vtbl(DataType dt, 10249 DRegister rd, 10250 const NeonRegisterList& nreglist, 10251 DRegister rm) { 10252 Vtbl(al, dt, rd, nreglist, rm); 10253 } 10254 10255 void Vtbx(Condition cond, 10256 DataType dt, 10257 DRegister rd, 10258 const NeonRegisterList& nreglist, 10259 DRegister rm) { 10260 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10261 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 10262 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10263 VIXL_ASSERT(allow_macro_instructions_); 10264 VIXL_ASSERT(OutsideITBlock()); 10265 MacroEmissionCheckScope guard(this); 10266 ITScope it_scope(this, &cond); 10267 vtbx(cond, dt, rd, nreglist, rm); 10268 } 10269 void Vtbx(DataType dt, 10270 DRegister rd, 10271 const NeonRegisterList& nreglist, 10272 DRegister rm) { 10273 Vtbx(al, dt, rd, nreglist, rm); 10274 } 10275 10276 void Vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10277 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10278 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10279 VIXL_ASSERT(allow_macro_instructions_); 10280 VIXL_ASSERT(OutsideITBlock()); 10281 MacroEmissionCheckScope guard(this); 10282 ITScope it_scope(this, &cond); 10283 vtrn(cond, dt, rd, rm); 10284 } 10285 void Vtrn(DataType dt, DRegister rd, DRegister rm) { Vtrn(al, dt, rd, rm); } 10286 10287 void Vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10288 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10289 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10290 VIXL_ASSERT(allow_macro_instructions_); 10291 VIXL_ASSERT(OutsideITBlock()); 10292 MacroEmissionCheckScope guard(this); 10293 ITScope it_scope(this, &cond); 10294 vtrn(cond, dt, rd, rm); 10295 } 10296 void Vtrn(DataType dt, QRegister rd, QRegister rm) { Vtrn(al, dt, rd, rm); } 10297 10298 void Vtst( 10299 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10300 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10301 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10302 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10303 VIXL_ASSERT(allow_macro_instructions_); 10304 VIXL_ASSERT(OutsideITBlock()); 10305 MacroEmissionCheckScope guard(this); 10306 ITScope it_scope(this, &cond); 10307 vtst(cond, dt, rd, rn, rm); 10308 } 10309 void Vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10310 Vtst(al, dt, rd, rn, rm); 10311 } 10312 10313 void Vtst( 10314 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10315 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10316 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10317 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10318 VIXL_ASSERT(allow_macro_instructions_); 10319 VIXL_ASSERT(OutsideITBlock()); 10320 MacroEmissionCheckScope guard(this); 10321 ITScope it_scope(this, &cond); 10322 vtst(cond, dt, rd, rn, rm); 10323 } 10324 void Vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10325 Vtst(al, dt, rd, rn, rm); 10326 } 10327 10328 void Vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10330 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10331 VIXL_ASSERT(allow_macro_instructions_); 10332 VIXL_ASSERT(OutsideITBlock()); 10333 MacroEmissionCheckScope guard(this); 10334 ITScope it_scope(this, &cond); 10335 vuzp(cond, dt, rd, rm); 10336 } 10337 void Vuzp(DataType dt, DRegister rd, DRegister rm) { Vuzp(al, dt, rd, rm); } 10338 10339 void Vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10340 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10341 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10342 VIXL_ASSERT(allow_macro_instructions_); 10343 VIXL_ASSERT(OutsideITBlock()); 10344 MacroEmissionCheckScope guard(this); 10345 ITScope it_scope(this, &cond); 10346 vuzp(cond, dt, rd, rm); 10347 } 10348 void Vuzp(DataType dt, QRegister rd, QRegister rm) { Vuzp(al, dt, rd, rm); } 10349 10350 void Vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10351 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10352 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10353 VIXL_ASSERT(allow_macro_instructions_); 10354 VIXL_ASSERT(OutsideITBlock()); 10355 MacroEmissionCheckScope guard(this); 10356 ITScope it_scope(this, &cond); 10357 vzip(cond, dt, rd, rm); 10358 } 10359 void Vzip(DataType dt, DRegister rd, DRegister rm) { Vzip(al, dt, rd, rm); } 10360 10361 void Vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10362 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10363 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10364 VIXL_ASSERT(allow_macro_instructions_); 10365 VIXL_ASSERT(OutsideITBlock()); 10366 MacroEmissionCheckScope guard(this); 10367 ITScope it_scope(this, &cond); 10368 vzip(cond, dt, rd, rm); 10369 } 10370 void Vzip(DataType dt, QRegister rd, QRegister rm) { Vzip(al, dt, rd, rm); } 10371 10372 void Yield(Condition cond) { 10373 VIXL_ASSERT(allow_macro_instructions_); 10374 VIXL_ASSERT(OutsideITBlock()); 10375 MacroEmissionCheckScope guard(this); 10376 ITScope it_scope(this, &cond); 10377 yield(cond); 10378 } 10379 void Yield() { Yield(al); } 10380 void Vabs(Condition cond, VRegister rd, VRegister rm) { 10381 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10382 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10383 if (rd.IsS()) { 10384 Vabs(cond, F32, rd.S(), rm.S()); 10385 } else { 10386 Vabs(cond, F64, rd.D(), rm.D()); 10387 } 10388 } 10389 void Vabs(VRegister rd, VRegister rm) { Vabs(al, rd, rm); } 10390 void Vadd(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10391 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10392 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10393 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10394 if (rd.IsS()) { 10395 Vadd(cond, F32, rd.S(), rn.S(), rm.S()); 10396 } else { 10397 Vadd(cond, F64, rd.D(), rn.D(), rm.D()); 10398 } 10399 } 10400 void Vadd(VRegister rd, VRegister rn, VRegister rm) { Vadd(al, rd, rn, rm); } 10401 void Vcmp(Condition cond, VRegister rd, VRegister rm) { 10402 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10403 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10404 if (rd.IsS()) { 10405 Vcmp(cond, F32, rd.S(), rm.S()); 10406 } else { 10407 Vcmp(cond, F64, rd.D(), rm.D()); 10408 } 10409 } 10410 void Vcmp(VRegister rd, VRegister rm) { Vcmp(al, rd, rm); } 10411 void Vcmpe(Condition cond, VRegister rd, VRegister rm) { 10412 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10413 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10414 if (rd.IsS()) { 10415 Vcmpe(cond, F32, rd.S(), rm.S()); 10416 } else { 10417 Vcmpe(cond, F64, rd.D(), rm.D()); 10418 } 10419 } 10420 void Vcmpe(VRegister rd, VRegister rm) { Vcmpe(al, rd, rm); } 10421 void Vdiv(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10422 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10423 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10424 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10425 if (rd.IsS()) { 10426 Vdiv(cond, F32, rd.S(), rn.S(), rm.S()); 10427 } else { 10428 Vdiv(cond, F64, rd.D(), rn.D(), rm.D()); 10429 } 10430 } 10431 void Vdiv(VRegister rd, VRegister rn, VRegister rm) { Vdiv(al, rd, rn, rm); } 10432 void Vfma(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10433 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10434 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10435 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10436 if (rd.IsS()) { 10437 Vfma(cond, F32, rd.S(), rn.S(), rm.S()); 10438 } else { 10439 Vfma(cond, F64, rd.D(), rn.D(), rm.D()); 10440 } 10441 } 10442 void Vfma(VRegister rd, VRegister rn, VRegister rm) { Vfma(al, rd, rn, rm); } 10443 void Vfms(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10444 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10445 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10446 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10447 if (rd.IsS()) { 10448 Vfms(cond, F32, rd.S(), rn.S(), rm.S()); 10449 } else { 10450 Vfms(cond, F64, rd.D(), rn.D(), rm.D()); 10451 } 10452 } 10453 void Vfms(VRegister rd, VRegister rn, VRegister rm) { Vfms(al, rd, rn, rm); } 10454 void Vfnma(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10455 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10456 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10457 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10458 if (rd.IsS()) { 10459 Vfnma(cond, F32, rd.S(), rn.S(), rm.S()); 10460 } else { 10461 Vfnma(cond, F64, rd.D(), rn.D(), rm.D()); 10462 } 10463 } 10464 void Vfnma(VRegister rd, VRegister rn, VRegister rm) { 10465 Vfnma(al, rd, rn, rm); 10466 } 10467 void Vfnms(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10468 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10469 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10470 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10471 if (rd.IsS()) { 10472 Vfnms(cond, F32, rd.S(), rn.S(), rm.S()); 10473 } else { 10474 Vfnms(cond, F64, rd.D(), rn.D(), rm.D()); 10475 } 10476 } 10477 void Vfnms(VRegister rd, VRegister rn, VRegister rm) { 10478 Vfnms(al, rd, rn, rm); 10479 } 10480 void Vmaxnm(VRegister rd, VRegister rn, VRegister rm) { 10481 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10482 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10483 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10484 if (rd.IsS()) { 10485 Vmaxnm(F32, rd.S(), rn.S(), rm.S()); 10486 } else { 10487 Vmaxnm(F64, rd.D(), rn.D(), rm.D()); 10488 } 10489 } 10490 void Vminnm(VRegister rd, VRegister rn, VRegister rm) { 10491 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10492 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10493 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10494 if (rd.IsS()) { 10495 Vminnm(F32, rd.S(), rn.S(), rm.S()); 10496 } else { 10497 Vminnm(F64, rd.D(), rn.D(), rm.D()); 10498 } 10499 } 10500 void Vmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10501 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10502 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10503 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10504 if (rd.IsS()) { 10505 Vmla(cond, F32, rd.S(), rn.S(), rm.S()); 10506 } else { 10507 Vmla(cond, F64, rd.D(), rn.D(), rm.D()); 10508 } 10509 } 10510 void Vmla(VRegister rd, VRegister rn, VRegister rm) { Vmla(al, rd, rn, rm); } 10511 void Vmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10512 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10513 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10514 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10515 if (rd.IsS()) { 10516 Vmls(cond, F32, rd.S(), rn.S(), rm.S()); 10517 } else { 10518 Vmls(cond, F64, rd.D(), rn.D(), rm.D()); 10519 } 10520 } 10521 void Vmls(VRegister rd, VRegister rn, VRegister rm) { Vmls(al, rd, rn, rm); } 10522 void Vmov(Condition cond, VRegister rd, VRegister rm) { 10523 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10524 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10525 if (rd.IsS()) { 10526 Vmov(cond, F32, rd.S(), rm.S()); 10527 } else { 10528 Vmov(cond, F64, rd.D(), rm.D()); 10529 } 10530 } 10531 void Vmov(VRegister rd, VRegister rm) { Vmov(al, rd, rm); } 10532 void Vmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10533 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10534 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10535 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10536 if (rd.IsS()) { 10537 Vmul(cond, F32, rd.S(), rn.S(), rm.S()); 10538 } else { 10539 Vmul(cond, F64, rd.D(), rn.D(), rm.D()); 10540 } 10541 } 10542 void Vmul(VRegister rd, VRegister rn, VRegister rm) { Vmul(al, rd, rn, rm); } 10543 void Vneg(Condition cond, VRegister rd, VRegister rm) { 10544 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10545 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10546 if (rd.IsS()) { 10547 Vneg(cond, F32, rd.S(), rm.S()); 10548 } else { 10549 Vneg(cond, F64, rd.D(), rm.D()); 10550 } 10551 } 10552 void Vneg(VRegister rd, VRegister rm) { Vneg(al, rd, rm); } 10553 void Vnmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10554 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10555 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10556 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10557 if (rd.IsS()) { 10558 Vnmla(cond, F32, rd.S(), rn.S(), rm.S()); 10559 } else { 10560 Vnmla(cond, F64, rd.D(), rn.D(), rm.D()); 10561 } 10562 } 10563 void Vnmla(VRegister rd, VRegister rn, VRegister rm) { 10564 Vnmla(al, rd, rn, rm); 10565 } 10566 void Vnmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10567 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10568 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10569 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10570 if (rd.IsS()) { 10571 Vnmls(cond, F32, rd.S(), rn.S(), rm.S()); 10572 } else { 10573 Vnmls(cond, F64, rd.D(), rn.D(), rm.D()); 10574 } 10575 } 10576 void Vnmls(VRegister rd, VRegister rn, VRegister rm) { 10577 Vnmls(al, rd, rn, rm); 10578 } 10579 void Vnmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10580 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10581 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10582 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10583 if (rd.IsS()) { 10584 Vnmul(cond, F32, rd.S(), rn.S(), rm.S()); 10585 } else { 10586 Vnmul(cond, F64, rd.D(), rn.D(), rm.D()); 10587 } 10588 } 10589 void Vnmul(VRegister rd, VRegister rn, VRegister rm) { 10590 Vnmul(al, rd, rn, rm); 10591 } 10592 void Vseleq(VRegister rd, VRegister rn, VRegister rm) { 10593 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10594 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10595 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10596 if (rd.IsS()) { 10597 Vseleq(F32, rd.S(), rn.S(), rm.S()); 10598 } else { 10599 Vseleq(F64, rd.D(), rn.D(), rm.D()); 10600 } 10601 } 10602 void Vselge(VRegister rd, VRegister rn, VRegister rm) { 10603 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10604 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10605 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10606 if (rd.IsS()) { 10607 Vselge(F32, rd.S(), rn.S(), rm.S()); 10608 } else { 10609 Vselge(F64, rd.D(), rn.D(), rm.D()); 10610 } 10611 } 10612 void Vselgt(VRegister rd, VRegister rn, VRegister rm) { 10613 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10614 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10615 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10616 if (rd.IsS()) { 10617 Vselgt(F32, rd.S(), rn.S(), rm.S()); 10618 } else { 10619 Vselgt(F64, rd.D(), rn.D(), rm.D()); 10620 } 10621 } 10622 void Vselvs(VRegister rd, VRegister rn, VRegister rm) { 10623 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10624 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10625 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10626 if (rd.IsS()) { 10627 Vselvs(F32, rd.S(), rn.S(), rm.S()); 10628 } else { 10629 Vselvs(F64, rd.D(), rn.D(), rm.D()); 10630 } 10631 } 10632 void Vsqrt(Condition cond, VRegister rd, VRegister rm) { 10633 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10634 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10635 if (rd.IsS()) { 10636 Vsqrt(cond, F32, rd.S(), rm.S()); 10637 } else { 10638 Vsqrt(cond, F64, rd.D(), rm.D()); 10639 } 10640 } 10641 void Vsqrt(VRegister rd, VRegister rm) { Vsqrt(al, rd, rm); } 10642 void Vsub(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10643 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10644 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10645 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10646 if (rd.IsS()) { 10647 Vsub(cond, F32, rd.S(), rn.S(), rm.S()); 10648 } else { 10649 Vsub(cond, F64, rd.D(), rn.D(), rm.D()); 10650 } 10651 } 10652 void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); } 10653 // End of generated code. 10654 10655 virtual bool AllowUnpredictable() VIXL_OVERRIDE { 10656 VIXL_ABORT_WITH_MSG("Unpredictable instruction.\n"); 10657 return false; 10658 } 10659 virtual bool AllowStronglyDiscouraged() VIXL_OVERRIDE { 10660 VIXL_ABORT_WITH_MSG( 10661 "ARM strongly recommends to not use this instruction.\n"); 10662 return false; 10663 } 10664 10665 private: 10666 RegisterList available_; 10667 VRegisterList available_vfp_; 10668 MacroAssemblerContext context_; 10669 Label::Offset checkpoint_; 10670 LiteralPoolManager literal_pool_manager_; 10671 VeneerPoolManager veneer_pool_manager_; 10672 bool generate_simulator_code_; 10673 bool allow_macro_instructions_; 10674}; 10675 10676// This scope utility allows scratch registers to be managed safely. The 10677// MacroAssembler's GetScratchRegisterList() is used as a pool of scratch 10678// registers. These registers can be allocated on demand, and will be returned 10679// at the end of the scope. 10680// 10681// When the scope ends, the MacroAssembler's lists will be restored to their 10682// original state, even if the lists were modified by some other means. 10683class UseScratchRegisterScope { 10684 public: 10685 // This constructor implicitly calls the `Open` function to initialise the 10686 // scope, so it is ready to use immediately after it has been constructed. 10687 explicit UseScratchRegisterScope(MacroAssembler* masm) 10688 : available_(NULL), 10689 available_vfp_(NULL), 10690 old_available_(0), 10691 old_available_vfp_(0) { 10692 Open(masm); 10693 } 10694 // This constructor allows deferred and optional initialisation of the scope. 10695 // The user is required to explicitly call the `Open` function before using 10696 // the scope. 10697 UseScratchRegisterScope() 10698 : available_(NULL), 10699 available_vfp_(NULL), 10700 old_available_(0), 10701 old_available_vfp_(0) {} 10702 10703 // This function performs the actual initialisation work. 10704 void Open(MacroAssembler* masm); 10705 10706 // The destructor always implicitly calls the `Close` function. 10707 ~UseScratchRegisterScope() { Close(); } 10708 10709 // This function performs the cleaning-up work. It must succeed even if the 10710 // scope has not been opened. It is safe to call multiple times. 10711 void Close(); 10712 10713 bool IsAvailable(const Register& reg) const; 10714 bool IsAvailable(const VRegister& reg) const; 10715 10716 // Take a register from the temp list. It will be returned automatically when 10717 // the scope ends. 10718 Register Acquire(); 10719 VRegister AcquireV(unsigned size_in_bits); 10720 QRegister AcquireQ(); 10721 DRegister AcquireD(); 10722 SRegister AcquireS(); 10723 10724 // Explicitly release an acquired (or excluded) register, putting it back in 10725 // the temp list. 10726 void Release(const Register& reg); 10727 void Release(const VRegister& reg); 10728 10729 // Make the specified registers available as scratch registers for the 10730 // duration of this scope. 10731 void Include(const RegisterList& list); 10732 void Include(const Register& reg1, 10733 const Register& reg2 = NoReg, 10734 const Register& reg3 = NoReg, 10735 const Register& reg4 = NoReg) { 10736 Include(RegisterList(reg1, reg2, reg3, reg4)); 10737 } 10738 void Include(const VRegisterList& list); 10739 void Include(const VRegister& reg1, 10740 const VRegister& reg2 = NoVReg, 10741 const VRegister& reg3 = NoVReg, 10742 const VRegister& reg4 = NoVReg) { 10743 Include(VRegisterList(reg1, reg2, reg3, reg4)); 10744 } 10745 10746 // Make sure that the specified registers are not available in this scope. 10747 // This can be used to prevent helper functions from using sensitive 10748 // registers, for example. 10749 void Exclude(const RegisterList& list); 10750 void Exclude(const Register& reg1, 10751 const Register& reg2 = NoReg, 10752 const Register& reg3 = NoReg, 10753 const Register& reg4 = NoReg) { 10754 Exclude(RegisterList(reg1, reg2, reg3, reg4)); 10755 } 10756 void Exclude(const VRegisterList& list); 10757 void Exclude(const VRegister& reg1, 10758 const VRegister& reg2 = NoVReg, 10759 const VRegister& reg3 = NoVReg, 10760 const VRegister& reg4 = NoVReg) { 10761 Exclude(VRegisterList(reg1, reg2, reg3, reg4)); 10762 } 10763 10764 // A convenience helper to exclude any registers used by the operand. 10765 void Exclude(const Operand& operand); 10766 10767 // Prevent any scratch registers from being used in this scope. 10768 void ExcludeAll(); 10769 10770 private: 10771 // Available scratch registers. 10772 RegisterList* available_; // kRRegister 10773 VRegisterList* available_vfp_; // kVRegister 10774 10775 // The state of the available lists at the start of this scope. 10776 uint32_t old_available_; // kRRegister 10777 uint64_t old_available_vfp_; // kVRegister 10778 10779 VIXL_DEBUG_NO_RETURN UseScratchRegisterScope(const UseScratchRegisterScope&) { 10780 VIXL_UNREACHABLE(); 10781 } 10782 VIXL_DEBUG_NO_RETURN void operator=(const UseScratchRegisterScope&) { 10783 VIXL_UNREACHABLE(); 10784 } 10785}; 10786 10787class JumpTableBase { 10788 protected: 10789 JumpTableBase(int len, int offset_size) 10790 : table_location_(Label::kMaxOffset), 10791 branch_location_(Label::kMaxOffset), 10792 length_(len), 10793 offset_shift_(WhichPowerOf2(offset_size)), 10794 presence_(length_) { 10795 VIXL_ASSERT((length_ >= 0) && (offset_size <= 4)); 10796 } 10797 virtual ~JumpTableBase() {} 10798 10799 public: 10800 int GetTableSizeInBytes() const { return length_ * (1 << offset_shift_); } 10801 int GetOffsetShift() const { return offset_shift_; } 10802 int GetLength() const { return length_; } 10803 Label* GetDefaultLabel() { return &default_; } 10804 Label* GetEndLabel() { return &end_; } 10805 void SetBranchLocation(uint32_t branch_location) { 10806 branch_location_ = branch_location; 10807 } 10808 uint32_t GetBranchLocation() const { return branch_location_; } 10809 void BindTable(uint32_t location) { table_location_ = location; } 10810 virtual void Link(MacroAssembler* masm, 10811 int case_index, 10812 uint32_t location) = 0; 10813 10814 uint32_t GetLocationForCase(int i) { 10815 VIXL_ASSERT((i >= 0) && (i < length_)); 10816 return table_location_ + (i * (1 << offset_shift_)); 10817 } 10818 void SetPresenceBitForCase(int i) { 10819 VIXL_ASSERT((i >= 0) && (i < length_)); 10820 presence_.Set(i); 10821 } 10822 10823 void Finalize(MacroAssembler* masm) { 10824 if (!default_.IsBound()) { 10825 masm->Bind(&default_); 10826 } 10827 masm->Bind(&end_); 10828 10829 presence_.ForEachBitNotSet(LinkIt(this, masm, default_.GetLocation())); 10830 } 10831 10832 private: 10833 uint32_t table_location_; 10834 uint32_t branch_location_; 10835 const int length_; 10836 const int offset_shift_; 10837 BitField presence_; 10838 Label default_; 10839 Label end_; 10840 struct LinkIt { 10841 JumpTableBase* table_; 10842 MacroAssembler* const masm_; 10843 const uint32_t location_; 10844 LinkIt(JumpTableBase* table, MacroAssembler* const masm, uint32_t location) 10845 : table_(table), masm_(masm), location_(location) {} 10846 bool execute(int id) const { 10847 VIXL_ASSERT(id < table_->GetLength()); 10848 table_->Link(masm_, static_cast<int>(id), location_); 10849 return true; 10850 } 10851 }; 10852}; 10853 10854// JumpTable<T>(len): Helper to describe a jump table 10855// len here describes the number of possible case. Values in [0, n[ can have a 10856// jump offset. Any other value will assert. 10857template <typename T> 10858class JumpTable : public JumpTableBase { 10859 protected: 10860 explicit JumpTable(int length) : JumpTableBase(length, sizeof(T)) {} 10861 10862 public: 10863 virtual void Link(MacroAssembler* masm, 10864 int case_index, 10865 uint32_t location) VIXL_OVERRIDE { 10866 uint32_t position_in_table = GetLocationForCase(case_index); 10867 uint32_t from = GetBranchLocation(); 10868 int offset = location - from; 10869 T* case_offset = masm->GetBuffer()->GetOffsetAddress<T*>(position_in_table); 10870 if (masm->IsUsingT32()) { 10871 *case_offset = offset >> 1; 10872 } else { 10873 *case_offset = offset >> 2; 10874 } 10875 } 10876}; 10877 10878class JumpTable8bitOffset : public JumpTable<uint8_t> { 10879 public: 10880 explicit JumpTable8bitOffset(int length) : JumpTable<uint8_t>(length) {} 10881}; 10882 10883class JumpTable16bitOffset : public JumpTable<uint16_t> { 10884 public: 10885 explicit JumpTable16bitOffset(int length) : JumpTable<uint16_t>(length) {} 10886}; 10887 10888class JumpTable32bitOffset : public JumpTable<uint32_t> { 10889 public: 10890 explicit JumpTable32bitOffset(int length) : JumpTable<uint32_t>(length) {} 10891}; 10892 10893} // namespace aarch32 10894} // namespace vixl 10895 10896#endif // VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 10897