macro-assembler-aarch32.h revision dcffac4d0a5a586d3c14971e33bd28fc848bc148 
1// Copyright 2015, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright
10//     notice, this list of conditions and the following disclaimer in the
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14//     without specific prior written permission.
15//
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20// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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27
28#ifndef VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_
29#define VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_
30
31#include "utils-vixl.h"
32#include "aarch32/instructions-aarch32.h"
33#include "aarch32/assembler-aarch32.h"
34#include "aarch32/operand-aarch32.h"
35
36namespace vixl {
37namespace aarch32 {
38
39class JumpTableBase;
40
41enum FlagsUpdate { LeaveFlags = 0, SetFlags = 1, DontCare = 2 };
42
43// LiteralPool class, defined as a container for literals
44class LiteralPool {
45 public:
46  typedef std::list<RawLiteral*>::iterator RawLiteralListIterator;
47
48 public:
49  LiteralPool() : size_(0) {}
50  ~LiteralPool() {
51    VIXL_ASSERT(literals_.empty() && (size_ == 0));
52    for (RawLiteralListIterator literal_it = keep_until_delete_.begin();
53         literal_it != keep_until_delete_.end();
54         literal_it++) {
55      delete *literal_it;
56    }
57    keep_until_delete_.clear();
58  }
59
60  unsigned GetSize() const { return size_; }
61
62  // Add a literal to the literal container.
63  void AddLiteral(RawLiteral* literal) {
64    if (literal->GetPositionInPool() == Label::kMaxOffset) {
65      uint32_t position = GetSize();
66      literal->SetPositionInPool(position);
67      literals_.push_back(literal);
68      size_ += literal->GetAlignedSize();
69    }
70  }
71
72  // First literal to be emitted.
73  RawLiteralListIterator GetFirst() { return literals_.begin(); }
74
75  // Mark the end of the literal container.
76  RawLiteralListIterator GetEnd() { return literals_.end(); }
77
78  // Remove all the literals from the container.
79  // If the literal's memory management has been delegated to the container
80  // it will be delete'd.
81  void Clear() {
82    for (RawLiteralListIterator literal_it = GetFirst(); literal_it != GetEnd();
83         literal_it++) {
84      RawLiteral* literal = *literal_it;
85      switch (literal->GetDeletionPolicy()) {
86        case RawLiteral::kDeletedOnPlacementByPool:
87          delete literal;
88          break;
89        case RawLiteral::kDeletedOnPoolDestruction:
90          keep_until_delete_.push_back(literal);
91          break;
92        case RawLiteral::kManuallyDeleted:
93          break;
94      }
95    }
96    literals_.clear();
97    size_ = 0;
98  }
99
100 private:
101  // Size (in bytes and including alignments) of the literal pool.
102  unsigned size_;
103
104  // Literal container.
105  std::list<RawLiteral*> literals_;
106  // Already bound Literal container the app requested this pool to keep.
107  std::list<RawLiteral*> keep_until_delete_;
108};
109
110// Macro assembler for aarch32 instruction set.
111class MacroAssembler : public Assembler {
112 public:
113  enum EmitOption { kBranchRequired, kNoBranchRequired };
114
115 private:
116  class AllowAssemblerEmissionScope {
117    MacroAssembler* masm_;
118
119   public:
120    AllowAssemblerEmissionScope(MacroAssembler* masm, uint32_t size)
121        : masm_(masm) {
122      VIXL_ASSERT(!masm->AllowAssembler());
123      masm->EnsureEmitFor(size);
124#ifdef VIXL_DEBUG
125      masm->SetAllowAssembler(true);
126#else
127      USE(masm_);
128#endif
129    }
130    ~AllowAssemblerEmissionScope() {
131#ifdef VIXL_DEBUG
132      VIXL_ASSERT(masm_->AllowAssembler());
133      masm_->SetAllowAssembler(false);
134#endif
135    }
136  };
137
138  class MacroAssemblerContext {
139   public:
140    MacroAssemblerContext() : count_(0) {}
141    ~MacroAssemblerContext() {}
142    unsigned GetRecursiveCount() const { return count_; }
143    void Up() {
144      count_++;
145      VIXL_CHECK(count_ < kMaxRecursion);
146    }
147    void Down() {
148      VIXL_ASSERT((count_ > 0) && (count_ < kMaxRecursion));
149      count_--;
150    }
151
152   private:
153    unsigned count_;
154    static const uint32_t kMaxRecursion = 5;
155  };
156
157  class ContextScope {
158   public:
159    explicit ContextScope(MacroAssembler* const masm) : masm_(masm) {
160      VIXL_ASSERT(masm_->AllowMacroInstructions());
161      masm_->GetContext()->Up();
162    }
163    ~ContextScope() { masm_->GetContext()->Down(); }
164
165   private:
166    MacroAssembler* const masm_;
167  };
168
169  MacroAssemblerContext* GetContext() { return &context_; }
170
171  class ITScope {
172   public:
173    ITScope(MacroAssembler* masm, Condition* cond, bool can_use_it = false)
174        : masm_(masm), cond_(*cond), can_use_it_(can_use_it) {
175      if (!cond_.Is(al) && masm->IsUsingT32()) {
176        if (can_use_it_) {
177          // IT is not deprecated (that implies a 16 bit T32 instruction).
178          // We generate an IT instruction and a conditional instruction.
179          masm->it(cond_);
180        } else {
181          // The usage of IT is deprecated for the instruction.
182          // We generate a conditional branch and an unconditional instruction.
183          masm_->EnsureEmitFor(k16BitT32InstructionSizeInBytes +
184                               kMaxT32MacroInstructionSizeInBytes);
185          // Generate the branch.
186          masm_->b(cond_.Negate(), Narrow, &label_);
187          // Tell the macro-assembler to generate unconditional instructions.
188          *cond = al;
189        }
190      }
191#ifdef VIXL_DEBUG
192      initial_cursor_offset_ = masm->GetCursorOffset();
193#else
194      USE(initial_cursor_offset_);
195#endif
196    }
197    ~ITScope() {
198      if (!cond_.Is(al) && masm_->IsUsingT32() && !can_use_it_) {
199        VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <=
200                    kMaxT32MacroInstructionSizeInBytes);
201        masm_->bind(&label_);
202      }
203    }
204
205   private:
206    MacroAssembler* masm_;
207    Condition cond_;
208    Label label_;
209    bool can_use_it_;
210    uint32_t initial_cursor_offset_;
211  };
212
213  template <Assembler::InstructionCondDtDL asmfn>
214  class EmitLiteralCondDtDL {
215   public:
216    EmitLiteralCondDtDL(Condition cond, DataType dt, DRegister rt)
217        : cond_(cond), dt_(dt), rt_(rt) {}
218    void emit(MacroAssembler* const masm, RawLiteral* const literal) {
219      (masm->*asmfn)(cond_, dt_, rt_, literal);
220    }
221
222   private:
223    Condition cond_;
224    DataType dt_;
225    DRegister rt_;
226  };
227
228  template <Assembler::InstructionCondDtSL asmfn>
229  class EmitLiteralCondDtSL {
230   public:
231    EmitLiteralCondDtSL(Condition cond, DataType dt, SRegister rt)
232        : cond_(cond), dt_(dt), rt_(rt) {}
233    void emit(MacroAssembler* const masm, RawLiteral* const literal) {
234      (masm->*asmfn)(cond_, dt_, rt_, literal);
235    }
236
237   private:
238    Condition cond_;
239    DataType dt_;
240    SRegister rt_;
241  };
242
243  template <Assembler::InstructionCondRL asmfn>
244  class EmitLiteralCondRL {
245   public:
246    EmitLiteralCondRL(Condition cond, Register rt) : cond_(cond), rt_(rt) {}
247    void emit(MacroAssembler* const masm, RawLiteral* const literal) {
248      (masm->*asmfn)(cond_, rt_, literal);
249    }
250
251   private:
252    Condition cond_;
253    Register rt_;
254  };
255
256  template <Assembler::InstructionCondRRL asmfn>
257  class EmitLiteralCondRRL {
258   public:
259    EmitLiteralCondRRL(Condition cond, Register rt, Register rt2)
260        : cond_(cond), rt_(rt), rt2_(rt2) {}
261    void emit(MacroAssembler* const masm, RawLiteral* const literal) {
262      (masm->*asmfn)(cond_, rt_, rt2_, literal);
263    }
264
265   private:
266    Condition cond_;
267    Register rt_, rt2_;
268  };
269
270  class LiteralPoolManager {
271   public:
272    explicit LiteralPoolManager(MacroAssembler* const masm) : masm_(masm) {
273      ResetCheckpoint();
274    }
275
276    void ResetCheckpoint() { checkpoint_ = Label::kMaxOffset; }
277
278    LiteralPool* GetLiteralPool() { return &literal_pool_; }
279    Label::Offset GetCheckpoint() const {
280      // Make room for a branch over the pools.
281      return checkpoint_ - kMaxInstructionSizeInBytes;
282    }
283    size_t GetLiteralPoolSize() const { return literal_pool_.GetSize(); }
284
285    // Checks if the insertion of the literal will put the forward reference
286    // too far in the literal pool.
287    bool IsInsertTooFar(RawLiteral* literal, uint32_t from) const {
288      uint32_t checkpoint = from + literal->GetLastInsertForwardDistance();
289      checkpoint =
290          std::min(checkpoint, static_cast<uint32_t>(literal->GetCheckpoint()));
291      bool too_far = AlignDown(checkpoint, 4) < from + literal_pool_.GetSize() +
292                                                    kMaxInstructionSizeInBytes;
293      return too_far;
294    }
295
296    // Set the different checkpoints where the literal pool has to be emited.
297    void UpdateCheckpoint(RawLiteral* literal) {
298      // The literal should have been placed somewhere in the literal pool
299      VIXL_ASSERT(literal->GetPositionInPool() != Label::kMaxOffset);
300      // TODO(all): Consider AddForwardRef as a  virtual so the checkpoint is
301      //   updated when inserted. Or move checkpoint_ into Label,
302      literal->UpdateCheckpoint();
303      Label::Offset tmp =
304          literal->GetAlignedCheckpoint(4) - literal->GetPositionInPool();
305      if (checkpoint_ > tmp) {
306        checkpoint_ = tmp;
307        masm_->ComputeCheckpoint();
308      }
309    }
310
311   private:
312    MacroAssembler* const masm_;
313    LiteralPool literal_pool_;
314
315    // Max offset in the code buffer where the literal needs to be
316    // emitted. A default value of Label::kMaxOffset means that the checkpoint
317    // is invalid.
318    Label::Offset checkpoint_;
319  };
320
321  class VeneerPoolManager {
322   public:
323    explicit VeneerPoolManager(MacroAssembler* masm)
324        : masm_(masm), checkpoint_(Label::kMaxOffset) {}
325    Label::Offset GetCheckpoint() const {
326      // Make room for a branch over the pools.
327      return checkpoint_ - kMaxInstructionSizeInBytes;
328    }
329    size_t GetMaxSize() const {
330      return labels_.size() * kMaxInstructionSizeInBytes;
331    }
332    void AddLabel(Label* label) {
333      if (!label->IsInVeneerPool()) {
334        label->SetInVeneerPool();
335        labels_.push_back(label);
336      }
337      Label::ForwardReference& back = label->GetBackForwardRef();
338      back.SetIsBranch();
339      label->UpdateCheckpoint();
340      Label::Offset tmp = label->GetCheckpoint();
341      if (checkpoint_ > tmp) {
342        checkpoint_ = tmp;
343        masm_->ComputeCheckpoint();
344      }
345    }
346    void RemoveLabel(Label* label);
347    void Emit(Label::Offset target);
348
349   private:
350    MacroAssembler* masm_;
351    // List of all unbound labels which are used by a branch instruction.
352    std::list<Label*> labels_;
353    // Max offset in the code buffer where the veneer needs to be emitted.
354    // A default value of Label::kMaxOffset means that the checkpoint is
355    // invalid.
356    Label::Offset checkpoint_;
357  };
358
359  void PerformEnsureEmit(Label::Offset target, uint32_t extra_size);
360
361 protected:
362  void HandleOutOfBoundsImmediate(Condition cond, Register tmp, uint32_t imm);
363
364  // Generate the instruction and if it's not possible revert the whole thing.
365  // emit the literal pool and regenerate the instruction.
366  // Note: The instruction is generated via
367  // void T::emit(MacroAssembler* const, RawLiteral* const)
368  template <typename T>
369  void GenerateInstruction(T instr_callback, RawLiteral* const literal) {
370    int32_t cursor = GetCursorOffset();
371    uint32_t where = cursor + GetArchitectureStatePCOffset();
372    // Emit the instruction, via the assembler
373    {
374      AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
375      instr_callback.emit(this, literal);
376    }
377    if (!literal->IsManuallyPlaced()) {
378      if (IsInsertTooFar(literal, where)) {
379        // The instruction's data is too far: revert the emission
380        GetBuffer()->Rewind(cursor);
381        literal->InvalidateLastForwardReference(RawLiteral::kNoUpdateNecessary);
382        EmitLiteralPool(kBranchRequired);
383        AllowAssemblerEmissionScope allow_scope(this,
384                                                kMaxInstructionSizeInBytes);
385        instr_callback.emit(this, literal);
386      }
387      literal_pool_manager_.GetLiteralPool()->AddLiteral(literal);
388      literal_pool_manager_.UpdateCheckpoint(literal);
389    }
390  }
391
392 public:
393  explicit MacroAssembler(InstructionSet isa = A32)
394      : Assembler(isa),
395        available_(r12),
396        checkpoint_(Label::kMaxOffset),
397        literal_pool_manager_(this),
398        veneer_pool_manager_(this),
399        generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
400    SetAllowAssembler(false);
401#ifdef VIXL_DEBUG
402    SetAllowMacroInstructions(true);
403#else
404    USE(literal_pool_manager_);
405    USE(allow_macro_instructions_);
406#endif
407    ComputeCheckpoint();
408  }
409  explicit MacroAssembler(size_t size, InstructionSet isa = A32)
410      : Assembler(size, isa),
411        available_(r12),
412        checkpoint_(Label::kMaxOffset),
413        literal_pool_manager_(this),
414        veneer_pool_manager_(this),
415        generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
416    SetAllowAssembler(false);
417#ifdef VIXL_DEBUG
418    SetAllowMacroInstructions(true);
419#endif
420    ComputeCheckpoint();
421  }
422  MacroAssembler(byte* buffer, size_t size, InstructionSet isa = A32)
423      : Assembler(buffer, size, isa),
424        available_(r12),
425        checkpoint_(Label::kMaxOffset),
426        literal_pool_manager_(this),
427        veneer_pool_manager_(this),
428        generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
429    SetAllowAssembler(false);
430#ifdef VIXL_DEBUG
431    SetAllowMacroInstructions(true);
432#endif
433    ComputeCheckpoint();
434  }
435
436  bool GenerateSimulatorCode() const { return generate_simulator_code_; }
437
438#ifdef VIXL_DEBUG
439  // Tell whether any of the macro instruction can be used. When false the
440  // MacroAssembler will assert if a method which can emit a variable number
441  // of instructions is called.
442  void SetAllowMacroInstructions(bool value) {
443    allow_macro_instructions_ = value;
444  }
445  bool AllowMacroInstructions() const { return allow_macro_instructions_; }
446#endif
447
448  void FinalizeCode() {
449    EmitLiteralPool(kNoBranchRequired);
450    Assembler::FinalizeCode();
451  }
452
453  RegisterList* GetScratchRegisterList() { return &available_; }
454  VRegisterList* GetScratchVRegisterList() { return &available_vfp_; }
455
456  // State and type helpers.
457  bool IsModifiedImmediate(uint32_t imm) {
458    return (IsUsingT32() && ImmediateT32(imm).IsValid()) ||
459           ImmediateA32(imm).IsValid();
460  }
461
462  void Bind(Label* label) {
463    VIXL_ASSERT(allow_macro_instructions_);
464    bind(label);
465    if (label->IsInVeneerPool()) veneer_pool_manager_.RemoveLabel(label);
466  }
467
468  void AddBranchLabel(Label* label) {
469    if (label->IsBound()) return;
470    veneer_pool_manager_.AddLabel(label);
471  }
472
473  void Place(RawLiteral* literal) {
474    VIXL_ASSERT(allow_macro_instructions_);
475    VIXL_ASSERT(literal->IsManuallyPlaced());
476    size_t literal_size = literal->GetSize();
477    VIXL_ASSERT(IsUint32(literal_size));
478    EnsureEmitFor(static_cast<uint32_t>(literal_size));
479    place(literal);
480  }
481
482  void ComputeCheckpoint();
483
484  int32_t GetMarginBeforeVeneerEmission() const {
485    return veneer_pool_manager_.GetCheckpoint() - GetCursorOffset();
486  }
487
488  int32_t GetMarginBeforePoolEmission() const {
489    return literal_pool_manager_.GetCheckpoint() - GetCursorOffset();
490  }
491
492  bool VeneerPoolIsEmpty() const {
493    return veneer_pool_manager_.GetCheckpoint() == Label::kMaxOffset;
494  }
495
496  bool LiteralPoolIsEmpty() const { return GetLiteralPoolSize() == 0; }
497
498  void EnsureEmitFor(uint32_t size) {
499    Label::Offset target = AlignUp(GetCursorOffset() + size, 4);
500    if (target < checkpoint_) return;
501    PerformEnsureEmit(target, size);
502  }
503
504  bool IsInsertTooFar(RawLiteral* literal, uint32_t where) {
505    return literal_pool_manager_.IsInsertTooFar(literal, where);
506  }
507
508  // Emit the literal pool in the code buffer.
509  // Every literal is placed on a 32bit boundary
510  // All the literals in the pool will be removed from the pool and potentially
511  // delete'd.
512  void EmitLiteralPool(LiteralPool* const literal_pool, EmitOption option) {
513    if (literal_pool->GetSize() > 0) {
514#ifdef VIXL_DEBUG
515      for (LiteralPool::RawLiteralListIterator literal_it =
516               literal_pool->GetFirst();
517           literal_it != literal_pool->GetEnd();
518           literal_it++) {
519        RawLiteral* literal = *literal_it;
520        VIXL_ASSERT(GetCursorOffset() < literal->GetCheckpoint());
521      }
522#endif
523      Label after_literal;
524      if (option == kBranchRequired) {
525        GetBuffer()->EnsureSpaceFor(kMaxInstructionSizeInBytes);
526#ifdef VIXL_DEBUG
527        bool save_assembler_state = AllowAssembler();
528        SetAllowAssembler(true);
529#endif
530        b(&after_literal);
531#ifdef VIXL_DEBUG
532        SetAllowAssembler(save_assembler_state);
533#endif
534      }
535      GetBuffer()->Align();
536      GetBuffer()->EnsureSpaceFor(literal_pool->GetSize());
537      for (LiteralPool::RawLiteralListIterator it = literal_pool->GetFirst();
538           it != literal_pool->GetEnd();
539           it++) {
540        place(*it);
541      }
542      if (option == kBranchRequired) bind(&after_literal);
543      literal_pool->Clear();
544    }
545  }
546  void EmitLiteralPool(EmitOption option = kBranchRequired) {
547    EmitLiteralPool(literal_pool_manager_.GetLiteralPool(), option);
548    literal_pool_manager_.ResetCheckpoint();
549    ComputeCheckpoint();
550  }
551
552  size_t GetLiteralPoolSize() const {
553    return literal_pool_manager_.GetLiteralPoolSize();
554  }
555
556  // Adr with a literal already constructed. Add the literal to the pool if it
557  // is not already done.
558  void Adr(Condition cond, Register rd, RawLiteral* literal) {
559    EmitLiteralCondRL<&Assembler::adr> emit_helper(cond, rd);
560    GenerateInstruction(emit_helper, literal);
561  }
562  void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); }
563
564  // Loads with literals already constructed. Add the literal to the pool
565  // if it is not already done.
566  void Ldr(Condition cond, Register rt, RawLiteral* literal) {
567    EmitLiteralCondRL<&Assembler::ldr> emit_helper(cond, rt);
568    GenerateInstruction(emit_helper, literal);
569  }
570  void Ldr(Register rt, RawLiteral* literal) { Ldr(al, rt, literal); }
571
572  void Ldrb(Condition cond, Register rt, RawLiteral* literal) {
573    EmitLiteralCondRL<&Assembler::ldrb> emit_helper(cond, rt);
574    GenerateInstruction(emit_helper, literal);
575  }
576  void Ldrb(Register rt, RawLiteral* literal) { Ldrb(al, rt, literal); }
577
578  void Ldrd(Condition cond, Register rt, Register rt2, RawLiteral* literal) {
579    EmitLiteralCondRRL<&Assembler::ldrd> emit_helper(cond, rt, rt2);
580    GenerateInstruction(emit_helper, literal);
581  }
582  void Ldrd(Register rt, Register rt2, RawLiteral* literal) {
583    Ldrd(al, rt, rt2, literal);
584  }
585
586  void Ldrh(Condition cond, Register rt, RawLiteral* literal) {
587    EmitLiteralCondRL<&Assembler::ldrh> emit_helper(cond, rt);
588    GenerateInstruction(emit_helper, literal);
589  }
590  void Ldrh(Register rt, RawLiteral* literal) { Ldrh(al, rt, literal); }
591
592  void Ldrsb(Condition cond, Register rt, RawLiteral* literal) {
593    EmitLiteralCondRL<&Assembler::ldrsb> emit_helper(cond, rt);
594    GenerateInstruction(emit_helper, literal);
595  }
596  void Ldrsb(Register rt, RawLiteral* literal) { Ldrsb(al, rt, literal); }
597
598  void Ldrsh(Condition cond, Register rt, RawLiteral* literal) {
599    EmitLiteralCondRL<&Assembler::ldrsh> emit_helper(cond, rt);
600    GenerateInstruction(emit_helper, literal);
601  }
602  void Ldrsh(Register rt, RawLiteral* literal) { Ldrsh(al, rt, literal); }
603
604  void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) {
605    EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(cond, dt, rd);
606    GenerateInstruction(emit_helper, literal);
607  }
608  void Vldr(DataType dt, DRegister rd, RawLiteral* literal) {
609    Vldr(al, dt, rd, literal);
610  }
611  void Vldr(Condition cond, DRegister rd, RawLiteral* literal) {
612    Vldr(cond, Untyped64, rd, literal);
613  }
614  void Vldr(DRegister rd, RawLiteral* literal) {
615    Vldr(al, Untyped64, rd, literal);
616  }
617
618  void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) {
619    EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(cond, dt, rd);
620    GenerateInstruction(emit_helper, literal);
621  }
622  void Vldr(DataType dt, SRegister rd, RawLiteral* literal) {
623    Vldr(al, dt, rd, literal);
624  }
625  void Vldr(Condition cond, SRegister rd, RawLiteral* literal) {
626    Vldr(cond, Untyped32, rd, literal);
627  }
628  void Vldr(SRegister rd, RawLiteral* literal) {
629    Vldr(al, Untyped32, rd, literal);
630  }
631
632  // Generic Ldr(register, data)
633  void Ldr(Condition cond, Register rt, uint32_t v) {
634    RawLiteral* literal =
635        new Literal<uint32_t>(v, RawLiteral::kDeletedOnPlacementByPool);
636    EmitLiteralCondRL<&Assembler::ldr> emit_helper(cond, rt);
637    GenerateInstruction(emit_helper, literal);
638  }
639  template <typename T>
640  void Ldr(Register rt, T v) {
641    Ldr(al, rt, v);
642  }
643
644  // Generic Ldrd(rt, rt2, data)
645  void Ldrd(Condition cond, Register rt, Register rt2, uint64_t v) {
646    RawLiteral* literal =
647        new Literal<uint64_t>(v, RawLiteral::kDeletedOnPlacementByPool);
648    EmitLiteralCondRRL<&Assembler::ldrd> emit_helper(cond, rt, rt2);
649    GenerateInstruction(emit_helper, literal);
650  }
651  template <typename T>
652  void Ldrd(Register rt, Register rt2, T v) {
653    Ldrd(al, rt, rt2, v);
654  }
655
656  void Vldr(Condition cond, SRegister rd, float v) {
657    RawLiteral* literal =
658        new Literal<float>(v, RawLiteral::kDeletedOnPlacementByPool);
659    EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(cond, Untyped32, rd);
660    GenerateInstruction(emit_helper, literal);
661  }
662  void Vldr(SRegister rd, float v) { Vldr(al, rd, v); }
663
664  void Vldr(Condition cond, DRegister rd, double v) {
665    RawLiteral* literal =
666        new Literal<double>(v, RawLiteral::kDeletedOnPlacementByPool);
667    EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(cond, Untyped64, rd);
668    GenerateInstruction(emit_helper, literal);
669  }
670  void Vldr(DRegister rd, double v) { Vldr(al, rd, v); }
671
672  void Vmov(Condition cond, DRegister rt, double v) { Vmov(cond, F64, rt, v); }
673  void Vmov(DRegister rt, double v) { Vmov(al, F64, rt, v); }
674  void Vmov(Condition cond, SRegister rt, float v) { Vmov(cond, F32, rt, v); }
675  void Vmov(SRegister rt, float v) { Vmov(al, F32, rt, v); }
676
677  void Switch(Register reg, JumpTableBase* table);
678  void GenerateSwitchTable(JumpTableBase* table, int table_size);
679  void Case(JumpTableBase* table, int case_index);
680  void Break(JumpTableBase* table);
681  void Default(JumpTableBase* table);
682  void EndSwitch(JumpTableBase* table);
683
684  // Claim memory on the stack.
685  // Note that the Claim, Drop, and Peek helpers below ensure that offsets used
686  // are multiples of 32 bits to help maintain 32-bit SP alignment.
687  // We could `Align{Up,Down}(size, 4)`, but that's potentially problematic:
688  //     Claim(3)
689  //     Claim(1)
690  //     Drop(4)
691  // would seem correct, when in fact:
692  //    Claim(3) -> sp = sp - 4
693  //    Claim(1) -> sp = sp - 4
694  //    Drop(4)  -> sp = sp + 4
695  //
696  void Claim(int32_t size) {
697    if (size == 0) return;
698    // The stack must be kept 32bit aligned.
699    VIXL_ASSERT((size > 0) && ((size % 4) == 0));
700    Sub(sp, sp, size);
701  }
702  // Release memory on the stack
703  void Drop(int32_t size) {
704    if (size == 0) return;
705    // The stack must be kept 32bit aligned.
706    VIXL_ASSERT((size > 0) && ((size % 4) == 0));
707    Add(sp, sp, size);
708  }
709  void Peek(Register dst, int32_t offset) {
710    VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0));
711    Ldr(dst, MemOperand(sp, offset));
712  }
713  void Poke(Register src, int32_t offset) {
714    VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0));
715    Str(src, MemOperand(sp, offset));
716  }
717  void Printf(const char* format,
718              CPURegister reg1 = NoReg,
719              CPURegister reg2 = NoReg,
720              CPURegister reg3 = NoReg,
721              CPURegister reg4 = NoReg);
722  // Functions used by Printf for generation.
723  void PushRegister(CPURegister reg);
724  void PreparePrintfArgument(CPURegister reg,
725                             int* core_count,
726                             int* vfp_count,
727                             uint32_t* printf_type);
728  // Handlers for cases not handled by the assembler.
729  virtual void Delegate(InstructionType type,
730                        InstructionCondROp instruction,
731                        Condition cond,
732                        Register rn,
733                        const Operand& operand) VIXL_OVERRIDE;
734  virtual void Delegate(InstructionType type,
735                        InstructionCondSizeROp instruction,
736                        Condition cond,
737                        EncodingSize size,
738                        Register rn,
739                        const Operand& operand) VIXL_OVERRIDE;
740  virtual void Delegate(InstructionType type,
741                        InstructionCondRROp instruction,
742                        Condition cond,
743                        Register rd,
744                        Register rn,
745                        const Operand& operand) VIXL_OVERRIDE;
746  virtual void Delegate(InstructionType type,
747                        InstructionCondSizeRROp instruction,
748                        Condition cond,
749                        EncodingSize size,
750                        Register rd,
751                        Register rn,
752                        const Operand& operand) VIXL_OVERRIDE;
753  virtual void Delegate(InstructionType type,
754                        InstructionRL instruction,
755                        Register rn,
756                        Label* label) VIXL_OVERRIDE;
757  virtual void Delegate(InstructionType type,
758                        InstructionCondDtSSop instruction,
759                        Condition cond,
760                        DataType dt,
761                        SRegister rd,
762                        const SOperand& operand) VIXL_OVERRIDE;
763  virtual void Delegate(InstructionType type,
764                        InstructionCondDtDDop instruction,
765                        Condition cond,
766                        DataType dt,
767                        DRegister rd,
768                        const DOperand& operand) VIXL_OVERRIDE;
769  virtual void Delegate(InstructionType type,
770                        InstructionCondDtQQop instruction,
771                        Condition cond,
772                        DataType dt,
773                        QRegister rd,
774                        const QOperand& operand) VIXL_OVERRIDE;
775  virtual void Delegate(InstructionType type,
776                        InstructionCondMop instruction,
777                        Condition cond,
778                        const MemOperand& operand) VIXL_OVERRIDE;
779  virtual void Delegate(InstructionType type,
780                        InstructionCondRMop instruction,
781                        Condition cond,
782                        Register rd,
783                        const MemOperand& operand) VIXL_OVERRIDE;
784  virtual void Delegate(InstructionType type,
785                        InstructionCondSizeRMop instruction,
786                        Condition cond,
787                        EncodingSize size,
788                        Register rd,
789                        const MemOperand& operand) VIXL_OVERRIDE;
790  virtual void Delegate(InstructionType type,
791                        InstructionCondRRMop instruction,
792                        Condition cond,
793                        Register rt,
794                        Register rt2,
795                        const MemOperand& operand) VIXL_OVERRIDE;
796  virtual void Delegate(InstructionType type,
797                        InstructionCondRRRMop instruction,
798                        Condition cond,
799                        Register rd,
800                        Register rt,
801                        Register rt2,
802                        const MemOperand& operand) VIXL_OVERRIDE;
803  virtual void Delegate(InstructionType type,
804                        InstructionCondDtSMop instruction,
805                        Condition cond,
806                        DataType dt,
807                        SRegister rd,
808                        const MemOperand& operand) VIXL_OVERRIDE;
809  virtual void Delegate(InstructionType type,
810                        InstructionCondDtDMop instruction,
811                        Condition cond,
812                        DataType dt,
813                        DRegister rd,
814                        const MemOperand& operand) VIXL_OVERRIDE;
815  virtual void Delegate(InstructionType type,
816                        InstructionCondDtNrlMop instruction,
817                        Condition cond,
818                        DataType dt,
819                        const NeonRegisterList& reglist,
820                        const MemOperand& operand) VIXL_OVERRIDE;
821  virtual void Delegate(InstructionType type,
822                        InstructionCondMsrOp instruction,
823                        Condition cond,
824                        MaskedSpecialRegister spec_reg,
825                        const Operand& operand) VIXL_OVERRIDE;
826
827  // Start of generated code.
828
829  void Adc(Condition cond, Register rd, Register rn, const Operand& operand) {
830    VIXL_ASSERT(allow_macro_instructions_);
831    VIXL_ASSERT(OutsideITBlock());
832    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
833    bool can_use_it =
834        // ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1
835        operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
836        operand.GetBaseRegister().IsLow();
837    ITScope it_scope(this, &cond, can_use_it);
838    adc(cond, rd, rn, operand);
839  }
840  void Adc(Register rd, Register rn, const Operand& operand) {
841    Adc(al, rd, rn, operand);
842  }
843  void Adc(FlagsUpdate flags,
844           Condition cond,
845           Register rd,
846           Register rn,
847           const Operand& operand) {
848    switch (flags) {
849      case LeaveFlags:
850        Adc(cond, rd, rn, operand);
851        break;
852      case SetFlags:
853        Adcs(cond, rd, rn, operand);
854        break;
855      case DontCare:
856        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
857                                    rn.Is(rd) && operand.IsPlainRegister() &&
858                                    operand.GetBaseRegister().IsLow();
859        if (can_be_16bit_encoded) {
860          Adcs(cond, rd, rn, operand);
861        } else {
862          Adc(cond, rd, rn, operand);
863        }
864        break;
865    }
866  }
867  void Adc(FlagsUpdate flags,
868           Register rd,
869           Register rn,
870           const Operand& operand) {
871    Adc(flags, al, rd, rn, operand);
872  }
873
874  void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) {
875    VIXL_ASSERT(allow_macro_instructions_);
876    VIXL_ASSERT(OutsideITBlock());
877    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
878    ITScope it_scope(this, &cond);
879    adcs(cond, rd, rn, operand);
880  }
881  void Adcs(Register rd, Register rn, const Operand& operand) {
882    Adcs(al, rd, rn, operand);
883  }
884
885  void Add(Condition cond, Register rd, Register rn, const Operand& operand) {
886    VIXL_ASSERT(allow_macro_instructions_);
887    VIXL_ASSERT(OutsideITBlock());
888    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
889    if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
890      uint32_t immediate = operand.GetImmediate();
891      if (immediate == 0) {
892        return;
893      }
894    }
895    bool can_use_it =
896        // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
897        (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() &&
898         rd.IsLow()) ||
899        // ADD<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2
900        (operand.IsImmediate() && (operand.GetImmediate() <= 255) &&
901         rd.IsLow() && rn.Is(rd)) ||
902        // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1
903        (operand.IsImmediate() && (operand.GetImmediate() <= 508) &&
904         ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) ||
905        // ADD<c>{<q>} <Rd>, <Rn>, <Rm>
906        (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
907         operand.GetBaseRegister().IsLow()) ||
908        // ADD<c>{<q>} <Rdn>, <Rm> ; T2
909        (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) &&
910         !operand.GetBaseRegister().IsSP() &&
911         !operand.GetBaseRegister().IsPC()) ||
912        // ADD{<c>}{<q>} {<Rdm>,} SP, <Rdm> ; T1
913        (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() &&
914         operand.GetBaseRegister().Is(rd));
915    ITScope it_scope(this, &cond, can_use_it);
916    add(cond, rd, rn, operand);
917  }
918  void Add(Register rd, Register rn, const Operand& operand) {
919    Add(al, rd, rn, operand);
920  }
921  void Add(FlagsUpdate flags,
922           Condition cond,
923           Register rd,
924           Register rn,
925           const Operand& operand) {
926    switch (flags) {
927      case LeaveFlags:
928        Add(cond, rd, rn, operand);
929        break;
930      case SetFlags:
931        Adds(cond, rd, rn, operand);
932        break;
933      case DontCare:
934        bool can_be_16bit_encoded =
935            IsUsingT32() && cond.Is(al) &&
936            ((operand.IsPlainRegister() &&
937              ((rd.IsLow() && rn.IsLow() &&
938                operand.GetBaseRegister().IsLow()) ||
939               rd.Is(rn))) ||
940             (operand.IsImmediate() &&
941              ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
942               (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
943        if (can_be_16bit_encoded) {
944          Adds(cond, rd, rn, operand);
945        } else {
946          Add(cond, rd, rn, operand);
947        }
948        break;
949    }
950  }
951  void Add(FlagsUpdate flags,
952           Register rd,
953           Register rn,
954           const Operand& operand) {
955    Add(flags, al, rd, rn, operand);
956  }
957
958  void Adds(Condition cond, Register rd, Register rn, const Operand& operand) {
959    VIXL_ASSERT(allow_macro_instructions_);
960    VIXL_ASSERT(OutsideITBlock());
961    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
962    ITScope it_scope(this, &cond);
963    adds(cond, rd, rn, operand);
964  }
965  void Adds(Register rd, Register rn, const Operand& operand) {
966    Adds(al, rd, rn, operand);
967  }
968
969  void Addw(Condition cond, Register rd, Register rn, const Operand& operand) {
970    VIXL_ASSERT(allow_macro_instructions_);
971    VIXL_ASSERT(OutsideITBlock());
972    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
973    ITScope it_scope(this, &cond);
974    addw(cond, rd, rn, operand);
975  }
976  void Addw(Register rd, Register rn, const Operand& operand) {
977    Addw(al, rd, rn, operand);
978  }
979
980  void Adr(Condition cond, Register rd, Label* label) {
981    VIXL_ASSERT(allow_macro_instructions_);
982    VIXL_ASSERT(OutsideITBlock());
983    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
984    ITScope it_scope(this, &cond);
985    adr(cond, rd, label);
986  }
987  void Adr(Register rd, Label* label) { Adr(al, rd, label); }
988
989  void And(Condition cond, Register rd, Register rn, const Operand& operand) {
990    VIXL_ASSERT(allow_macro_instructions_);
991    VIXL_ASSERT(OutsideITBlock());
992    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
993    if (cond.Is(al) && operand.IsImmediate()) {
994      uint32_t immediate = operand.GetImmediate();
995      if (immediate == 0) {
996        mov(rd, 0);
997        return;
998      }
999      if ((immediate == 0xffffffff) && rd.Is(rn)) {
1000        return;
1001      }
1002    }
1003    bool can_use_it =
1004        // AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1
1005        operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1006        operand.GetBaseRegister().IsLow();
1007    ITScope it_scope(this, &cond, can_use_it);
1008    and_(cond, rd, rn, operand);
1009  }
1010  void And(Register rd, Register rn, const Operand& operand) {
1011    And(al, rd, rn, operand);
1012  }
1013  void And(FlagsUpdate flags,
1014           Condition cond,
1015           Register rd,
1016           Register rn,
1017           const Operand& operand) {
1018    switch (flags) {
1019      case LeaveFlags:
1020        And(cond, rd, rn, operand);
1021        break;
1022      case SetFlags:
1023        Ands(cond, rd, rn, operand);
1024        break;
1025      case DontCare:
1026        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1027                                    rn.Is(rd) && operand.IsPlainRegister() &&
1028                                    operand.GetBaseRegister().IsLow();
1029        if (can_be_16bit_encoded) {
1030          Ands(cond, rd, rn, operand);
1031        } else {
1032          And(cond, rd, rn, operand);
1033        }
1034        break;
1035    }
1036  }
1037  void And(FlagsUpdate flags,
1038           Register rd,
1039           Register rn,
1040           const Operand& operand) {
1041    And(flags, al, rd, rn, operand);
1042  }
1043
1044  void Ands(Condition cond, Register rd, Register rn, const Operand& operand) {
1045    VIXL_ASSERT(allow_macro_instructions_);
1046    VIXL_ASSERT(OutsideITBlock());
1047    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1048    ITScope it_scope(this, &cond);
1049    ands(cond, rd, rn, operand);
1050  }
1051  void Ands(Register rd, Register rn, const Operand& operand) {
1052    Ands(al, rd, rn, operand);
1053  }
1054
1055  void Asr(Condition cond, Register rd, Register rm, const Operand& operand) {
1056    VIXL_ASSERT(allow_macro_instructions_);
1057    VIXL_ASSERT(OutsideITBlock());
1058    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1059    bool can_use_it =
1060        // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
1061        (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
1062         (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
1063        // ASR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1
1064        (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
1065         operand.GetBaseRegister().IsLow());
1066    ITScope it_scope(this, &cond, can_use_it);
1067    asr(cond, rd, rm, operand);
1068  }
1069  void Asr(Register rd, Register rm, const Operand& operand) {
1070    Asr(al, rd, rm, operand);
1071  }
1072  void Asr(FlagsUpdate flags,
1073           Condition cond,
1074           Register rd,
1075           Register rm,
1076           const Operand& operand) {
1077    switch (flags) {
1078      case LeaveFlags:
1079        Asr(cond, rd, rm, operand);
1080        break;
1081      case SetFlags:
1082        Asrs(cond, rd, rm, operand);
1083        break;
1084      case DontCare:
1085        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1086                                    rm.IsLow() && operand.IsImmediate() &&
1087                                    (operand.GetImmediate() < 32);
1088        if (can_be_16bit_encoded) {
1089          Asrs(cond, rd, rm, operand);
1090        } else {
1091          Asr(cond, rd, rm, operand);
1092        }
1093        break;
1094    }
1095  }
1096  void Asr(FlagsUpdate flags,
1097           Register rd,
1098           Register rm,
1099           const Operand& operand) {
1100    Asr(flags, al, rd, rm, operand);
1101  }
1102
1103  void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) {
1104    VIXL_ASSERT(allow_macro_instructions_);
1105    VIXL_ASSERT(OutsideITBlock());
1106    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1107    ITScope it_scope(this, &cond);
1108    asrs(cond, rd, rm, operand);
1109  }
1110  void Asrs(Register rd, Register rm, const Operand& operand) {
1111    Asrs(al, rd, rm, operand);
1112  }
1113
1114  void B(Condition cond, Label* label) {
1115    VIXL_ASSERT(allow_macro_instructions_);
1116    VIXL_ASSERT(OutsideITBlock());
1117    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1118    b(cond, label);
1119    AddBranchLabel(label);
1120  }
1121  void B(Label* label) { B(al, label); }
1122
1123  void Bfc(Condition cond, Register rd, uint32_t lsb, const Operand& operand) {
1124    VIXL_ASSERT(allow_macro_instructions_);
1125    VIXL_ASSERT(OutsideITBlock());
1126    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1127    ITScope it_scope(this, &cond);
1128    bfc(cond, rd, lsb, operand);
1129  }
1130  void Bfc(Register rd, uint32_t lsb, const Operand& operand) {
1131    Bfc(al, rd, lsb, operand);
1132  }
1133
1134  void Bfi(Condition cond,
1135           Register rd,
1136           Register rn,
1137           uint32_t lsb,
1138           const Operand& operand) {
1139    VIXL_ASSERT(allow_macro_instructions_);
1140    VIXL_ASSERT(OutsideITBlock());
1141    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1142    ITScope it_scope(this, &cond);
1143    bfi(cond, rd, rn, lsb, operand);
1144  }
1145  void Bfi(Register rd, Register rn, uint32_t lsb, const Operand& operand) {
1146    Bfi(al, rd, rn, lsb, operand);
1147  }
1148
1149  void Bic(Condition cond, Register rd, Register rn, const Operand& operand) {
1150    VIXL_ASSERT(allow_macro_instructions_);
1151    VIXL_ASSERT(OutsideITBlock());
1152    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1153    if (cond.Is(al) && operand.IsImmediate()) {
1154      uint32_t immediate = operand.GetImmediate();
1155      if ((immediate == 0) && rd.Is(rn)) {
1156        return;
1157      }
1158      if (immediate == 0xffffffff) {
1159        mov(rd, 0);
1160        return;
1161      }
1162    }
1163    bool can_use_it =
1164        // BIC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1
1165        operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1166        operand.GetBaseRegister().IsLow();
1167    ITScope it_scope(this, &cond, can_use_it);
1168    bic(cond, rd, rn, operand);
1169  }
1170  void Bic(Register rd, Register rn, const Operand& operand) {
1171    Bic(al, rd, rn, operand);
1172  }
1173  void Bic(FlagsUpdate flags,
1174           Condition cond,
1175           Register rd,
1176           Register rn,
1177           const Operand& operand) {
1178    switch (flags) {
1179      case LeaveFlags:
1180        Bic(cond, rd, rn, operand);
1181        break;
1182      case SetFlags:
1183        Bics(cond, rd, rn, operand);
1184        break;
1185      case DontCare:
1186        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1187                                    rn.Is(rd) && operand.IsPlainRegister() &&
1188                                    operand.GetBaseRegister().IsLow();
1189        if (can_be_16bit_encoded) {
1190          Bics(cond, rd, rn, operand);
1191        } else {
1192          Bic(cond, rd, rn, operand);
1193        }
1194        break;
1195    }
1196  }
1197  void Bic(FlagsUpdate flags,
1198           Register rd,
1199           Register rn,
1200           const Operand& operand) {
1201    Bic(flags, al, rd, rn, operand);
1202  }
1203
1204  void Bics(Condition cond, Register rd, Register rn, const Operand& operand) {
1205    VIXL_ASSERT(allow_macro_instructions_);
1206    VIXL_ASSERT(OutsideITBlock());
1207    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1208    ITScope it_scope(this, &cond);
1209    bics(cond, rd, rn, operand);
1210  }
1211  void Bics(Register rd, Register rn, const Operand& operand) {
1212    Bics(al, rd, rn, operand);
1213  }
1214
1215  void Bkpt(Condition cond, uint32_t imm) {
1216    VIXL_ASSERT(allow_macro_instructions_);
1217    VIXL_ASSERT(OutsideITBlock());
1218    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1219    ITScope it_scope(this, &cond);
1220    bkpt(cond, imm);
1221  }
1222  void Bkpt(uint32_t imm) { Bkpt(al, imm); }
1223
1224  void Bl(Condition cond, Label* label) {
1225    VIXL_ASSERT(allow_macro_instructions_);
1226    VIXL_ASSERT(OutsideITBlock());
1227    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1228    ITScope it_scope(this, &cond);
1229    bl(cond, label);
1230    AddBranchLabel(label);
1231  }
1232  void Bl(Label* label) { Bl(al, label); }
1233
1234  void Blx(Condition cond, Label* label) {
1235    VIXL_ASSERT(allow_macro_instructions_);
1236    VIXL_ASSERT(OutsideITBlock());
1237    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1238    ITScope it_scope(this, &cond);
1239    blx(cond, label);
1240    AddBranchLabel(label);
1241  }
1242  void Blx(Label* label) { Blx(al, label); }
1243
1244  void Blx(Condition cond, Register rm) {
1245    VIXL_ASSERT(allow_macro_instructions_);
1246    VIXL_ASSERT(OutsideITBlock());
1247    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1248    bool can_use_it =
1249        // BLX{<c>}{<q>} <Rm> ; T1
1250        !rm.IsPC();
1251    ITScope it_scope(this, &cond, can_use_it);
1252    blx(cond, rm);
1253  }
1254  void Blx(Register rm) { Blx(al, rm); }
1255
1256  void Bx(Condition cond, Register rm) {
1257    VIXL_ASSERT(allow_macro_instructions_);
1258    VIXL_ASSERT(OutsideITBlock());
1259    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1260    bool can_use_it =
1261        // BX{<c>}{<q>} <Rm> ; T1
1262        !rm.IsPC();
1263    ITScope it_scope(this, &cond, can_use_it);
1264    bx(cond, rm);
1265  }
1266  void Bx(Register rm) { Bx(al, rm); }
1267
1268  void Bxj(Condition cond, Register rm) {
1269    VIXL_ASSERT(allow_macro_instructions_);
1270    VIXL_ASSERT(OutsideITBlock());
1271    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1272    ITScope it_scope(this, &cond);
1273    bxj(cond, rm);
1274  }
1275  void Bxj(Register rm) { Bxj(al, rm); }
1276
1277  void Cbnz(Register rn, Label* label) {
1278    VIXL_ASSERT(allow_macro_instructions_);
1279    VIXL_ASSERT(OutsideITBlock());
1280    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1281    cbnz(rn, label);
1282    AddBranchLabel(label);
1283  }
1284
1285  void Cbz(Register rn, Label* label) {
1286    VIXL_ASSERT(allow_macro_instructions_);
1287    VIXL_ASSERT(OutsideITBlock());
1288    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1289    cbz(rn, label);
1290    AddBranchLabel(label);
1291  }
1292
1293  void Clrex(Condition cond) {
1294    VIXL_ASSERT(allow_macro_instructions_);
1295    VIXL_ASSERT(OutsideITBlock());
1296    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1297    ITScope it_scope(this, &cond);
1298    clrex(cond);
1299  }
1300  void Clrex() { Clrex(al); }
1301
1302  void Clz(Condition cond, Register rd, Register rm) {
1303    VIXL_ASSERT(allow_macro_instructions_);
1304    VIXL_ASSERT(OutsideITBlock());
1305    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1306    ITScope it_scope(this, &cond);
1307    clz(cond, rd, rm);
1308  }
1309  void Clz(Register rd, Register rm) { Clz(al, rd, rm); }
1310
1311  void Cmn(Condition cond, Register rn, const Operand& operand) {
1312    VIXL_ASSERT(allow_macro_instructions_);
1313    VIXL_ASSERT(OutsideITBlock());
1314    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1315    bool can_use_it =
1316        // CMN{<c>}{<q>} <Rn>, <Rm> ; T1
1317        operand.IsPlainRegister() && rn.IsLow() &&
1318        operand.GetBaseRegister().IsLow();
1319    ITScope it_scope(this, &cond, can_use_it);
1320    cmn(cond, rn, operand);
1321  }
1322  void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); }
1323
1324  void Cmp(Condition cond, Register rn, const Operand& operand) {
1325    VIXL_ASSERT(allow_macro_instructions_);
1326    VIXL_ASSERT(OutsideITBlock());
1327    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1328    bool can_use_it =
1329        // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
1330        (operand.IsImmediate() && (operand.GetImmediate() <= 255) &&
1331         rn.IsLow()) ||
1332        // CMP{<c>}{<q>} <Rn>, <Rm> ; T1 T2
1333        (operand.IsPlainRegister() && !rn.IsPC() &&
1334         !operand.GetBaseRegister().IsPC());
1335    ITScope it_scope(this, &cond, can_use_it);
1336    cmp(cond, rn, operand);
1337  }
1338  void Cmp(Register rn, const Operand& operand) { Cmp(al, rn, operand); }
1339
1340  void Crc32b(Condition cond, Register rd, Register rn, Register rm) {
1341    VIXL_ASSERT(allow_macro_instructions_);
1342    VIXL_ASSERT(OutsideITBlock());
1343    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1344    ITScope it_scope(this, &cond);
1345    crc32b(cond, rd, rn, rm);
1346  }
1347  void Crc32b(Register rd, Register rn, Register rm) { Crc32b(al, rd, rn, rm); }
1348
1349  void Crc32cb(Condition cond, Register rd, Register rn, Register rm) {
1350    VIXL_ASSERT(allow_macro_instructions_);
1351    VIXL_ASSERT(OutsideITBlock());
1352    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1353    ITScope it_scope(this, &cond);
1354    crc32cb(cond, rd, rn, rm);
1355  }
1356  void Crc32cb(Register rd, Register rn, Register rm) {
1357    Crc32cb(al, rd, rn, rm);
1358  }
1359
1360  void Crc32ch(Condition cond, Register rd, Register rn, Register rm) {
1361    VIXL_ASSERT(allow_macro_instructions_);
1362    VIXL_ASSERT(OutsideITBlock());
1363    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1364    ITScope it_scope(this, &cond);
1365    crc32ch(cond, rd, rn, rm);
1366  }
1367  void Crc32ch(Register rd, Register rn, Register rm) {
1368    Crc32ch(al, rd, rn, rm);
1369  }
1370
1371  void Crc32cw(Condition cond, Register rd, Register rn, Register rm) {
1372    VIXL_ASSERT(allow_macro_instructions_);
1373    VIXL_ASSERT(OutsideITBlock());
1374    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1375    ITScope it_scope(this, &cond);
1376    crc32cw(cond, rd, rn, rm);
1377  }
1378  void Crc32cw(Register rd, Register rn, Register rm) {
1379    Crc32cw(al, rd, rn, rm);
1380  }
1381
1382  void Crc32h(Condition cond, Register rd, Register rn, Register rm) {
1383    VIXL_ASSERT(allow_macro_instructions_);
1384    VIXL_ASSERT(OutsideITBlock());
1385    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1386    ITScope it_scope(this, &cond);
1387    crc32h(cond, rd, rn, rm);
1388  }
1389  void Crc32h(Register rd, Register rn, Register rm) { Crc32h(al, rd, rn, rm); }
1390
1391  void Crc32w(Condition cond, Register rd, Register rn, Register rm) {
1392    VIXL_ASSERT(allow_macro_instructions_);
1393    VIXL_ASSERT(OutsideITBlock());
1394    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1395    ITScope it_scope(this, &cond);
1396    crc32w(cond, rd, rn, rm);
1397  }
1398  void Crc32w(Register rd, Register rn, Register rm) { Crc32w(al, rd, rn, rm); }
1399
1400  void Dmb(Condition cond, MemoryBarrier option) {
1401    VIXL_ASSERT(allow_macro_instructions_);
1402    VIXL_ASSERT(OutsideITBlock());
1403    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1404    ITScope it_scope(this, &cond);
1405    dmb(cond, option);
1406  }
1407  void Dmb(MemoryBarrier option) { Dmb(al, option); }
1408
1409  void Dsb(Condition cond, MemoryBarrier option) {
1410    VIXL_ASSERT(allow_macro_instructions_);
1411    VIXL_ASSERT(OutsideITBlock());
1412    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1413    ITScope it_scope(this, &cond);
1414    dsb(cond, option);
1415  }
1416  void Dsb(MemoryBarrier option) { Dsb(al, option); }
1417
1418  void Eor(Condition cond, Register rd, Register rn, const Operand& operand) {
1419    VIXL_ASSERT(allow_macro_instructions_);
1420    VIXL_ASSERT(OutsideITBlock());
1421    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1422    if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1423      uint32_t immediate = operand.GetImmediate();
1424      if (immediate == 0) {
1425        return;
1426      }
1427      if (immediate == 0xffffffff) {
1428        mvn(rd, rn);
1429        return;
1430      }
1431    }
1432    bool can_use_it =
1433        // EOR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1
1434        operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1435        operand.GetBaseRegister().IsLow();
1436    ITScope it_scope(this, &cond, can_use_it);
1437    eor(cond, rd, rn, operand);
1438  }
1439  void Eor(Register rd, Register rn, const Operand& operand) {
1440    Eor(al, rd, rn, operand);
1441  }
1442  void Eor(FlagsUpdate flags,
1443           Condition cond,
1444           Register rd,
1445           Register rn,
1446           const Operand& operand) {
1447    switch (flags) {
1448      case LeaveFlags:
1449        Eor(cond, rd, rn, operand);
1450        break;
1451      case SetFlags:
1452        Eors(cond, rd, rn, operand);
1453        break;
1454      case DontCare:
1455        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1456                                    rn.Is(rd) && operand.IsPlainRegister() &&
1457                                    operand.GetBaseRegister().IsLow();
1458        if (can_be_16bit_encoded) {
1459          Eors(cond, rd, rn, operand);
1460        } else {
1461          Eor(cond, rd, rn, operand);
1462        }
1463        break;
1464    }
1465  }
1466  void Eor(FlagsUpdate flags,
1467           Register rd,
1468           Register rn,
1469           const Operand& operand) {
1470    Eor(flags, al, rd, rn, operand);
1471  }
1472
1473  void Eors(Condition cond, Register rd, Register rn, const Operand& operand) {
1474    VIXL_ASSERT(allow_macro_instructions_);
1475    VIXL_ASSERT(OutsideITBlock());
1476    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1477    ITScope it_scope(this, &cond);
1478    eors(cond, rd, rn, operand);
1479  }
1480  void Eors(Register rd, Register rn, const Operand& operand) {
1481    Eors(al, rd, rn, operand);
1482  }
1483
1484  void Fldmdbx(Condition cond,
1485               Register rn,
1486               WriteBack write_back,
1487               DRegisterList dreglist) {
1488    VIXL_ASSERT(allow_macro_instructions_);
1489    VIXL_ASSERT(OutsideITBlock());
1490    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1491    ITScope it_scope(this, &cond);
1492    fldmdbx(cond, rn, write_back, dreglist);
1493  }
1494  void Fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) {
1495    Fldmdbx(al, rn, write_back, dreglist);
1496  }
1497
1498  void Fldmiax(Condition cond,
1499               Register rn,
1500               WriteBack write_back,
1501               DRegisterList dreglist) {
1502    VIXL_ASSERT(allow_macro_instructions_);
1503    VIXL_ASSERT(OutsideITBlock());
1504    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1505    ITScope it_scope(this, &cond);
1506    fldmiax(cond, rn, write_back, dreglist);
1507  }
1508  void Fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) {
1509    Fldmiax(al, rn, write_back, dreglist);
1510  }
1511
1512  void Fstmdbx(Condition cond,
1513               Register rn,
1514               WriteBack write_back,
1515               DRegisterList dreglist) {
1516    VIXL_ASSERT(allow_macro_instructions_);
1517    VIXL_ASSERT(OutsideITBlock());
1518    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1519    ITScope it_scope(this, &cond);
1520    fstmdbx(cond, rn, write_back, dreglist);
1521  }
1522  void Fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) {
1523    Fstmdbx(al, rn, write_back, dreglist);
1524  }
1525
1526  void Fstmiax(Condition cond,
1527               Register rn,
1528               WriteBack write_back,
1529               DRegisterList dreglist) {
1530    VIXL_ASSERT(allow_macro_instructions_);
1531    VIXL_ASSERT(OutsideITBlock());
1532    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1533    ITScope it_scope(this, &cond);
1534    fstmiax(cond, rn, write_back, dreglist);
1535  }
1536  void Fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) {
1537    Fstmiax(al, rn, write_back, dreglist);
1538  }
1539
1540  void Hlt(Condition cond, uint32_t imm) {
1541    VIXL_ASSERT(allow_macro_instructions_);
1542    VIXL_ASSERT(OutsideITBlock());
1543    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1544    ITScope it_scope(this, &cond);
1545    hlt(cond, imm);
1546  }
1547  void Hlt(uint32_t imm) { Hlt(al, imm); }
1548
1549  void Hvc(Condition cond, uint32_t imm) {
1550    VIXL_ASSERT(allow_macro_instructions_);
1551    VIXL_ASSERT(OutsideITBlock());
1552    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1553    ITScope it_scope(this, &cond);
1554    hvc(cond, imm);
1555  }
1556  void Hvc(uint32_t imm) { Hvc(al, imm); }
1557
1558  void Isb(Condition cond, MemoryBarrier option) {
1559    VIXL_ASSERT(allow_macro_instructions_);
1560    VIXL_ASSERT(OutsideITBlock());
1561    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1562    ITScope it_scope(this, &cond);
1563    isb(cond, option);
1564  }
1565  void Isb(MemoryBarrier option) { Isb(al, option); }
1566
1567
1568  void Lda(Condition cond, Register rt, const MemOperand& operand) {
1569    VIXL_ASSERT(allow_macro_instructions_);
1570    VIXL_ASSERT(OutsideITBlock());
1571    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1572    ITScope it_scope(this, &cond);
1573    lda(cond, rt, operand);
1574  }
1575  void Lda(Register rt, const MemOperand& operand) { Lda(al, rt, operand); }
1576
1577  void Ldab(Condition cond, Register rt, const MemOperand& operand) {
1578    VIXL_ASSERT(allow_macro_instructions_);
1579    VIXL_ASSERT(OutsideITBlock());
1580    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1581    ITScope it_scope(this, &cond);
1582    ldab(cond, rt, operand);
1583  }
1584  void Ldab(Register rt, const MemOperand& operand) { Ldab(al, rt, operand); }
1585
1586  void Ldaex(Condition cond, Register rt, const MemOperand& operand) {
1587    VIXL_ASSERT(allow_macro_instructions_);
1588    VIXL_ASSERT(OutsideITBlock());
1589    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1590    ITScope it_scope(this, &cond);
1591    ldaex(cond, rt, operand);
1592  }
1593  void Ldaex(Register rt, const MemOperand& operand) { Ldaex(al, rt, operand); }
1594
1595  void Ldaexb(Condition cond, Register rt, const MemOperand& operand) {
1596    VIXL_ASSERT(allow_macro_instructions_);
1597    VIXL_ASSERT(OutsideITBlock());
1598    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1599    ITScope it_scope(this, &cond);
1600    ldaexb(cond, rt, operand);
1601  }
1602  void Ldaexb(Register rt, const MemOperand& operand) {
1603    Ldaexb(al, rt, operand);
1604  }
1605
1606  void Ldaexd(Condition cond,
1607              Register rt,
1608              Register rt2,
1609              const MemOperand& operand) {
1610    VIXL_ASSERT(allow_macro_instructions_);
1611    VIXL_ASSERT(OutsideITBlock());
1612    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1613    ITScope it_scope(this, &cond);
1614    ldaexd(cond, rt, rt2, operand);
1615  }
1616  void Ldaexd(Register rt, Register rt2, const MemOperand& operand) {
1617    Ldaexd(al, rt, rt2, operand);
1618  }
1619
1620  void Ldaexh(Condition cond, Register rt, const MemOperand& operand) {
1621    VIXL_ASSERT(allow_macro_instructions_);
1622    VIXL_ASSERT(OutsideITBlock());
1623    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1624    ITScope it_scope(this, &cond);
1625    ldaexh(cond, rt, operand);
1626  }
1627  void Ldaexh(Register rt, const MemOperand& operand) {
1628    Ldaexh(al, rt, operand);
1629  }
1630
1631  void Ldah(Condition cond, Register rt, const MemOperand& operand) {
1632    VIXL_ASSERT(allow_macro_instructions_);
1633    VIXL_ASSERT(OutsideITBlock());
1634    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1635    ITScope it_scope(this, &cond);
1636    ldah(cond, rt, operand);
1637  }
1638  void Ldah(Register rt, const MemOperand& operand) { Ldah(al, rt, operand); }
1639
1640  void Ldm(Condition cond,
1641           Register rn,
1642           WriteBack write_back,
1643           RegisterList registers) {
1644    VIXL_ASSERT(allow_macro_instructions_);
1645    VIXL_ASSERT(OutsideITBlock());
1646    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1647    ITScope it_scope(this, &cond);
1648    ldm(cond, rn, write_back, registers);
1649  }
1650  void Ldm(Register rn, WriteBack write_back, RegisterList registers) {
1651    Ldm(al, rn, write_back, registers);
1652  }
1653
1654  void Ldmda(Condition cond,
1655             Register rn,
1656             WriteBack write_back,
1657             RegisterList registers) {
1658    VIXL_ASSERT(allow_macro_instructions_);
1659    VIXL_ASSERT(OutsideITBlock());
1660    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1661    ITScope it_scope(this, &cond);
1662    ldmda(cond, rn, write_back, registers);
1663  }
1664  void Ldmda(Register rn, WriteBack write_back, RegisterList registers) {
1665    Ldmda(al, rn, write_back, registers);
1666  }
1667
1668  void Ldmdb(Condition cond,
1669             Register rn,
1670             WriteBack write_back,
1671             RegisterList registers) {
1672    VIXL_ASSERT(allow_macro_instructions_);
1673    VIXL_ASSERT(OutsideITBlock());
1674    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1675    ITScope it_scope(this, &cond);
1676    ldmdb(cond, rn, write_back, registers);
1677  }
1678  void Ldmdb(Register rn, WriteBack write_back, RegisterList registers) {
1679    Ldmdb(al, rn, write_back, registers);
1680  }
1681
1682  void Ldmea(Condition cond,
1683             Register rn,
1684             WriteBack write_back,
1685             RegisterList registers) {
1686    VIXL_ASSERT(allow_macro_instructions_);
1687    VIXL_ASSERT(OutsideITBlock());
1688    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1689    ITScope it_scope(this, &cond);
1690    ldmea(cond, rn, write_back, registers);
1691  }
1692  void Ldmea(Register rn, WriteBack write_back, RegisterList registers) {
1693    Ldmea(al, rn, write_back, registers);
1694  }
1695
1696  void Ldmed(Condition cond,
1697             Register rn,
1698             WriteBack write_back,
1699             RegisterList registers) {
1700    VIXL_ASSERT(allow_macro_instructions_);
1701    VIXL_ASSERT(OutsideITBlock());
1702    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1703    ITScope it_scope(this, &cond);
1704    ldmed(cond, rn, write_back, registers);
1705  }
1706  void Ldmed(Register rn, WriteBack write_back, RegisterList registers) {
1707    Ldmed(al, rn, write_back, registers);
1708  }
1709
1710  void Ldmfa(Condition cond,
1711             Register rn,
1712             WriteBack write_back,
1713             RegisterList registers) {
1714    VIXL_ASSERT(allow_macro_instructions_);
1715    VIXL_ASSERT(OutsideITBlock());
1716    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1717    ITScope it_scope(this, &cond);
1718    ldmfa(cond, rn, write_back, registers);
1719  }
1720  void Ldmfa(Register rn, WriteBack write_back, RegisterList registers) {
1721    Ldmfa(al, rn, write_back, registers);
1722  }
1723
1724  void Ldmfd(Condition cond,
1725             Register rn,
1726             WriteBack write_back,
1727             RegisterList registers) {
1728    VIXL_ASSERT(allow_macro_instructions_);
1729    VIXL_ASSERT(OutsideITBlock());
1730    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1731    ITScope it_scope(this, &cond);
1732    ldmfd(cond, rn, write_back, registers);
1733  }
1734  void Ldmfd(Register rn, WriteBack write_back, RegisterList registers) {
1735    Ldmfd(al, rn, write_back, registers);
1736  }
1737
1738  void Ldmib(Condition cond,
1739             Register rn,
1740             WriteBack write_back,
1741             RegisterList registers) {
1742    VIXL_ASSERT(allow_macro_instructions_);
1743    VIXL_ASSERT(OutsideITBlock());
1744    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1745    ITScope it_scope(this, &cond);
1746    ldmib(cond, rn, write_back, registers);
1747  }
1748  void Ldmib(Register rn, WriteBack write_back, RegisterList registers) {
1749    Ldmib(al, rn, write_back, registers);
1750  }
1751
1752  void Ldr(Condition cond, Register rt, const MemOperand& operand) {
1753    VIXL_ASSERT(allow_macro_instructions_);
1754    VIXL_ASSERT(OutsideITBlock());
1755    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1756    bool can_use_it =
1757        // LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1
1758        (operand.IsImmediate() && rt.IsLow() &&
1759         operand.GetBaseRegister().IsLow() &&
1760         operand.IsOffsetImmediateWithinRange(0, 124, 4) &&
1761         (operand.GetAddrMode() == Offset)) ||
1762        // LDR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2
1763        (operand.IsImmediate() && rt.IsLow() &&
1764         operand.GetBaseRegister().IsSP() &&
1765         operand.IsOffsetImmediateWithinRange(0, 1020, 4) &&
1766         (operand.GetAddrMode() == Offset)) ||
1767        // LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
1768        (operand.IsPlainRegister() && rt.IsLow() &&
1769         operand.GetBaseRegister().IsLow() &&
1770         operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
1771         (operand.GetAddrMode() == Offset));
1772    ITScope it_scope(this, &cond, can_use_it);
1773    ldr(cond, rt, operand);
1774  }
1775  void Ldr(Register rt, const MemOperand& operand) { Ldr(al, rt, operand); }
1776
1777  void Ldr(Condition cond, Register rt, Label* label) {
1778    VIXL_ASSERT(allow_macro_instructions_);
1779    VIXL_ASSERT(OutsideITBlock());
1780    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1781    ITScope it_scope(this, &cond);
1782    ldr(cond, rt, label);
1783  }
1784  void Ldr(Register rt, Label* label) { Ldr(al, rt, label); }
1785
1786  void Ldrb(Condition cond, Register rt, const MemOperand& operand) {
1787    VIXL_ASSERT(allow_macro_instructions_);
1788    VIXL_ASSERT(OutsideITBlock());
1789    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1790    bool can_use_it =
1791        // LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1
1792        (operand.IsImmediate() && rt.IsLow() &&
1793         operand.GetBaseRegister().IsLow() &&
1794         operand.IsOffsetImmediateWithinRange(0, 31) &&
1795         (operand.GetAddrMode() == Offset)) ||
1796        // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
1797        (operand.IsPlainRegister() && rt.IsLow() &&
1798         operand.GetBaseRegister().IsLow() &&
1799         operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
1800         (operand.GetAddrMode() == Offset));
1801    ITScope it_scope(this, &cond, can_use_it);
1802    ldrb(cond, rt, operand);
1803  }
1804  void Ldrb(Register rt, const MemOperand& operand) { Ldrb(al, rt, operand); }
1805
1806  void Ldrb(Condition cond, Register rt, Label* label) {
1807    VIXL_ASSERT(allow_macro_instructions_);
1808    VIXL_ASSERT(OutsideITBlock());
1809    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1810    ITScope it_scope(this, &cond);
1811    ldrb(cond, rt, label);
1812  }
1813  void Ldrb(Register rt, Label* label) { Ldrb(al, rt, label); }
1814
1815  void Ldrd(Condition cond,
1816            Register rt,
1817            Register rt2,
1818            const MemOperand& operand) {
1819    VIXL_ASSERT(allow_macro_instructions_);
1820    VIXL_ASSERT(OutsideITBlock());
1821    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1822    ITScope it_scope(this, &cond);
1823    ldrd(cond, rt, rt2, operand);
1824  }
1825  void Ldrd(Register rt, Register rt2, const MemOperand& operand) {
1826    Ldrd(al, rt, rt2, operand);
1827  }
1828
1829  void Ldrd(Condition cond, Register rt, Register rt2, Label* label) {
1830    VIXL_ASSERT(allow_macro_instructions_);
1831    VIXL_ASSERT(OutsideITBlock());
1832    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1833    ITScope it_scope(this, &cond);
1834    ldrd(cond, rt, rt2, label);
1835  }
1836  void Ldrd(Register rt, Register rt2, Label* label) {
1837    Ldrd(al, rt, rt2, label);
1838  }
1839
1840  void Ldrex(Condition cond, Register rt, const MemOperand& operand) {
1841    VIXL_ASSERT(allow_macro_instructions_);
1842    VIXL_ASSERT(OutsideITBlock());
1843    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1844    ITScope it_scope(this, &cond);
1845    ldrex(cond, rt, operand);
1846  }
1847  void Ldrex(Register rt, const MemOperand& operand) { Ldrex(al, rt, operand); }
1848
1849  void Ldrexb(Condition cond, Register rt, const MemOperand& operand) {
1850    VIXL_ASSERT(allow_macro_instructions_);
1851    VIXL_ASSERT(OutsideITBlock());
1852    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1853    ITScope it_scope(this, &cond);
1854    ldrexb(cond, rt, operand);
1855  }
1856  void Ldrexb(Register rt, const MemOperand& operand) {
1857    Ldrexb(al, rt, operand);
1858  }
1859
1860  void Ldrexd(Condition cond,
1861              Register rt,
1862              Register rt2,
1863              const MemOperand& operand) {
1864    VIXL_ASSERT(allow_macro_instructions_);
1865    VIXL_ASSERT(OutsideITBlock());
1866    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1867    ITScope it_scope(this, &cond);
1868    ldrexd(cond, rt, rt2, operand);
1869  }
1870  void Ldrexd(Register rt, Register rt2, const MemOperand& operand) {
1871    Ldrexd(al, rt, rt2, operand);
1872  }
1873
1874  void Ldrexh(Condition cond, Register rt, const MemOperand& operand) {
1875    VIXL_ASSERT(allow_macro_instructions_);
1876    VIXL_ASSERT(OutsideITBlock());
1877    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1878    ITScope it_scope(this, &cond);
1879    ldrexh(cond, rt, operand);
1880  }
1881  void Ldrexh(Register rt, const MemOperand& operand) {
1882    Ldrexh(al, rt, operand);
1883  }
1884
1885  void Ldrh(Condition cond, Register rt, const MemOperand& operand) {
1886    VIXL_ASSERT(allow_macro_instructions_);
1887    VIXL_ASSERT(OutsideITBlock());
1888    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1889    bool can_use_it =
1890        // LDRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1
1891        (operand.IsImmediate() && rt.IsLow() &&
1892         operand.GetBaseRegister().IsLow() &&
1893         operand.IsOffsetImmediateWithinRange(0, 62, 2) &&
1894         (operand.GetAddrMode() == Offset)) ||
1895        // LDRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
1896        (operand.IsPlainRegister() && rt.IsLow() &&
1897         operand.GetBaseRegister().IsLow() &&
1898         operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
1899         (operand.GetAddrMode() == Offset));
1900    ITScope it_scope(this, &cond, can_use_it);
1901    ldrh(cond, rt, operand);
1902  }
1903  void Ldrh(Register rt, const MemOperand& operand) { Ldrh(al, rt, operand); }
1904
1905  void Ldrh(Condition cond, Register rt, Label* label) {
1906    VIXL_ASSERT(allow_macro_instructions_);
1907    VIXL_ASSERT(OutsideITBlock());
1908    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1909    ITScope it_scope(this, &cond);
1910    ldrh(cond, rt, label);
1911  }
1912  void Ldrh(Register rt, Label* label) { Ldrh(al, rt, label); }
1913
1914  void Ldrsb(Condition cond, Register rt, const MemOperand& operand) {
1915    VIXL_ASSERT(allow_macro_instructions_);
1916    VIXL_ASSERT(OutsideITBlock());
1917    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1918    bool can_use_it =
1919        // LDRSB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
1920        operand.IsPlainRegister() && rt.IsLow() &&
1921        operand.GetBaseRegister().IsLow() &&
1922        operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
1923        (operand.GetAddrMode() == Offset);
1924    ITScope it_scope(this, &cond, can_use_it);
1925    ldrsb(cond, rt, operand);
1926  }
1927  void Ldrsb(Register rt, const MemOperand& operand) { Ldrsb(al, rt, operand); }
1928
1929  void Ldrsb(Condition cond, Register rt, Label* label) {
1930    VIXL_ASSERT(allow_macro_instructions_);
1931    VIXL_ASSERT(OutsideITBlock());
1932    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1933    ITScope it_scope(this, &cond);
1934    ldrsb(cond, rt, label);
1935  }
1936  void Ldrsb(Register rt, Label* label) { Ldrsb(al, rt, label); }
1937
1938  void Ldrsh(Condition cond, Register rt, const MemOperand& operand) {
1939    VIXL_ASSERT(allow_macro_instructions_);
1940    VIXL_ASSERT(OutsideITBlock());
1941    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1942    bool can_use_it =
1943        // LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
1944        operand.IsPlainRegister() && rt.IsLow() &&
1945        operand.GetBaseRegister().IsLow() &&
1946        operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
1947        (operand.GetAddrMode() == Offset);
1948    ITScope it_scope(this, &cond, can_use_it);
1949    ldrsh(cond, rt, operand);
1950  }
1951  void Ldrsh(Register rt, const MemOperand& operand) { Ldrsh(al, rt, operand); }
1952
1953  void Ldrsh(Condition cond, Register rt, Label* label) {
1954    VIXL_ASSERT(allow_macro_instructions_);
1955    VIXL_ASSERT(OutsideITBlock());
1956    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1957    ITScope it_scope(this, &cond);
1958    ldrsh(cond, rt, label);
1959  }
1960  void Ldrsh(Register rt, Label* label) { Ldrsh(al, rt, label); }
1961
1962  void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) {
1963    VIXL_ASSERT(allow_macro_instructions_);
1964    VIXL_ASSERT(OutsideITBlock());
1965    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
1966    bool can_use_it =
1967        // LSL<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
1968        (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
1969         (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) ||
1970        // LSL<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1
1971        (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
1972         operand.GetBaseRegister().IsLow());
1973    ITScope it_scope(this, &cond, can_use_it);
1974    lsl(cond, rd, rm, operand);
1975  }
1976  void Lsl(Register rd, Register rm, const Operand& operand) {
1977    Lsl(al, rd, rm, operand);
1978  }
1979  void Lsl(FlagsUpdate flags,
1980           Condition cond,
1981           Register rd,
1982           Register rm,
1983           const Operand& operand) {
1984    switch (flags) {
1985      case LeaveFlags:
1986        Lsl(cond, rd, rm, operand);
1987        break;
1988      case SetFlags:
1989        Lsls(cond, rd, rm, operand);
1990        break;
1991      case DontCare:
1992        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1993                                    rm.IsLow() && operand.IsImmediate() &&
1994                                    (operand.GetImmediate() < 32) &&
1995                                    (operand.GetImmediate() != 0);
1996        if (can_be_16bit_encoded) {
1997          Lsls(cond, rd, rm, operand);
1998        } else {
1999          Lsl(cond, rd, rm, operand);
2000        }
2001        break;
2002    }
2003  }
2004  void Lsl(FlagsUpdate flags,
2005           Register rd,
2006           Register rm,
2007           const Operand& operand) {
2008    Lsl(flags, al, rd, rm, operand);
2009  }
2010
2011  void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) {
2012    VIXL_ASSERT(allow_macro_instructions_);
2013    VIXL_ASSERT(OutsideITBlock());
2014    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2015    ITScope it_scope(this, &cond);
2016    lsls(cond, rd, rm, operand);
2017  }
2018  void Lsls(Register rd, Register rm, const Operand& operand) {
2019    Lsls(al, rd, rm, operand);
2020  }
2021
2022  void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) {
2023    VIXL_ASSERT(allow_macro_instructions_);
2024    VIXL_ASSERT(OutsideITBlock());
2025    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2026    bool can_use_it =
2027        // LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
2028        (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
2029         (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
2030        // LSR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1
2031        (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2032         operand.GetBaseRegister().IsLow());
2033    ITScope it_scope(this, &cond, can_use_it);
2034    lsr(cond, rd, rm, operand);
2035  }
2036  void Lsr(Register rd, Register rm, const Operand& operand) {
2037    Lsr(al, rd, rm, operand);
2038  }
2039  void Lsr(FlagsUpdate flags,
2040           Condition cond,
2041           Register rd,
2042           Register rm,
2043           const Operand& operand) {
2044    switch (flags) {
2045      case LeaveFlags:
2046        Lsr(cond, rd, rm, operand);
2047        break;
2048      case SetFlags:
2049        Lsrs(cond, rd, rm, operand);
2050        break;
2051      case DontCare:
2052        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2053                                    rm.IsLow() && operand.IsImmediate() &&
2054                                    (operand.GetImmediate() < 32);
2055        if (can_be_16bit_encoded) {
2056          Lsrs(cond, rd, rm, operand);
2057        } else {
2058          Lsr(cond, rd, rm, operand);
2059        }
2060        break;
2061    }
2062  }
2063  void Lsr(FlagsUpdate flags,
2064           Register rd,
2065           Register rm,
2066           const Operand& operand) {
2067    Lsr(flags, al, rd, rm, operand);
2068  }
2069
2070  void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) {
2071    VIXL_ASSERT(allow_macro_instructions_);
2072    VIXL_ASSERT(OutsideITBlock());
2073    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2074    ITScope it_scope(this, &cond);
2075    lsrs(cond, rd, rm, operand);
2076  }
2077  void Lsrs(Register rd, Register rm, const Operand& operand) {
2078    Lsrs(al, rd, rm, operand);
2079  }
2080
2081  void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) {
2082    VIXL_ASSERT(allow_macro_instructions_);
2083    VIXL_ASSERT(OutsideITBlock());
2084    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2085    ITScope it_scope(this, &cond);
2086    mla(cond, rd, rn, rm, ra);
2087  }
2088  void Mla(Register rd, Register rn, Register rm, Register ra) {
2089    Mla(al, rd, rn, rm, ra);
2090  }
2091  void Mla(FlagsUpdate flags,
2092           Condition cond,
2093           Register rd,
2094           Register rn,
2095           Register rm,
2096           Register ra) {
2097    switch (flags) {
2098      case LeaveFlags:
2099        Mla(cond, rd, rn, rm, ra);
2100        break;
2101      case SetFlags:
2102        Mlas(cond, rd, rn, rm, ra);
2103        break;
2104      case DontCare:
2105        Mla(cond, rd, rn, rm, ra);
2106        break;
2107    }
2108  }
2109  void Mla(
2110      FlagsUpdate flags, Register rd, Register rn, Register rm, Register ra) {
2111    Mla(flags, al, rd, rn, rm, ra);
2112  }
2113
2114  void Mlas(
2115      Condition cond, Register rd, Register rn, Register rm, Register ra) {
2116    VIXL_ASSERT(allow_macro_instructions_);
2117    VIXL_ASSERT(OutsideITBlock());
2118    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2119    ITScope it_scope(this, &cond);
2120    mlas(cond, rd, rn, rm, ra);
2121  }
2122  void Mlas(Register rd, Register rn, Register rm, Register ra) {
2123    Mlas(al, rd, rn, rm, ra);
2124  }
2125
2126  void Mls(Condition cond, Register rd, Register rn, Register rm, Register ra) {
2127    VIXL_ASSERT(allow_macro_instructions_);
2128    VIXL_ASSERT(OutsideITBlock());
2129    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2130    ITScope it_scope(this, &cond);
2131    mls(cond, rd, rn, rm, ra);
2132  }
2133  void Mls(Register rd, Register rn, Register rm, Register ra) {
2134    Mls(al, rd, rn, rm, ra);
2135  }
2136
2137  void Mov(Condition cond, Register rd, const Operand& operand) {
2138    VIXL_ASSERT(allow_macro_instructions_);
2139    VIXL_ASSERT(OutsideITBlock());
2140    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2141    bool can_use_it =
2142        // MOV<c>{<q>} <Rd>, #<imm8> ; T1
2143        (operand.IsImmediate() && rd.IsLow() &&
2144         (operand.GetImmediate() <= 255)) ||
2145        // MOV{<c>}{<q>} <Rd>, <Rm> ; T1
2146        (operand.IsPlainRegister() && !rd.IsPC() &&
2147         !operand.GetBaseRegister().IsPC()) ||
2148        // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} ; T2
2149        (operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2150         operand.GetBaseRegister().IsLow() &&
2151         (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) ||
2152          operand.GetShift().Is(ASR))) ||
2153        // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
2154        // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
2155        // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
2156        // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
2157        (operand.IsRegisterShiftedRegister() &&
2158         rd.Is(operand.GetBaseRegister()) && rd.IsLow() &&
2159         (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) ||
2160          operand.GetShift().Is(ASR) || operand.GetShift().Is(ROR)) &&
2161         operand.GetShiftRegister().IsLow());
2162    ITScope it_scope(this, &cond, can_use_it);
2163    mov(cond, rd, operand);
2164  }
2165  void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); }
2166  void Mov(FlagsUpdate flags,
2167           Condition cond,
2168           Register rd,
2169           const Operand& operand) {
2170    switch (flags) {
2171      case LeaveFlags:
2172        Mov(cond, rd, operand);
2173        break;
2174      case SetFlags:
2175        Movs(cond, rd, operand);
2176        break;
2177      case DontCare:
2178        bool can_be_16bit_encoded =
2179            IsUsingT32() && cond.Is(al) &&
2180            ((operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2181              operand.GetBaseRegister().IsLow() &&
2182              (operand.GetShiftAmount() < 32) &&
2183              (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() ||
2184               operand.GetShift().IsASR())) ||
2185             (operand.IsRegisterShiftedRegister() && rd.IsLow() &&
2186              operand.GetBaseRegister().Is(rd) &&
2187              operand.GetShiftRegister().IsLow() &&
2188              (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() ||
2189               operand.GetShift().IsASR() || operand.GetShift().IsROR())) ||
2190             (operand.IsImmediate() && rd.IsLow() &&
2191              (operand.GetImmediate() < 256)));
2192        if (can_be_16bit_encoded) {
2193          Movs(cond, rd, operand);
2194        } else {
2195          Mov(cond, rd, operand);
2196        }
2197        break;
2198    }
2199  }
2200  void Mov(FlagsUpdate flags, Register rd, const Operand& operand) {
2201    Mov(flags, al, rd, operand);
2202  }
2203
2204  void Movs(Condition cond, Register rd, const Operand& operand) {
2205    VIXL_ASSERT(allow_macro_instructions_);
2206    VIXL_ASSERT(OutsideITBlock());
2207    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2208    ITScope it_scope(this, &cond);
2209    movs(cond, rd, operand);
2210  }
2211  void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); }
2212
2213  void Movt(Condition cond, Register rd, const Operand& operand) {
2214    VIXL_ASSERT(allow_macro_instructions_);
2215    VIXL_ASSERT(OutsideITBlock());
2216    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2217    ITScope it_scope(this, &cond);
2218    movt(cond, rd, operand);
2219  }
2220  void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); }
2221
2222  void Movw(Condition cond, Register rd, const Operand& operand) {
2223    VIXL_ASSERT(allow_macro_instructions_);
2224    VIXL_ASSERT(OutsideITBlock());
2225    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2226    ITScope it_scope(this, &cond);
2227    movw(cond, rd, operand);
2228  }
2229  void Movw(Register rd, const Operand& operand) { Movw(al, rd, operand); }
2230
2231  void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) {
2232    VIXL_ASSERT(allow_macro_instructions_);
2233    VIXL_ASSERT(OutsideITBlock());
2234    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2235    ITScope it_scope(this, &cond);
2236    mrs(cond, rd, spec_reg);
2237  }
2238  void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); }
2239
2240  void Msr(Condition cond,
2241           MaskedSpecialRegister spec_reg,
2242           const Operand& operand) {
2243    VIXL_ASSERT(allow_macro_instructions_);
2244    VIXL_ASSERT(OutsideITBlock());
2245    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2246    ITScope it_scope(this, &cond);
2247    msr(cond, spec_reg, operand);
2248  }
2249  void Msr(MaskedSpecialRegister spec_reg, const Operand& operand) {
2250    Msr(al, spec_reg, operand);
2251  }
2252
2253  void Mul(Condition cond, Register rd, Register rn, Register rm) {
2254    VIXL_ASSERT(allow_macro_instructions_);
2255    VIXL_ASSERT(OutsideITBlock());
2256    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2257    bool can_use_it =
2258        // MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>} ; T1
2259        rd.Is(rm) && rn.IsLow() && rm.IsLow();
2260    ITScope it_scope(this, &cond, can_use_it);
2261    mul(cond, rd, rn, rm);
2262  }
2263  void Mul(Register rd, Register rn, Register rm) { Mul(al, rd, rn, rm); }
2264  void Mul(FlagsUpdate flags,
2265           Condition cond,
2266           Register rd,
2267           Register rn,
2268           Register rm) {
2269    switch (flags) {
2270      case LeaveFlags:
2271        Mul(cond, rd, rn, rm);
2272        break;
2273      case SetFlags:
2274        Muls(cond, rd, rn, rm);
2275        break;
2276      case DontCare:
2277        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2278                                    rn.IsLow() && rm.Is(rd);
2279        if (can_be_16bit_encoded) {
2280          Muls(cond, rd, rn, rm);
2281        } else {
2282          Mul(cond, rd, rn, rm);
2283        }
2284        break;
2285    }
2286  }
2287  void Mul(FlagsUpdate flags, Register rd, Register rn, Register rm) {
2288    Mul(flags, al, rd, rn, rm);
2289  }
2290
2291  void Muls(Condition cond, Register rd, Register rn, Register rm) {
2292    VIXL_ASSERT(allow_macro_instructions_);
2293    VIXL_ASSERT(OutsideITBlock());
2294    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2295    ITScope it_scope(this, &cond);
2296    muls(cond, rd, rn, rm);
2297  }
2298  void Muls(Register rd, Register rn, Register rm) { Muls(al, rd, rn, rm); }
2299
2300  void Mvn(Condition cond, Register rd, const Operand& operand) {
2301    VIXL_ASSERT(allow_macro_instructions_);
2302    VIXL_ASSERT(OutsideITBlock());
2303    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2304    bool can_use_it =
2305        // MVN<c>{<q>} <Rd>, <Rm> ; T1
2306        operand.IsPlainRegister() && rd.IsLow() &&
2307        operand.GetBaseRegister().IsLow();
2308    ITScope it_scope(this, &cond, can_use_it);
2309    mvn(cond, rd, operand);
2310  }
2311  void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); }
2312  void Mvn(FlagsUpdate flags,
2313           Condition cond,
2314           Register rd,
2315           const Operand& operand) {
2316    switch (flags) {
2317      case LeaveFlags:
2318        Mvn(cond, rd, operand);
2319        break;
2320      case SetFlags:
2321        Mvns(cond, rd, operand);
2322        break;
2323      case DontCare:
2324        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2325                                    operand.IsPlainRegister() &&
2326                                    operand.GetBaseRegister().IsLow();
2327        if (can_be_16bit_encoded) {
2328          Mvns(cond, rd, operand);
2329        } else {
2330          Mvn(cond, rd, operand);
2331        }
2332        break;
2333    }
2334  }
2335  void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) {
2336    Mvn(flags, al, rd, operand);
2337  }
2338
2339  void Mvns(Condition cond, Register rd, const Operand& operand) {
2340    VIXL_ASSERT(allow_macro_instructions_);
2341    VIXL_ASSERT(OutsideITBlock());
2342    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2343    ITScope it_scope(this, &cond);
2344    mvns(cond, rd, operand);
2345  }
2346  void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); }
2347
2348  void Nop(Condition cond) {
2349    VIXL_ASSERT(allow_macro_instructions_);
2350    VIXL_ASSERT(OutsideITBlock());
2351    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2352    ITScope it_scope(this, &cond);
2353    nop(cond);
2354  }
2355  void Nop() { Nop(al); }
2356
2357  void Orn(Condition cond, Register rd, Register rn, const Operand& operand) {
2358    VIXL_ASSERT(allow_macro_instructions_);
2359    VIXL_ASSERT(OutsideITBlock());
2360    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2361    if (cond.Is(al) && operand.IsImmediate()) {
2362      uint32_t immediate = operand.GetImmediate();
2363      if (immediate == 0) {
2364        mvn(rd, 0);
2365        return;
2366      }
2367      if ((immediate == 0xffffffff) && rd.Is(rn)) {
2368        return;
2369      }
2370    }
2371    ITScope it_scope(this, &cond);
2372    orn(cond, rd, rn, operand);
2373  }
2374  void Orn(Register rd, Register rn, const Operand& operand) {
2375    Orn(al, rd, rn, operand);
2376  }
2377  void Orn(FlagsUpdate flags,
2378           Condition cond,
2379           Register rd,
2380           Register rn,
2381           const Operand& operand) {
2382    switch (flags) {
2383      case LeaveFlags:
2384        Orn(cond, rd, rn, operand);
2385        break;
2386      case SetFlags:
2387        Orns(cond, rd, rn, operand);
2388        break;
2389      case DontCare:
2390        Orn(cond, rd, rn, operand);
2391        break;
2392    }
2393  }
2394  void Orn(FlagsUpdate flags,
2395           Register rd,
2396           Register rn,
2397           const Operand& operand) {
2398    Orn(flags, al, rd, rn, operand);
2399  }
2400
2401  void Orns(Condition cond, Register rd, Register rn, const Operand& operand) {
2402    VIXL_ASSERT(allow_macro_instructions_);
2403    VIXL_ASSERT(OutsideITBlock());
2404    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2405    ITScope it_scope(this, &cond);
2406    orns(cond, rd, rn, operand);
2407  }
2408  void Orns(Register rd, Register rn, const Operand& operand) {
2409    Orns(al, rd, rn, operand);
2410  }
2411
2412  void Orr(Condition cond, Register rd, Register rn, const Operand& operand) {
2413    VIXL_ASSERT(allow_macro_instructions_);
2414    VIXL_ASSERT(OutsideITBlock());
2415    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2416    if (cond.Is(al) && operand.IsImmediate()) {
2417      uint32_t immediate = operand.GetImmediate();
2418      if ((immediate == 0) && rd.Is(rn)) {
2419        return;
2420      }
2421      if (immediate == 0xffffffff) {
2422        mvn(rd, 0);
2423        return;
2424      }
2425    }
2426    bool can_use_it =
2427        // ORR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1
2428        operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
2429        operand.GetBaseRegister().IsLow();
2430    ITScope it_scope(this, &cond, can_use_it);
2431    orr(cond, rd, rn, operand);
2432  }
2433  void Orr(Register rd, Register rn, const Operand& operand) {
2434    Orr(al, rd, rn, operand);
2435  }
2436  void Orr(FlagsUpdate flags,
2437           Condition cond,
2438           Register rd,
2439           Register rn,
2440           const Operand& operand) {
2441    switch (flags) {
2442      case LeaveFlags:
2443        Orr(cond, rd, rn, operand);
2444        break;
2445      case SetFlags:
2446        Orrs(cond, rd, rn, operand);
2447        break;
2448      case DontCare:
2449        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2450                                    rn.Is(rd) && operand.IsPlainRegister() &&
2451                                    operand.GetBaseRegister().IsLow();
2452        if (can_be_16bit_encoded) {
2453          Orrs(cond, rd, rn, operand);
2454        } else {
2455          Orr(cond, rd, rn, operand);
2456        }
2457        break;
2458    }
2459  }
2460  void Orr(FlagsUpdate flags,
2461           Register rd,
2462           Register rn,
2463           const Operand& operand) {
2464    Orr(flags, al, rd, rn, operand);
2465  }
2466
2467  void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) {
2468    VIXL_ASSERT(allow_macro_instructions_);
2469    VIXL_ASSERT(OutsideITBlock());
2470    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2471    ITScope it_scope(this, &cond);
2472    orrs(cond, rd, rn, operand);
2473  }
2474  void Orrs(Register rd, Register rn, const Operand& operand) {
2475    Orrs(al, rd, rn, operand);
2476  }
2477
2478  void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) {
2479    VIXL_ASSERT(allow_macro_instructions_);
2480    VIXL_ASSERT(OutsideITBlock());
2481    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2482    ITScope it_scope(this, &cond);
2483    pkhbt(cond, rd, rn, operand);
2484  }
2485  void Pkhbt(Register rd, Register rn, const Operand& operand) {
2486    Pkhbt(al, rd, rn, operand);
2487  }
2488
2489  void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) {
2490    VIXL_ASSERT(allow_macro_instructions_);
2491    VIXL_ASSERT(OutsideITBlock());
2492    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2493    ITScope it_scope(this, &cond);
2494    pkhtb(cond, rd, rn, operand);
2495  }
2496  void Pkhtb(Register rd, Register rn, const Operand& operand) {
2497    Pkhtb(al, rd, rn, operand);
2498  }
2499
2500  void Pld(Condition cond, Label* label) {
2501    VIXL_ASSERT(allow_macro_instructions_);
2502    VIXL_ASSERT(OutsideITBlock());
2503    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2504    ITScope it_scope(this, &cond);
2505    pld(cond, label);
2506  }
2507  void Pld(Label* label) { Pld(al, label); }
2508
2509  void Pld(Condition cond, const MemOperand& operand) {
2510    VIXL_ASSERT(allow_macro_instructions_);
2511    VIXL_ASSERT(OutsideITBlock());
2512    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2513    ITScope it_scope(this, &cond);
2514    pld(cond, operand);
2515  }
2516  void Pld(const MemOperand& operand) { Pld(al, operand); }
2517
2518  void Pldw(Condition cond, const MemOperand& operand) {
2519    VIXL_ASSERT(allow_macro_instructions_);
2520    VIXL_ASSERT(OutsideITBlock());
2521    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2522    ITScope it_scope(this, &cond);
2523    pldw(cond, operand);
2524  }
2525  void Pldw(const MemOperand& operand) { Pldw(al, operand); }
2526
2527  void Pli(Condition cond, const MemOperand& operand) {
2528    VIXL_ASSERT(allow_macro_instructions_);
2529    VIXL_ASSERT(OutsideITBlock());
2530    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2531    ITScope it_scope(this, &cond);
2532    pli(cond, operand);
2533  }
2534  void Pli(const MemOperand& operand) { Pli(al, operand); }
2535
2536  void Pli(Condition cond, Label* label) {
2537    VIXL_ASSERT(allow_macro_instructions_);
2538    VIXL_ASSERT(OutsideITBlock());
2539    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2540    ITScope it_scope(this, &cond);
2541    pli(cond, label);
2542  }
2543  void Pli(Label* label) { Pli(al, label); }
2544
2545  void Pop(Condition cond, RegisterList registers) {
2546    VIXL_ASSERT(allow_macro_instructions_);
2547    VIXL_ASSERT(OutsideITBlock());
2548    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2549    ITScope it_scope(this, &cond);
2550    pop(cond, registers);
2551  }
2552  void Pop(RegisterList registers) { Pop(al, registers); }
2553
2554  void Pop(Condition cond, Register rt) {
2555    VIXL_ASSERT(allow_macro_instructions_);
2556    VIXL_ASSERT(OutsideITBlock());
2557    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2558    ITScope it_scope(this, &cond);
2559    pop(cond, rt);
2560  }
2561  void Pop(Register rt) { Pop(al, rt); }
2562
2563  void Push(Condition cond, RegisterList registers) {
2564    VIXL_ASSERT(allow_macro_instructions_);
2565    VIXL_ASSERT(OutsideITBlock());
2566    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2567    ITScope it_scope(this, &cond);
2568    push(cond, registers);
2569  }
2570  void Push(RegisterList registers) { Push(al, registers); }
2571
2572  void Push(Condition cond, Register rt) {
2573    VIXL_ASSERT(allow_macro_instructions_);
2574    VIXL_ASSERT(OutsideITBlock());
2575    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2576    ITScope it_scope(this, &cond);
2577    push(cond, rt);
2578  }
2579  void Push(Register rt) { Push(al, rt); }
2580
2581  void Qadd(Condition cond, Register rd, Register rm, Register rn) {
2582    VIXL_ASSERT(allow_macro_instructions_);
2583    VIXL_ASSERT(OutsideITBlock());
2584    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2585    ITScope it_scope(this, &cond);
2586    qadd(cond, rd, rm, rn);
2587  }
2588  void Qadd(Register rd, Register rm, Register rn) { Qadd(al, rd, rm, rn); }
2589
2590  void Qadd16(Condition cond, Register rd, Register rn, Register rm) {
2591    VIXL_ASSERT(allow_macro_instructions_);
2592    VIXL_ASSERT(OutsideITBlock());
2593    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2594    ITScope it_scope(this, &cond);
2595    qadd16(cond, rd, rn, rm);
2596  }
2597  void Qadd16(Register rd, Register rn, Register rm) { Qadd16(al, rd, rn, rm); }
2598
2599  void Qadd8(Condition cond, Register rd, Register rn, Register rm) {
2600    VIXL_ASSERT(allow_macro_instructions_);
2601    VIXL_ASSERT(OutsideITBlock());
2602    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2603    ITScope it_scope(this, &cond);
2604    qadd8(cond, rd, rn, rm);
2605  }
2606  void Qadd8(Register rd, Register rn, Register rm) { Qadd8(al, rd, rn, rm); }
2607
2608  void Qasx(Condition cond, Register rd, Register rn, Register rm) {
2609    VIXL_ASSERT(allow_macro_instructions_);
2610    VIXL_ASSERT(OutsideITBlock());
2611    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2612    ITScope it_scope(this, &cond);
2613    qasx(cond, rd, rn, rm);
2614  }
2615  void Qasx(Register rd, Register rn, Register rm) { Qasx(al, rd, rn, rm); }
2616
2617  void Qdadd(Condition cond, Register rd, Register rm, Register rn) {
2618    VIXL_ASSERT(allow_macro_instructions_);
2619    VIXL_ASSERT(OutsideITBlock());
2620    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2621    ITScope it_scope(this, &cond);
2622    qdadd(cond, rd, rm, rn);
2623  }
2624  void Qdadd(Register rd, Register rm, Register rn) { Qdadd(al, rd, rm, rn); }
2625
2626  void Qdsub(Condition cond, Register rd, Register rm, Register rn) {
2627    VIXL_ASSERT(allow_macro_instructions_);
2628    VIXL_ASSERT(OutsideITBlock());
2629    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2630    ITScope it_scope(this, &cond);
2631    qdsub(cond, rd, rm, rn);
2632  }
2633  void Qdsub(Register rd, Register rm, Register rn) { Qdsub(al, rd, rm, rn); }
2634
2635  void Qsax(Condition cond, Register rd, Register rn, Register rm) {
2636    VIXL_ASSERT(allow_macro_instructions_);
2637    VIXL_ASSERT(OutsideITBlock());
2638    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2639    ITScope it_scope(this, &cond);
2640    qsax(cond, rd, rn, rm);
2641  }
2642  void Qsax(Register rd, Register rn, Register rm) { Qsax(al, rd, rn, rm); }
2643
2644  void Qsub(Condition cond, Register rd, Register rm, Register rn) {
2645    VIXL_ASSERT(allow_macro_instructions_);
2646    VIXL_ASSERT(OutsideITBlock());
2647    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2648    ITScope it_scope(this, &cond);
2649    qsub(cond, rd, rm, rn);
2650  }
2651  void Qsub(Register rd, Register rm, Register rn) { Qsub(al, rd, rm, rn); }
2652
2653  void Qsub16(Condition cond, Register rd, Register rn, Register rm) {
2654    VIXL_ASSERT(allow_macro_instructions_);
2655    VIXL_ASSERT(OutsideITBlock());
2656    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2657    ITScope it_scope(this, &cond);
2658    qsub16(cond, rd, rn, rm);
2659  }
2660  void Qsub16(Register rd, Register rn, Register rm) { Qsub16(al, rd, rn, rm); }
2661
2662  void Qsub8(Condition cond, Register rd, Register rn, Register rm) {
2663    VIXL_ASSERT(allow_macro_instructions_);
2664    VIXL_ASSERT(OutsideITBlock());
2665    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2666    ITScope it_scope(this, &cond);
2667    qsub8(cond, rd, rn, rm);
2668  }
2669  void Qsub8(Register rd, Register rn, Register rm) { Qsub8(al, rd, rn, rm); }
2670
2671  void Rbit(Condition cond, Register rd, Register rm) {
2672    VIXL_ASSERT(allow_macro_instructions_);
2673    VIXL_ASSERT(OutsideITBlock());
2674    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2675    ITScope it_scope(this, &cond);
2676    rbit(cond, rd, rm);
2677  }
2678  void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); }
2679
2680  void Rev(Condition cond, Register rd, Register rm) {
2681    VIXL_ASSERT(allow_macro_instructions_);
2682    VIXL_ASSERT(OutsideITBlock());
2683    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2684    ITScope it_scope(this, &cond);
2685    rev(cond, rd, rm);
2686  }
2687  void Rev(Register rd, Register rm) { Rev(al, rd, rm); }
2688
2689  void Rev16(Condition cond, Register rd, Register rm) {
2690    VIXL_ASSERT(allow_macro_instructions_);
2691    VIXL_ASSERT(OutsideITBlock());
2692    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2693    ITScope it_scope(this, &cond);
2694    rev16(cond, rd, rm);
2695  }
2696  void Rev16(Register rd, Register rm) { Rev16(al, rd, rm); }
2697
2698  void Revsh(Condition cond, Register rd, Register rm) {
2699    VIXL_ASSERT(allow_macro_instructions_);
2700    VIXL_ASSERT(OutsideITBlock());
2701    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2702    ITScope it_scope(this, &cond);
2703    revsh(cond, rd, rm);
2704  }
2705  void Revsh(Register rd, Register rm) { Revsh(al, rd, rm); }
2706
2707  void Ror(Condition cond, Register rd, Register rm, const Operand& operand) {
2708    VIXL_ASSERT(allow_macro_instructions_);
2709    VIXL_ASSERT(OutsideITBlock());
2710    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2711    bool can_use_it =
2712        // ROR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
2713        (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
2714         (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) ||
2715        // ROR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1
2716        (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2717         operand.GetBaseRegister().IsLow());
2718    ITScope it_scope(this, &cond, can_use_it);
2719    ror(cond, rd, rm, operand);
2720  }
2721  void Ror(Register rd, Register rm, const Operand& operand) {
2722    Ror(al, rd, rm, operand);
2723  }
2724  void Ror(FlagsUpdate flags,
2725           Condition cond,
2726           Register rd,
2727           Register rm,
2728           const Operand& operand) {
2729    switch (flags) {
2730      case LeaveFlags:
2731        Ror(cond, rd, rm, operand);
2732        break;
2733      case SetFlags:
2734        Rors(cond, rd, rm, operand);
2735        break;
2736      case DontCare:
2737        Ror(cond, rd, rm, operand);
2738        break;
2739    }
2740  }
2741  void Ror(FlagsUpdate flags,
2742           Register rd,
2743           Register rm,
2744           const Operand& operand) {
2745    Ror(flags, al, rd, rm, operand);
2746  }
2747
2748  void Rors(Condition cond, Register rd, Register rm, const Operand& operand) {
2749    VIXL_ASSERT(allow_macro_instructions_);
2750    VIXL_ASSERT(OutsideITBlock());
2751    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2752    ITScope it_scope(this, &cond);
2753    rors(cond, rd, rm, operand);
2754  }
2755  void Rors(Register rd, Register rm, const Operand& operand) {
2756    Rors(al, rd, rm, operand);
2757  }
2758
2759  void Rrx(Condition cond, Register rd, Register rm) {
2760    VIXL_ASSERT(allow_macro_instructions_);
2761    VIXL_ASSERT(OutsideITBlock());
2762    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2763    ITScope it_scope(this, &cond);
2764    rrx(cond, rd, rm);
2765  }
2766  void Rrx(Register rd, Register rm) { Rrx(al, rd, rm); }
2767  void Rrx(FlagsUpdate flags, Condition cond, Register rd, Register rm) {
2768    switch (flags) {
2769      case LeaveFlags:
2770        Rrx(cond, rd, rm);
2771        break;
2772      case SetFlags:
2773        Rrxs(cond, rd, rm);
2774        break;
2775      case DontCare:
2776        Rrx(cond, rd, rm);
2777        break;
2778    }
2779  }
2780  void Rrx(FlagsUpdate flags, Register rd, Register rm) {
2781    Rrx(flags, al, rd, rm);
2782  }
2783
2784  void Rrxs(Condition cond, Register rd, Register rm) {
2785    VIXL_ASSERT(allow_macro_instructions_);
2786    VIXL_ASSERT(OutsideITBlock());
2787    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2788    ITScope it_scope(this, &cond);
2789    rrxs(cond, rd, rm);
2790  }
2791  void Rrxs(Register rd, Register rm) { Rrxs(al, rd, rm); }
2792
2793  void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) {
2794    VIXL_ASSERT(allow_macro_instructions_);
2795    VIXL_ASSERT(OutsideITBlock());
2796    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2797    bool can_use_it =
2798        // RSB<c>{<q>} {<Rd>, }<Rn>, #0 ; T1
2799        operand.IsImmediate() && rd.IsLow() && rn.IsLow() &&
2800        (operand.GetImmediate() == 0);
2801    ITScope it_scope(this, &cond, can_use_it);
2802    rsb(cond, rd, rn, operand);
2803  }
2804  void Rsb(Register rd, Register rn, const Operand& operand) {
2805    Rsb(al, rd, rn, operand);
2806  }
2807  void Rsb(FlagsUpdate flags,
2808           Condition cond,
2809           Register rd,
2810           Register rn,
2811           const Operand& operand) {
2812    switch (flags) {
2813      case LeaveFlags:
2814        Rsb(cond, rd, rn, operand);
2815        break;
2816      case SetFlags:
2817        Rsbs(cond, rd, rn, operand);
2818        break;
2819      case DontCare:
2820        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2821                                    rn.IsLow() && operand.IsImmediate() &&
2822                                    (operand.GetImmediate() == 0);
2823        if (can_be_16bit_encoded) {
2824          Rsbs(cond, rd, rn, operand);
2825        } else {
2826          Rsb(cond, rd, rn, operand);
2827        }
2828        break;
2829    }
2830  }
2831  void Rsb(FlagsUpdate flags,
2832           Register rd,
2833           Register rn,
2834           const Operand& operand) {
2835    Rsb(flags, al, rd, rn, operand);
2836  }
2837
2838  void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) {
2839    VIXL_ASSERT(allow_macro_instructions_);
2840    VIXL_ASSERT(OutsideITBlock());
2841    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2842    ITScope it_scope(this, &cond);
2843    rsbs(cond, rd, rn, operand);
2844  }
2845  void Rsbs(Register rd, Register rn, const Operand& operand) {
2846    Rsbs(al, rd, rn, operand);
2847  }
2848
2849  void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) {
2850    VIXL_ASSERT(allow_macro_instructions_);
2851    VIXL_ASSERT(OutsideITBlock());
2852    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2853    ITScope it_scope(this, &cond);
2854    rsc(cond, rd, rn, operand);
2855  }
2856  void Rsc(Register rd, Register rn, const Operand& operand) {
2857    Rsc(al, rd, rn, operand);
2858  }
2859  void Rsc(FlagsUpdate flags,
2860           Condition cond,
2861           Register rd,
2862           Register rn,
2863           const Operand& operand) {
2864    switch (flags) {
2865      case LeaveFlags:
2866        Rsc(cond, rd, rn, operand);
2867        break;
2868      case SetFlags:
2869        Rscs(cond, rd, rn, operand);
2870        break;
2871      case DontCare:
2872        Rsc(cond, rd, rn, operand);
2873        break;
2874    }
2875  }
2876  void Rsc(FlagsUpdate flags,
2877           Register rd,
2878           Register rn,
2879           const Operand& operand) {
2880    Rsc(flags, al, rd, rn, operand);
2881  }
2882
2883  void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) {
2884    VIXL_ASSERT(allow_macro_instructions_);
2885    VIXL_ASSERT(OutsideITBlock());
2886    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2887    ITScope it_scope(this, &cond);
2888    rscs(cond, rd, rn, operand);
2889  }
2890  void Rscs(Register rd, Register rn, const Operand& operand) {
2891    Rscs(al, rd, rn, operand);
2892  }
2893
2894  void Sadd16(Condition cond, Register rd, Register rn, Register rm) {
2895    VIXL_ASSERT(allow_macro_instructions_);
2896    VIXL_ASSERT(OutsideITBlock());
2897    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2898    ITScope it_scope(this, &cond);
2899    sadd16(cond, rd, rn, rm);
2900  }
2901  void Sadd16(Register rd, Register rn, Register rm) { Sadd16(al, rd, rn, rm); }
2902
2903  void Sadd8(Condition cond, Register rd, Register rn, Register rm) {
2904    VIXL_ASSERT(allow_macro_instructions_);
2905    VIXL_ASSERT(OutsideITBlock());
2906    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2907    ITScope it_scope(this, &cond);
2908    sadd8(cond, rd, rn, rm);
2909  }
2910  void Sadd8(Register rd, Register rn, Register rm) { Sadd8(al, rd, rn, rm); }
2911
2912  void Sasx(Condition cond, Register rd, Register rn, Register rm) {
2913    VIXL_ASSERT(allow_macro_instructions_);
2914    VIXL_ASSERT(OutsideITBlock());
2915    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2916    ITScope it_scope(this, &cond);
2917    sasx(cond, rd, rn, rm);
2918  }
2919  void Sasx(Register rd, Register rn, Register rm) { Sasx(al, rd, rn, rm); }
2920
2921  void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) {
2922    VIXL_ASSERT(allow_macro_instructions_);
2923    VIXL_ASSERT(OutsideITBlock());
2924    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2925    bool can_use_it =
2926        // SBC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1
2927        operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
2928        operand.GetBaseRegister().IsLow();
2929    ITScope it_scope(this, &cond, can_use_it);
2930    sbc(cond, rd, rn, operand);
2931  }
2932  void Sbc(Register rd, Register rn, const Operand& operand) {
2933    Sbc(al, rd, rn, operand);
2934  }
2935  void Sbc(FlagsUpdate flags,
2936           Condition cond,
2937           Register rd,
2938           Register rn,
2939           const Operand& operand) {
2940    switch (flags) {
2941      case LeaveFlags:
2942        Sbc(cond, rd, rn, operand);
2943        break;
2944      case SetFlags:
2945        Sbcs(cond, rd, rn, operand);
2946        break;
2947      case DontCare:
2948        bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2949                                    rn.Is(rd) && operand.IsPlainRegister() &&
2950                                    operand.GetBaseRegister().IsLow();
2951        if (can_be_16bit_encoded) {
2952          Sbcs(cond, rd, rn, operand);
2953        } else {
2954          Sbc(cond, rd, rn, operand);
2955        }
2956        break;
2957    }
2958  }
2959  void Sbc(FlagsUpdate flags,
2960           Register rd,
2961           Register rn,
2962           const Operand& operand) {
2963    Sbc(flags, al, rd, rn, operand);
2964  }
2965
2966  void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) {
2967    VIXL_ASSERT(allow_macro_instructions_);
2968    VIXL_ASSERT(OutsideITBlock());
2969    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2970    ITScope it_scope(this, &cond);
2971    sbcs(cond, rd, rn, operand);
2972  }
2973  void Sbcs(Register rd, Register rn, const Operand& operand) {
2974    Sbcs(al, rd, rn, operand);
2975  }
2976
2977  void Sbfx(Condition cond,
2978            Register rd,
2979            Register rn,
2980            uint32_t lsb,
2981            const Operand& operand) {
2982    VIXL_ASSERT(allow_macro_instructions_);
2983    VIXL_ASSERT(OutsideITBlock());
2984    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2985    ITScope it_scope(this, &cond);
2986    sbfx(cond, rd, rn, lsb, operand);
2987  }
2988  void Sbfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) {
2989    Sbfx(al, rd, rn, lsb, operand);
2990  }
2991
2992  void Sdiv(Condition cond, Register rd, Register rn, Register rm) {
2993    VIXL_ASSERT(allow_macro_instructions_);
2994    VIXL_ASSERT(OutsideITBlock());
2995    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
2996    ITScope it_scope(this, &cond);
2997    sdiv(cond, rd, rn, rm);
2998  }
2999  void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); }
3000
3001  void Sel(Condition cond, Register rd, Register rn, Register rm) {
3002    VIXL_ASSERT(allow_macro_instructions_);
3003    VIXL_ASSERT(OutsideITBlock());
3004    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3005    ITScope it_scope(this, &cond);
3006    sel(cond, rd, rn, rm);
3007  }
3008  void Sel(Register rd, Register rn, Register rm) { Sel(al, rd, rn, rm); }
3009
3010  void Shadd16(Condition cond, Register rd, Register rn, Register rm) {
3011    VIXL_ASSERT(allow_macro_instructions_);
3012    VIXL_ASSERT(OutsideITBlock());
3013    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3014    ITScope it_scope(this, &cond);
3015    shadd16(cond, rd, rn, rm);
3016  }
3017  void Shadd16(Register rd, Register rn, Register rm) {
3018    Shadd16(al, rd, rn, rm);
3019  }
3020
3021  void Shadd8(Condition cond, Register rd, Register rn, Register rm) {
3022    VIXL_ASSERT(allow_macro_instructions_);
3023    VIXL_ASSERT(OutsideITBlock());
3024    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3025    ITScope it_scope(this, &cond);
3026    shadd8(cond, rd, rn, rm);
3027  }
3028  void Shadd8(Register rd, Register rn, Register rm) { Shadd8(al, rd, rn, rm); }
3029
3030  void Shasx(Condition cond, Register rd, Register rn, Register rm) {
3031    VIXL_ASSERT(allow_macro_instructions_);
3032    VIXL_ASSERT(OutsideITBlock());
3033    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3034    ITScope it_scope(this, &cond);
3035    shasx(cond, rd, rn, rm);
3036  }
3037  void Shasx(Register rd, Register rn, Register rm) { Shasx(al, rd, rn, rm); }
3038
3039  void Shsax(Condition cond, Register rd, Register rn, Register rm) {
3040    VIXL_ASSERT(allow_macro_instructions_);
3041    VIXL_ASSERT(OutsideITBlock());
3042    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3043    ITScope it_scope(this, &cond);
3044    shsax(cond, rd, rn, rm);
3045  }
3046  void Shsax(Register rd, Register rn, Register rm) { Shsax(al, rd, rn, rm); }
3047
3048  void Shsub16(Condition cond, Register rd, Register rn, Register rm) {
3049    VIXL_ASSERT(allow_macro_instructions_);
3050    VIXL_ASSERT(OutsideITBlock());
3051    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3052    ITScope it_scope(this, &cond);
3053    shsub16(cond, rd, rn, rm);
3054  }
3055  void Shsub16(Register rd, Register rn, Register rm) {
3056    Shsub16(al, rd, rn, rm);
3057  }
3058
3059  void Shsub8(Condition cond, Register rd, Register rn, Register rm) {
3060    VIXL_ASSERT(allow_macro_instructions_);
3061    VIXL_ASSERT(OutsideITBlock());
3062    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3063    ITScope it_scope(this, &cond);
3064    shsub8(cond, rd, rn, rm);
3065  }
3066  void Shsub8(Register rd, Register rn, Register rm) { Shsub8(al, rd, rn, rm); }
3067
3068  void Smlabb(
3069      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3070    VIXL_ASSERT(allow_macro_instructions_);
3071    VIXL_ASSERT(OutsideITBlock());
3072    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3073    ITScope it_scope(this, &cond);
3074    smlabb(cond, rd, rn, rm, ra);
3075  }
3076  void Smlabb(Register rd, Register rn, Register rm, Register ra) {
3077    Smlabb(al, rd, rn, rm, ra);
3078  }
3079
3080  void Smlabt(
3081      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3082    VIXL_ASSERT(allow_macro_instructions_);
3083    VIXL_ASSERT(OutsideITBlock());
3084    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3085    ITScope it_scope(this, &cond);
3086    smlabt(cond, rd, rn, rm, ra);
3087  }
3088  void Smlabt(Register rd, Register rn, Register rm, Register ra) {
3089    Smlabt(al, rd, rn, rm, ra);
3090  }
3091
3092  void Smlad(
3093      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3094    VIXL_ASSERT(allow_macro_instructions_);
3095    VIXL_ASSERT(OutsideITBlock());
3096    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3097    ITScope it_scope(this, &cond);
3098    smlad(cond, rd, rn, rm, ra);
3099  }
3100  void Smlad(Register rd, Register rn, Register rm, Register ra) {
3101    Smlad(al, rd, rn, rm, ra);
3102  }
3103
3104  void Smladx(
3105      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3106    VIXL_ASSERT(allow_macro_instructions_);
3107    VIXL_ASSERT(OutsideITBlock());
3108    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3109    ITScope it_scope(this, &cond);
3110    smladx(cond, rd, rn, rm, ra);
3111  }
3112  void Smladx(Register rd, Register rn, Register rm, Register ra) {
3113    Smladx(al, rd, rn, rm, ra);
3114  }
3115
3116  void Smlal(
3117      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3118    VIXL_ASSERT(allow_macro_instructions_);
3119    VIXL_ASSERT(OutsideITBlock());
3120    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3121    ITScope it_scope(this, &cond);
3122    smlal(cond, rdlo, rdhi, rn, rm);
3123  }
3124  void Smlal(Register rdlo, Register rdhi, Register rn, Register rm) {
3125    Smlal(al, rdlo, rdhi, rn, rm);
3126  }
3127
3128  void Smlalbb(
3129      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3130    VIXL_ASSERT(allow_macro_instructions_);
3131    VIXL_ASSERT(OutsideITBlock());
3132    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3133    ITScope it_scope(this, &cond);
3134    smlalbb(cond, rdlo, rdhi, rn, rm);
3135  }
3136  void Smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) {
3137    Smlalbb(al, rdlo, rdhi, rn, rm);
3138  }
3139
3140  void Smlalbt(
3141      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3142    VIXL_ASSERT(allow_macro_instructions_);
3143    VIXL_ASSERT(OutsideITBlock());
3144    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3145    ITScope it_scope(this, &cond);
3146    smlalbt(cond, rdlo, rdhi, rn, rm);
3147  }
3148  void Smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) {
3149    Smlalbt(al, rdlo, rdhi, rn, rm);
3150  }
3151
3152  void Smlald(
3153      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3154    VIXL_ASSERT(allow_macro_instructions_);
3155    VIXL_ASSERT(OutsideITBlock());
3156    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3157    ITScope it_scope(this, &cond);
3158    smlald(cond, rdlo, rdhi, rn, rm);
3159  }
3160  void Smlald(Register rdlo, Register rdhi, Register rn, Register rm) {
3161    Smlald(al, rdlo, rdhi, rn, rm);
3162  }
3163
3164  void Smlaldx(
3165      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3166    VIXL_ASSERT(allow_macro_instructions_);
3167    VIXL_ASSERT(OutsideITBlock());
3168    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3169    ITScope it_scope(this, &cond);
3170    smlaldx(cond, rdlo, rdhi, rn, rm);
3171  }
3172  void Smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) {
3173    Smlaldx(al, rdlo, rdhi, rn, rm);
3174  }
3175
3176  void Smlals(
3177      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3178    VIXL_ASSERT(allow_macro_instructions_);
3179    VIXL_ASSERT(OutsideITBlock());
3180    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3181    ITScope it_scope(this, &cond);
3182    smlals(cond, rdlo, rdhi, rn, rm);
3183  }
3184  void Smlals(Register rdlo, Register rdhi, Register rn, Register rm) {
3185    Smlals(al, rdlo, rdhi, rn, rm);
3186  }
3187
3188  void Smlaltb(
3189      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3190    VIXL_ASSERT(allow_macro_instructions_);
3191    VIXL_ASSERT(OutsideITBlock());
3192    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3193    ITScope it_scope(this, &cond);
3194    smlaltb(cond, rdlo, rdhi, rn, rm);
3195  }
3196  void Smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) {
3197    Smlaltb(al, rdlo, rdhi, rn, rm);
3198  }
3199
3200  void Smlaltt(
3201      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3202    VIXL_ASSERT(allow_macro_instructions_);
3203    VIXL_ASSERT(OutsideITBlock());
3204    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3205    ITScope it_scope(this, &cond);
3206    smlaltt(cond, rdlo, rdhi, rn, rm);
3207  }
3208  void Smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) {
3209    Smlaltt(al, rdlo, rdhi, rn, rm);
3210  }
3211
3212  void Smlatb(
3213      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3214    VIXL_ASSERT(allow_macro_instructions_);
3215    VIXL_ASSERT(OutsideITBlock());
3216    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3217    ITScope it_scope(this, &cond);
3218    smlatb(cond, rd, rn, rm, ra);
3219  }
3220  void Smlatb(Register rd, Register rn, Register rm, Register ra) {
3221    Smlatb(al, rd, rn, rm, ra);
3222  }
3223
3224  void Smlatt(
3225      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3226    VIXL_ASSERT(allow_macro_instructions_);
3227    VIXL_ASSERT(OutsideITBlock());
3228    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3229    ITScope it_scope(this, &cond);
3230    smlatt(cond, rd, rn, rm, ra);
3231  }
3232  void Smlatt(Register rd, Register rn, Register rm, Register ra) {
3233    Smlatt(al, rd, rn, rm, ra);
3234  }
3235
3236  void Smlawb(
3237      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3238    VIXL_ASSERT(allow_macro_instructions_);
3239    VIXL_ASSERT(OutsideITBlock());
3240    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3241    ITScope it_scope(this, &cond);
3242    smlawb(cond, rd, rn, rm, ra);
3243  }
3244  void Smlawb(Register rd, Register rn, Register rm, Register ra) {
3245    Smlawb(al, rd, rn, rm, ra);
3246  }
3247
3248  void Smlawt(
3249      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3250    VIXL_ASSERT(allow_macro_instructions_);
3251    VIXL_ASSERT(OutsideITBlock());
3252    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3253    ITScope it_scope(this, &cond);
3254    smlawt(cond, rd, rn, rm, ra);
3255  }
3256  void Smlawt(Register rd, Register rn, Register rm, Register ra) {
3257    Smlawt(al, rd, rn, rm, ra);
3258  }
3259
3260  void Smlsd(
3261      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3262    VIXL_ASSERT(allow_macro_instructions_);
3263    VIXL_ASSERT(OutsideITBlock());
3264    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3265    ITScope it_scope(this, &cond);
3266    smlsd(cond, rd, rn, rm, ra);
3267  }
3268  void Smlsd(Register rd, Register rn, Register rm, Register ra) {
3269    Smlsd(al, rd, rn, rm, ra);
3270  }
3271
3272  void Smlsdx(
3273      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3274    VIXL_ASSERT(allow_macro_instructions_);
3275    VIXL_ASSERT(OutsideITBlock());
3276    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3277    ITScope it_scope(this, &cond);
3278    smlsdx(cond, rd, rn, rm, ra);
3279  }
3280  void Smlsdx(Register rd, Register rn, Register rm, Register ra) {
3281    Smlsdx(al, rd, rn, rm, ra);
3282  }
3283
3284  void Smlsld(
3285      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3286    VIXL_ASSERT(allow_macro_instructions_);
3287    VIXL_ASSERT(OutsideITBlock());
3288    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3289    ITScope it_scope(this, &cond);
3290    smlsld(cond, rdlo, rdhi, rn, rm);
3291  }
3292  void Smlsld(Register rdlo, Register rdhi, Register rn, Register rm) {
3293    Smlsld(al, rdlo, rdhi, rn, rm);
3294  }
3295
3296  void Smlsldx(
3297      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3298    VIXL_ASSERT(allow_macro_instructions_);
3299    VIXL_ASSERT(OutsideITBlock());
3300    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3301    ITScope it_scope(this, &cond);
3302    smlsldx(cond, rdlo, rdhi, rn, rm);
3303  }
3304  void Smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) {
3305    Smlsldx(al, rdlo, rdhi, rn, rm);
3306  }
3307
3308  void Smmla(
3309      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3310    VIXL_ASSERT(allow_macro_instructions_);
3311    VIXL_ASSERT(OutsideITBlock());
3312    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3313    ITScope it_scope(this, &cond);
3314    smmla(cond, rd, rn, rm, ra);
3315  }
3316  void Smmla(Register rd, Register rn, Register rm, Register ra) {
3317    Smmla(al, rd, rn, rm, ra);
3318  }
3319
3320  void Smmlar(
3321      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3322    VIXL_ASSERT(allow_macro_instructions_);
3323    VIXL_ASSERT(OutsideITBlock());
3324    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3325    ITScope it_scope(this, &cond);
3326    smmlar(cond, rd, rn, rm, ra);
3327  }
3328  void Smmlar(Register rd, Register rn, Register rm, Register ra) {
3329    Smmlar(al, rd, rn, rm, ra);
3330  }
3331
3332  void Smmls(
3333      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3334    VIXL_ASSERT(allow_macro_instructions_);
3335    VIXL_ASSERT(OutsideITBlock());
3336    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3337    ITScope it_scope(this, &cond);
3338    smmls(cond, rd, rn, rm, ra);
3339  }
3340  void Smmls(Register rd, Register rn, Register rm, Register ra) {
3341    Smmls(al, rd, rn, rm, ra);
3342  }
3343
3344  void Smmlsr(
3345      Condition cond, Register rd, Register rn, Register rm, Register ra) {
3346    VIXL_ASSERT(allow_macro_instructions_);
3347    VIXL_ASSERT(OutsideITBlock());
3348    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3349    ITScope it_scope(this, &cond);
3350    smmlsr(cond, rd, rn, rm, ra);
3351  }
3352  void Smmlsr(Register rd, Register rn, Register rm, Register ra) {
3353    Smmlsr(al, rd, rn, rm, ra);
3354  }
3355
3356  void Smmul(Condition cond, Register rd, Register rn, Register rm) {
3357    VIXL_ASSERT(allow_macro_instructions_);
3358    VIXL_ASSERT(OutsideITBlock());
3359    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3360    ITScope it_scope(this, &cond);
3361    smmul(cond, rd, rn, rm);
3362  }
3363  void Smmul(Register rd, Register rn, Register rm) { Smmul(al, rd, rn, rm); }
3364
3365  void Smmulr(Condition cond, Register rd, Register rn, Register rm) {
3366    VIXL_ASSERT(allow_macro_instructions_);
3367    VIXL_ASSERT(OutsideITBlock());
3368    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3369    ITScope it_scope(this, &cond);
3370    smmulr(cond, rd, rn, rm);
3371  }
3372  void Smmulr(Register rd, Register rn, Register rm) { Smmulr(al, rd, rn, rm); }
3373
3374  void Smuad(Condition cond, Register rd, Register rn, Register rm) {
3375    VIXL_ASSERT(allow_macro_instructions_);
3376    VIXL_ASSERT(OutsideITBlock());
3377    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3378    ITScope it_scope(this, &cond);
3379    smuad(cond, rd, rn, rm);
3380  }
3381  void Smuad(Register rd, Register rn, Register rm) { Smuad(al, rd, rn, rm); }
3382
3383  void Smuadx(Condition cond, Register rd, Register rn, Register rm) {
3384    VIXL_ASSERT(allow_macro_instructions_);
3385    VIXL_ASSERT(OutsideITBlock());
3386    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3387    ITScope it_scope(this, &cond);
3388    smuadx(cond, rd, rn, rm);
3389  }
3390  void Smuadx(Register rd, Register rn, Register rm) { Smuadx(al, rd, rn, rm); }
3391
3392  void Smulbb(Condition cond, Register rd, Register rn, Register rm) {
3393    VIXL_ASSERT(allow_macro_instructions_);
3394    VIXL_ASSERT(OutsideITBlock());
3395    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3396    ITScope it_scope(this, &cond);
3397    smulbb(cond, rd, rn, rm);
3398  }
3399  void Smulbb(Register rd, Register rn, Register rm) { Smulbb(al, rd, rn, rm); }
3400
3401  void Smulbt(Condition cond, Register rd, Register rn, Register rm) {
3402    VIXL_ASSERT(allow_macro_instructions_);
3403    VIXL_ASSERT(OutsideITBlock());
3404    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3405    ITScope it_scope(this, &cond);
3406    smulbt(cond, rd, rn, rm);
3407  }
3408  void Smulbt(Register rd, Register rn, Register rm) { Smulbt(al, rd, rn, rm); }
3409
3410  void Smull(
3411      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3412    VIXL_ASSERT(allow_macro_instructions_);
3413    VIXL_ASSERT(OutsideITBlock());
3414    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3415    ITScope it_scope(this, &cond);
3416    smull(cond, rdlo, rdhi, rn, rm);
3417  }
3418  void Smull(Register rdlo, Register rdhi, Register rn, Register rm) {
3419    Smull(al, rdlo, rdhi, rn, rm);
3420  }
3421  void Smull(FlagsUpdate flags,
3422             Condition cond,
3423             Register rdlo,
3424             Register rdhi,
3425             Register rn,
3426             Register rm) {
3427    switch (flags) {
3428      case LeaveFlags:
3429        Smull(cond, rdlo, rdhi, rn, rm);
3430        break;
3431      case SetFlags:
3432        Smulls(cond, rdlo, rdhi, rn, rm);
3433        break;
3434      case DontCare:
3435        Smull(cond, rdlo, rdhi, rn, rm);
3436        break;
3437    }
3438  }
3439  void Smull(FlagsUpdate flags,
3440             Register rdlo,
3441             Register rdhi,
3442             Register rn,
3443             Register rm) {
3444    Smull(flags, al, rdlo, rdhi, rn, rm);
3445  }
3446
3447  void Smulls(
3448      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3449    VIXL_ASSERT(allow_macro_instructions_);
3450    VIXL_ASSERT(OutsideITBlock());
3451    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3452    ITScope it_scope(this, &cond);
3453    smulls(cond, rdlo, rdhi, rn, rm);
3454  }
3455  void Smulls(Register rdlo, Register rdhi, Register rn, Register rm) {
3456    Smulls(al, rdlo, rdhi, rn, rm);
3457  }
3458
3459  void Smultb(Condition cond, Register rd, Register rn, Register rm) {
3460    VIXL_ASSERT(allow_macro_instructions_);
3461    VIXL_ASSERT(OutsideITBlock());
3462    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3463    ITScope it_scope(this, &cond);
3464    smultb(cond, rd, rn, rm);
3465  }
3466  void Smultb(Register rd, Register rn, Register rm) { Smultb(al, rd, rn, rm); }
3467
3468  void Smultt(Condition cond, Register rd, Register rn, Register rm) {
3469    VIXL_ASSERT(allow_macro_instructions_);
3470    VIXL_ASSERT(OutsideITBlock());
3471    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3472    ITScope it_scope(this, &cond);
3473    smultt(cond, rd, rn, rm);
3474  }
3475  void Smultt(Register rd, Register rn, Register rm) { Smultt(al, rd, rn, rm); }
3476
3477  void Smulwb(Condition cond, Register rd, Register rn, Register rm) {
3478    VIXL_ASSERT(allow_macro_instructions_);
3479    VIXL_ASSERT(OutsideITBlock());
3480    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3481    ITScope it_scope(this, &cond);
3482    smulwb(cond, rd, rn, rm);
3483  }
3484  void Smulwb(Register rd, Register rn, Register rm) { Smulwb(al, rd, rn, rm); }
3485
3486  void Smulwt(Condition cond, Register rd, Register rn, Register rm) {
3487    VIXL_ASSERT(allow_macro_instructions_);
3488    VIXL_ASSERT(OutsideITBlock());
3489    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3490    ITScope it_scope(this, &cond);
3491    smulwt(cond, rd, rn, rm);
3492  }
3493  void Smulwt(Register rd, Register rn, Register rm) { Smulwt(al, rd, rn, rm); }
3494
3495  void Smusd(Condition cond, Register rd, Register rn, Register rm) {
3496    VIXL_ASSERT(allow_macro_instructions_);
3497    VIXL_ASSERT(OutsideITBlock());
3498    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3499    ITScope it_scope(this, &cond);
3500    smusd(cond, rd, rn, rm);
3501  }
3502  void Smusd(Register rd, Register rn, Register rm) { Smusd(al, rd, rn, rm); }
3503
3504  void Smusdx(Condition cond, Register rd, Register rn, Register rm) {
3505    VIXL_ASSERT(allow_macro_instructions_);
3506    VIXL_ASSERT(OutsideITBlock());
3507    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3508    ITScope it_scope(this, &cond);
3509    smusdx(cond, rd, rn, rm);
3510  }
3511  void Smusdx(Register rd, Register rn, Register rm) { Smusdx(al, rd, rn, rm); }
3512
3513  void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
3514    VIXL_ASSERT(allow_macro_instructions_);
3515    VIXL_ASSERT(OutsideITBlock());
3516    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3517    ITScope it_scope(this, &cond);
3518    ssat(cond, rd, imm, operand);
3519  }
3520  void Ssat(Register rd, uint32_t imm, const Operand& operand) {
3521    Ssat(al, rd, imm, operand);
3522  }
3523
3524  void Ssat16(Condition cond, Register rd, uint32_t imm, Register rn) {
3525    VIXL_ASSERT(allow_macro_instructions_);
3526    VIXL_ASSERT(OutsideITBlock());
3527    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3528    ITScope it_scope(this, &cond);
3529    ssat16(cond, rd, imm, rn);
3530  }
3531  void Ssat16(Register rd, uint32_t imm, Register rn) {
3532    Ssat16(al, rd, imm, rn);
3533  }
3534
3535  void Ssax(Condition cond, Register rd, Register rn, Register rm) {
3536    VIXL_ASSERT(allow_macro_instructions_);
3537    VIXL_ASSERT(OutsideITBlock());
3538    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3539    ITScope it_scope(this, &cond);
3540    ssax(cond, rd, rn, rm);
3541  }
3542  void Ssax(Register rd, Register rn, Register rm) { Ssax(al, rd, rn, rm); }
3543
3544  void Ssub16(Condition cond, Register rd, Register rn, Register rm) {
3545    VIXL_ASSERT(allow_macro_instructions_);
3546    VIXL_ASSERT(OutsideITBlock());
3547    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3548    ITScope it_scope(this, &cond);
3549    ssub16(cond, rd, rn, rm);
3550  }
3551  void Ssub16(Register rd, Register rn, Register rm) { Ssub16(al, rd, rn, rm); }
3552
3553  void Ssub8(Condition cond, Register rd, Register rn, Register rm) {
3554    VIXL_ASSERT(allow_macro_instructions_);
3555    VIXL_ASSERT(OutsideITBlock());
3556    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3557    ITScope it_scope(this, &cond);
3558    ssub8(cond, rd, rn, rm);
3559  }
3560  void Ssub8(Register rd, Register rn, Register rm) { Ssub8(al, rd, rn, rm); }
3561
3562  void Stl(Condition cond, Register rt, const MemOperand& operand) {
3563    VIXL_ASSERT(allow_macro_instructions_);
3564    VIXL_ASSERT(OutsideITBlock());
3565    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3566    ITScope it_scope(this, &cond);
3567    stl(cond, rt, operand);
3568  }
3569  void Stl(Register rt, const MemOperand& operand) { Stl(al, rt, operand); }
3570
3571  void Stlb(Condition cond, Register rt, const MemOperand& operand) {
3572    VIXL_ASSERT(allow_macro_instructions_);
3573    VIXL_ASSERT(OutsideITBlock());
3574    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3575    ITScope it_scope(this, &cond);
3576    stlb(cond, rt, operand);
3577  }
3578  void Stlb(Register rt, const MemOperand& operand) { Stlb(al, rt, operand); }
3579
3580  void Stlex(Condition cond,
3581             Register rd,
3582             Register rt,
3583             const MemOperand& operand) {
3584    VIXL_ASSERT(allow_macro_instructions_);
3585    VIXL_ASSERT(OutsideITBlock());
3586    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3587    ITScope it_scope(this, &cond);
3588    stlex(cond, rd, rt, operand);
3589  }
3590  void Stlex(Register rd, Register rt, const MemOperand& operand) {
3591    Stlex(al, rd, rt, operand);
3592  }
3593
3594  void Stlexb(Condition cond,
3595              Register rd,
3596              Register rt,
3597              const MemOperand& operand) {
3598    VIXL_ASSERT(allow_macro_instructions_);
3599    VIXL_ASSERT(OutsideITBlock());
3600    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3601    ITScope it_scope(this, &cond);
3602    stlexb(cond, rd, rt, operand);
3603  }
3604  void Stlexb(Register rd, Register rt, const MemOperand& operand) {
3605    Stlexb(al, rd, rt, operand);
3606  }
3607
3608  void Stlexd(Condition cond,
3609              Register rd,
3610              Register rt,
3611              Register rt2,
3612              const MemOperand& operand) {
3613    VIXL_ASSERT(allow_macro_instructions_);
3614    VIXL_ASSERT(OutsideITBlock());
3615    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3616    ITScope it_scope(this, &cond);
3617    stlexd(cond, rd, rt, rt2, operand);
3618  }
3619  void Stlexd(Register rd,
3620              Register rt,
3621              Register rt2,
3622              const MemOperand& operand) {
3623    Stlexd(al, rd, rt, rt2, operand);
3624  }
3625
3626  void Stlexh(Condition cond,
3627              Register rd,
3628              Register rt,
3629              const MemOperand& operand) {
3630    VIXL_ASSERT(allow_macro_instructions_);
3631    VIXL_ASSERT(OutsideITBlock());
3632    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3633    ITScope it_scope(this, &cond);
3634    stlexh(cond, rd, rt, operand);
3635  }
3636  void Stlexh(Register rd, Register rt, const MemOperand& operand) {
3637    Stlexh(al, rd, rt, operand);
3638  }
3639
3640  void Stlh(Condition cond, Register rt, const MemOperand& operand) {
3641    VIXL_ASSERT(allow_macro_instructions_);
3642    VIXL_ASSERT(OutsideITBlock());
3643    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3644    ITScope it_scope(this, &cond);
3645    stlh(cond, rt, operand);
3646  }
3647  void Stlh(Register rt, const MemOperand& operand) { Stlh(al, rt, operand); }
3648
3649  void Stm(Condition cond,
3650           Register rn,
3651           WriteBack write_back,
3652           RegisterList registers) {
3653    VIXL_ASSERT(allow_macro_instructions_);
3654    VIXL_ASSERT(OutsideITBlock());
3655    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3656    ITScope it_scope(this, &cond);
3657    stm(cond, rn, write_back, registers);
3658  }
3659  void Stm(Register rn, WriteBack write_back, RegisterList registers) {
3660    Stm(al, rn, write_back, registers);
3661  }
3662
3663  void Stmda(Condition cond,
3664             Register rn,
3665             WriteBack write_back,
3666             RegisterList registers) {
3667    VIXL_ASSERT(allow_macro_instructions_);
3668    VIXL_ASSERT(OutsideITBlock());
3669    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3670    ITScope it_scope(this, &cond);
3671    stmda(cond, rn, write_back, registers);
3672  }
3673  void Stmda(Register rn, WriteBack write_back, RegisterList registers) {
3674    Stmda(al, rn, write_back, registers);
3675  }
3676
3677  void Stmdb(Condition cond,
3678             Register rn,
3679             WriteBack write_back,
3680             RegisterList registers) {
3681    VIXL_ASSERT(allow_macro_instructions_);
3682    VIXL_ASSERT(OutsideITBlock());
3683    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3684    ITScope it_scope(this, &cond);
3685    stmdb(cond, rn, write_back, registers);
3686  }
3687  void Stmdb(Register rn, WriteBack write_back, RegisterList registers) {
3688    Stmdb(al, rn, write_back, registers);
3689  }
3690
3691  void Stmea(Condition cond,
3692             Register rn,
3693             WriteBack write_back,
3694             RegisterList registers) {
3695    VIXL_ASSERT(allow_macro_instructions_);
3696    VIXL_ASSERT(OutsideITBlock());
3697    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3698    ITScope it_scope(this, &cond);
3699    stmea(cond, rn, write_back, registers);
3700  }
3701  void Stmea(Register rn, WriteBack write_back, RegisterList registers) {
3702    Stmea(al, rn, write_back, registers);
3703  }
3704
3705  void Stmed(Condition cond,
3706             Register rn,
3707             WriteBack write_back,
3708             RegisterList registers) {
3709    VIXL_ASSERT(allow_macro_instructions_);
3710    VIXL_ASSERT(OutsideITBlock());
3711    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3712    ITScope it_scope(this, &cond);
3713    stmed(cond, rn, write_back, registers);
3714  }
3715  void Stmed(Register rn, WriteBack write_back, RegisterList registers) {
3716    Stmed(al, rn, write_back, registers);
3717  }
3718
3719  void Stmfa(Condition cond,
3720             Register rn,
3721             WriteBack write_back,
3722             RegisterList registers) {
3723    VIXL_ASSERT(allow_macro_instructions_);
3724    VIXL_ASSERT(OutsideITBlock());
3725    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3726    ITScope it_scope(this, &cond);
3727    stmfa(cond, rn, write_back, registers);
3728  }
3729  void Stmfa(Register rn, WriteBack write_back, RegisterList registers) {
3730    Stmfa(al, rn, write_back, registers);
3731  }
3732
3733  void Stmfd(Condition cond,
3734             Register rn,
3735             WriteBack write_back,
3736             RegisterList registers) {
3737    VIXL_ASSERT(allow_macro_instructions_);
3738    VIXL_ASSERT(OutsideITBlock());
3739    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3740    ITScope it_scope(this, &cond);
3741    stmfd(cond, rn, write_back, registers);
3742  }
3743  void Stmfd(Register rn, WriteBack write_back, RegisterList registers) {
3744    Stmfd(al, rn, write_back, registers);
3745  }
3746
3747  void Stmib(Condition cond,
3748             Register rn,
3749             WriteBack write_back,
3750             RegisterList registers) {
3751    VIXL_ASSERT(allow_macro_instructions_);
3752    VIXL_ASSERT(OutsideITBlock());
3753    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3754    ITScope it_scope(this, &cond);
3755    stmib(cond, rn, write_back, registers);
3756  }
3757  void Stmib(Register rn, WriteBack write_back, RegisterList registers) {
3758    Stmib(al, rn, write_back, registers);
3759  }
3760
3761  void Str(Condition cond, Register rt, const MemOperand& operand) {
3762    VIXL_ASSERT(allow_macro_instructions_);
3763    VIXL_ASSERT(OutsideITBlock());
3764    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3765    bool can_use_it =
3766        // STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1
3767        (operand.IsImmediate() && rt.IsLow() &&
3768         operand.GetBaseRegister().IsLow() &&
3769         operand.IsOffsetImmediateWithinRange(0, 124, 4) &&
3770         (operand.GetAddrMode() == Offset)) ||
3771        // STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2
3772        (operand.IsImmediate() && rt.IsLow() &&
3773         operand.GetBaseRegister().IsSP() &&
3774         operand.IsOffsetImmediateWithinRange(0, 1020, 4) &&
3775         (operand.GetAddrMode() == Offset)) ||
3776        // STR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
3777        (operand.IsPlainRegister() && rt.IsLow() &&
3778         operand.GetBaseRegister().IsLow() &&
3779         operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
3780         (operand.GetAddrMode() == Offset));
3781    ITScope it_scope(this, &cond, can_use_it);
3782    str(cond, rt, operand);
3783  }
3784  void Str(Register rt, const MemOperand& operand) { Str(al, rt, operand); }
3785
3786  void Strb(Condition cond, Register rt, const MemOperand& operand) {
3787    VIXL_ASSERT(allow_macro_instructions_);
3788    VIXL_ASSERT(OutsideITBlock());
3789    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3790    bool can_use_it =
3791        // STRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1
3792        (operand.IsImmediate() && rt.IsLow() &&
3793         operand.GetBaseRegister().IsLow() &&
3794         operand.IsOffsetImmediateWithinRange(0, 31) &&
3795         (operand.GetAddrMode() == Offset)) ||
3796        // STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
3797        (operand.IsPlainRegister() && rt.IsLow() &&
3798         operand.GetBaseRegister().IsLow() &&
3799         operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
3800         (operand.GetAddrMode() == Offset));
3801    ITScope it_scope(this, &cond, can_use_it);
3802    strb(cond, rt, operand);
3803  }
3804  void Strb(Register rt, const MemOperand& operand) { Strb(al, rt, operand); }
3805
3806  void Strd(Condition cond,
3807            Register rt,
3808            Register rt2,
3809            const MemOperand& operand) {
3810    VIXL_ASSERT(allow_macro_instructions_);
3811    VIXL_ASSERT(OutsideITBlock());
3812    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3813    ITScope it_scope(this, &cond);
3814    strd(cond, rt, rt2, operand);
3815  }
3816  void Strd(Register rt, Register rt2, const MemOperand& operand) {
3817    Strd(al, rt, rt2, operand);
3818  }
3819
3820  void Strex(Condition cond,
3821             Register rd,
3822             Register rt,
3823             const MemOperand& operand) {
3824    VIXL_ASSERT(allow_macro_instructions_);
3825    VIXL_ASSERT(OutsideITBlock());
3826    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3827    ITScope it_scope(this, &cond);
3828    strex(cond, rd, rt, operand);
3829  }
3830  void Strex(Register rd, Register rt, const MemOperand& operand) {
3831    Strex(al, rd, rt, operand);
3832  }
3833
3834  void Strexb(Condition cond,
3835              Register rd,
3836              Register rt,
3837              const MemOperand& operand) {
3838    VIXL_ASSERT(allow_macro_instructions_);
3839    VIXL_ASSERT(OutsideITBlock());
3840    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3841    ITScope it_scope(this, &cond);
3842    strexb(cond, rd, rt, operand);
3843  }
3844  void Strexb(Register rd, Register rt, const MemOperand& operand) {
3845    Strexb(al, rd, rt, operand);
3846  }
3847
3848  void Strexd(Condition cond,
3849              Register rd,
3850              Register rt,
3851              Register rt2,
3852              const MemOperand& operand) {
3853    VIXL_ASSERT(allow_macro_instructions_);
3854    VIXL_ASSERT(OutsideITBlock());
3855    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3856    ITScope it_scope(this, &cond);
3857    strexd(cond, rd, rt, rt2, operand);
3858  }
3859  void Strexd(Register rd,
3860              Register rt,
3861              Register rt2,
3862              const MemOperand& operand) {
3863    Strexd(al, rd, rt, rt2, operand);
3864  }
3865
3866  void Strexh(Condition cond,
3867              Register rd,
3868              Register rt,
3869              const MemOperand& operand) {
3870    VIXL_ASSERT(allow_macro_instructions_);
3871    VIXL_ASSERT(OutsideITBlock());
3872    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3873    ITScope it_scope(this, &cond);
3874    strexh(cond, rd, rt, operand);
3875  }
3876  void Strexh(Register rd, Register rt, const MemOperand& operand) {
3877    Strexh(al, rd, rt, operand);
3878  }
3879
3880  void Strh(Condition cond, Register rt, const MemOperand& operand) {
3881    VIXL_ASSERT(allow_macro_instructions_);
3882    VIXL_ASSERT(OutsideITBlock());
3883    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3884    bool can_use_it =
3885        // STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1
3886        (operand.IsImmediate() && rt.IsLow() &&
3887         operand.GetBaseRegister().IsLow() &&
3888         operand.IsOffsetImmediateWithinRange(0, 62, 2) &&
3889         (operand.GetAddrMode() == Offset)) ||
3890        // STRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1
3891        (operand.IsPlainRegister() && rt.IsLow() &&
3892         operand.GetBaseRegister().IsLow() &&
3893         operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
3894         (operand.GetAddrMode() == Offset));
3895    ITScope it_scope(this, &cond, can_use_it);
3896    strh(cond, rt, operand);
3897  }
3898  void Strh(Register rt, const MemOperand& operand) { Strh(al, rt, operand); }
3899
3900  void Sub(Condition cond, Register rd, Register rn, const Operand& operand) {
3901    VIXL_ASSERT(allow_macro_instructions_);
3902    VIXL_ASSERT(OutsideITBlock());
3903    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3904    if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
3905      uint32_t immediate = operand.GetImmediate();
3906      if (immediate == 0) {
3907        return;
3908      }
3909    }
3910    bool can_use_it =
3911        // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
3912        (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() &&
3913         rd.IsLow()) ||
3914        // SUB<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2
3915        (operand.IsImmediate() && (operand.GetImmediate() <= 255) &&
3916         rd.IsLow() && rn.Is(rd)) ||
3917        // SUB<c>{<q>} <Rd>, <Rn>, <Rm>
3918        (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
3919         operand.GetBaseRegister().IsLow());
3920    ITScope it_scope(this, &cond, can_use_it);
3921    sub(cond, rd, rn, operand);
3922  }
3923  void Sub(Register rd, Register rn, const Operand& operand) {
3924    Sub(al, rd, rn, operand);
3925  }
3926  void Sub(FlagsUpdate flags,
3927           Condition cond,
3928           Register rd,
3929           Register rn,
3930           const Operand& operand) {
3931    switch (flags) {
3932      case LeaveFlags:
3933        Sub(cond, rd, rn, operand);
3934        break;
3935      case SetFlags:
3936        Subs(cond, rd, rn, operand);
3937        break;
3938      case DontCare:
3939        bool can_be_16bit_encoded =
3940            IsUsingT32() && cond.Is(al) &&
3941            ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
3942              operand.GetBaseRegister().IsLow()) ||
3943             (operand.IsImmediate() &&
3944              ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
3945               (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
3946        if (can_be_16bit_encoded) {
3947          Subs(cond, rd, rn, operand);
3948        } else {
3949          Sub(cond, rd, rn, operand);
3950        }
3951        break;
3952    }
3953  }
3954  void Sub(FlagsUpdate flags,
3955           Register rd,
3956           Register rn,
3957           const Operand& operand) {
3958    Sub(flags, al, rd, rn, operand);
3959  }
3960
3961  void Subs(Condition cond, Register rd, Register rn, const Operand& operand) {
3962    VIXL_ASSERT(allow_macro_instructions_);
3963    VIXL_ASSERT(OutsideITBlock());
3964    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3965    ITScope it_scope(this, &cond);
3966    subs(cond, rd, rn, operand);
3967  }
3968  void Subs(Register rd, Register rn, const Operand& operand) {
3969    Subs(al, rd, rn, operand);
3970  }
3971
3972  void Subw(Condition cond, Register rd, Register rn, const Operand& operand) {
3973    VIXL_ASSERT(allow_macro_instructions_);
3974    VIXL_ASSERT(OutsideITBlock());
3975    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3976    ITScope it_scope(this, &cond);
3977    subw(cond, rd, rn, operand);
3978  }
3979  void Subw(Register rd, Register rn, const Operand& operand) {
3980    Subw(al, rd, rn, operand);
3981  }
3982
3983  void Svc(Condition cond, uint32_t imm) {
3984    VIXL_ASSERT(allow_macro_instructions_);
3985    VIXL_ASSERT(OutsideITBlock());
3986    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3987    ITScope it_scope(this, &cond);
3988    svc(cond, imm);
3989  }
3990  void Svc(uint32_t imm) { Svc(al, imm); }
3991
3992  void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
3993    VIXL_ASSERT(allow_macro_instructions_);
3994    VIXL_ASSERT(OutsideITBlock());
3995    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
3996    ITScope it_scope(this, &cond);
3997    sxtab(cond, rd, rn, operand);
3998  }
3999  void Sxtab(Register rd, Register rn, const Operand& operand) {
4000    Sxtab(al, rd, rn, operand);
4001  }
4002
4003  void Sxtab16(Condition cond,
4004               Register rd,
4005               Register rn,
4006               const Operand& operand) {
4007    VIXL_ASSERT(allow_macro_instructions_);
4008    VIXL_ASSERT(OutsideITBlock());
4009    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4010    ITScope it_scope(this, &cond);
4011    sxtab16(cond, rd, rn, operand);
4012  }
4013  void Sxtab16(Register rd, Register rn, const Operand& operand) {
4014    Sxtab16(al, rd, rn, operand);
4015  }
4016
4017  void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
4018    VIXL_ASSERT(allow_macro_instructions_);
4019    VIXL_ASSERT(OutsideITBlock());
4020    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4021    ITScope it_scope(this, &cond);
4022    sxtah(cond, rd, rn, operand);
4023  }
4024  void Sxtah(Register rd, Register rn, const Operand& operand) {
4025    Sxtah(al, rd, rn, operand);
4026  }
4027
4028  void Sxtb(Condition cond, Register rd, const Operand& operand) {
4029    VIXL_ASSERT(allow_macro_instructions_);
4030    VIXL_ASSERT(OutsideITBlock());
4031    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4032    ITScope it_scope(this, &cond);
4033    sxtb(cond, rd, operand);
4034  }
4035  void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); }
4036
4037  void Sxtb16(Condition cond, Register rd, const Operand& operand) {
4038    VIXL_ASSERT(allow_macro_instructions_);
4039    VIXL_ASSERT(OutsideITBlock());
4040    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4041    ITScope it_scope(this, &cond);
4042    sxtb16(cond, rd, operand);
4043  }
4044  void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); }
4045
4046  void Sxth(Condition cond, Register rd, const Operand& operand) {
4047    VIXL_ASSERT(allow_macro_instructions_);
4048    VIXL_ASSERT(OutsideITBlock());
4049    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4050    ITScope it_scope(this, &cond);
4051    sxth(cond, rd, operand);
4052  }
4053  void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); }
4054
4055  void Tbb(Condition cond, Register rn, Register rm) {
4056    VIXL_ASSERT(allow_macro_instructions_);
4057    VIXL_ASSERT(OutsideITBlock());
4058    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4059    ITScope it_scope(this, &cond);
4060    tbb(cond, rn, rm);
4061  }
4062  void Tbb(Register rn, Register rm) { Tbb(al, rn, rm); }
4063
4064  void Tbh(Condition cond, Register rn, Register rm) {
4065    VIXL_ASSERT(allow_macro_instructions_);
4066    VIXL_ASSERT(OutsideITBlock());
4067    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4068    ITScope it_scope(this, &cond);
4069    tbh(cond, rn, rm);
4070  }
4071  void Tbh(Register rn, Register rm) { Tbh(al, rn, rm); }
4072
4073  void Teq(Condition cond, Register rn, const Operand& operand) {
4074    VIXL_ASSERT(allow_macro_instructions_);
4075    VIXL_ASSERT(OutsideITBlock());
4076    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4077    ITScope it_scope(this, &cond);
4078    teq(cond, rn, operand);
4079  }
4080  void Teq(Register rn, const Operand& operand) { Teq(al, rn, operand); }
4081
4082  void Tst(Condition cond, Register rn, const Operand& operand) {
4083    VIXL_ASSERT(allow_macro_instructions_);
4084    VIXL_ASSERT(OutsideITBlock());
4085    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4086    bool can_use_it =
4087        // TST{<c>}{<q>} <Rn>, <Rm> ; T1
4088        operand.IsPlainRegister() && rn.IsLow() &&
4089        operand.GetBaseRegister().IsLow();
4090    ITScope it_scope(this, &cond, can_use_it);
4091    tst(cond, rn, operand);
4092  }
4093  void Tst(Register rn, const Operand& operand) { Tst(al, rn, operand); }
4094
4095  void Uadd16(Condition cond, Register rd, Register rn, Register rm) {
4096    VIXL_ASSERT(allow_macro_instructions_);
4097    VIXL_ASSERT(OutsideITBlock());
4098    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4099    ITScope it_scope(this, &cond);
4100    uadd16(cond, rd, rn, rm);
4101  }
4102  void Uadd16(Register rd, Register rn, Register rm) { Uadd16(al, rd, rn, rm); }
4103
4104  void Uadd8(Condition cond, Register rd, Register rn, Register rm) {
4105    VIXL_ASSERT(allow_macro_instructions_);
4106    VIXL_ASSERT(OutsideITBlock());
4107    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4108    ITScope it_scope(this, &cond);
4109    uadd8(cond, rd, rn, rm);
4110  }
4111  void Uadd8(Register rd, Register rn, Register rm) { Uadd8(al, rd, rn, rm); }
4112
4113  void Uasx(Condition cond, Register rd, Register rn, Register rm) {
4114    VIXL_ASSERT(allow_macro_instructions_);
4115    VIXL_ASSERT(OutsideITBlock());
4116    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4117    ITScope it_scope(this, &cond);
4118    uasx(cond, rd, rn, rm);
4119  }
4120  void Uasx(Register rd, Register rn, Register rm) { Uasx(al, rd, rn, rm); }
4121
4122  void Ubfx(Condition cond,
4123            Register rd,
4124            Register rn,
4125            uint32_t lsb,
4126            const Operand& operand) {
4127    VIXL_ASSERT(allow_macro_instructions_);
4128    VIXL_ASSERT(OutsideITBlock());
4129    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4130    ITScope it_scope(this, &cond);
4131    ubfx(cond, rd, rn, lsb, operand);
4132  }
4133  void Ubfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) {
4134    Ubfx(al, rd, rn, lsb, operand);
4135  }
4136
4137  void Udf(Condition cond, uint32_t imm) {
4138    VIXL_ASSERT(allow_macro_instructions_);
4139    VIXL_ASSERT(OutsideITBlock());
4140    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4141    ITScope it_scope(this, &cond);
4142    udf(cond, imm);
4143  }
4144  void Udf(uint32_t imm) { Udf(al, imm); }
4145
4146  void Udiv(Condition cond, Register rd, Register rn, Register rm) {
4147    VIXL_ASSERT(allow_macro_instructions_);
4148    VIXL_ASSERT(OutsideITBlock());
4149    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4150    ITScope it_scope(this, &cond);
4151    udiv(cond, rd, rn, rm);
4152  }
4153  void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); }
4154
4155  void Uhadd16(Condition cond, Register rd, Register rn, Register rm) {
4156    VIXL_ASSERT(allow_macro_instructions_);
4157    VIXL_ASSERT(OutsideITBlock());
4158    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4159    ITScope it_scope(this, &cond);
4160    uhadd16(cond, rd, rn, rm);
4161  }
4162  void Uhadd16(Register rd, Register rn, Register rm) {
4163    Uhadd16(al, rd, rn, rm);
4164  }
4165
4166  void Uhadd8(Condition cond, Register rd, Register rn, Register rm) {
4167    VIXL_ASSERT(allow_macro_instructions_);
4168    VIXL_ASSERT(OutsideITBlock());
4169    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4170    ITScope it_scope(this, &cond);
4171    uhadd8(cond, rd, rn, rm);
4172  }
4173  void Uhadd8(Register rd, Register rn, Register rm) { Uhadd8(al, rd, rn, rm); }
4174
4175  void Uhasx(Condition cond, Register rd, Register rn, Register rm) {
4176    VIXL_ASSERT(allow_macro_instructions_);
4177    VIXL_ASSERT(OutsideITBlock());
4178    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4179    ITScope it_scope(this, &cond);
4180    uhasx(cond, rd, rn, rm);
4181  }
4182  void Uhasx(Register rd, Register rn, Register rm) { Uhasx(al, rd, rn, rm); }
4183
4184  void Uhsax(Condition cond, Register rd, Register rn, Register rm) {
4185    VIXL_ASSERT(allow_macro_instructions_);
4186    VIXL_ASSERT(OutsideITBlock());
4187    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4188    ITScope it_scope(this, &cond);
4189    uhsax(cond, rd, rn, rm);
4190  }
4191  void Uhsax(Register rd, Register rn, Register rm) { Uhsax(al, rd, rn, rm); }
4192
4193  void Uhsub16(Condition cond, Register rd, Register rn, Register rm) {
4194    VIXL_ASSERT(allow_macro_instructions_);
4195    VIXL_ASSERT(OutsideITBlock());
4196    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4197    ITScope it_scope(this, &cond);
4198    uhsub16(cond, rd, rn, rm);
4199  }
4200  void Uhsub16(Register rd, Register rn, Register rm) {
4201    Uhsub16(al, rd, rn, rm);
4202  }
4203
4204  void Uhsub8(Condition cond, Register rd, Register rn, Register rm) {
4205    VIXL_ASSERT(allow_macro_instructions_);
4206    VIXL_ASSERT(OutsideITBlock());
4207    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4208    ITScope it_scope(this, &cond);
4209    uhsub8(cond, rd, rn, rm);
4210  }
4211  void Uhsub8(Register rd, Register rn, Register rm) { Uhsub8(al, rd, rn, rm); }
4212
4213  void Umaal(
4214      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4215    VIXL_ASSERT(allow_macro_instructions_);
4216    VIXL_ASSERT(OutsideITBlock());
4217    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4218    ITScope it_scope(this, &cond);
4219    umaal(cond, rdlo, rdhi, rn, rm);
4220  }
4221  void Umaal(Register rdlo, Register rdhi, Register rn, Register rm) {
4222    Umaal(al, rdlo, rdhi, rn, rm);
4223  }
4224
4225  void Umlal(
4226      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4227    VIXL_ASSERT(allow_macro_instructions_);
4228    VIXL_ASSERT(OutsideITBlock());
4229    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4230    ITScope it_scope(this, &cond);
4231    umlal(cond, rdlo, rdhi, rn, rm);
4232  }
4233  void Umlal(Register rdlo, Register rdhi, Register rn, Register rm) {
4234    Umlal(al, rdlo, rdhi, rn, rm);
4235  }
4236  void Umlal(FlagsUpdate flags,
4237             Condition cond,
4238             Register rdlo,
4239             Register rdhi,
4240             Register rn,
4241             Register rm) {
4242    switch (flags) {
4243      case LeaveFlags:
4244        Umlal(cond, rdlo, rdhi, rn, rm);
4245        break;
4246      case SetFlags:
4247        Umlals(cond, rdlo, rdhi, rn, rm);
4248        break;
4249      case DontCare:
4250        Umlal(cond, rdlo, rdhi, rn, rm);
4251        break;
4252    }
4253  }
4254  void Umlal(FlagsUpdate flags,
4255             Register rdlo,
4256             Register rdhi,
4257             Register rn,
4258             Register rm) {
4259    Umlal(flags, al, rdlo, rdhi, rn, rm);
4260  }
4261
4262  void Umlals(
4263      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4264    VIXL_ASSERT(allow_macro_instructions_);
4265    VIXL_ASSERT(OutsideITBlock());
4266    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4267    ITScope it_scope(this, &cond);
4268    umlals(cond, rdlo, rdhi, rn, rm);
4269  }
4270  void Umlals(Register rdlo, Register rdhi, Register rn, Register rm) {
4271    Umlals(al, rdlo, rdhi, rn, rm);
4272  }
4273
4274  void Umull(
4275      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4276    VIXL_ASSERT(allow_macro_instructions_);
4277    VIXL_ASSERT(OutsideITBlock());
4278    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4279    ITScope it_scope(this, &cond);
4280    umull(cond, rdlo, rdhi, rn, rm);
4281  }
4282  void Umull(Register rdlo, Register rdhi, Register rn, Register rm) {
4283    Umull(al, rdlo, rdhi, rn, rm);
4284  }
4285  void Umull(FlagsUpdate flags,
4286             Condition cond,
4287             Register rdlo,
4288             Register rdhi,
4289             Register rn,
4290             Register rm) {
4291    switch (flags) {
4292      case LeaveFlags:
4293        Umull(cond, rdlo, rdhi, rn, rm);
4294        break;
4295      case SetFlags:
4296        Umulls(cond, rdlo, rdhi, rn, rm);
4297        break;
4298      case DontCare:
4299        Umull(cond, rdlo, rdhi, rn, rm);
4300        break;
4301    }
4302  }
4303  void Umull(FlagsUpdate flags,
4304             Register rdlo,
4305             Register rdhi,
4306             Register rn,
4307             Register rm) {
4308    Umull(flags, al, rdlo, rdhi, rn, rm);
4309  }
4310
4311  void Umulls(
4312      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4313    VIXL_ASSERT(allow_macro_instructions_);
4314    VIXL_ASSERT(OutsideITBlock());
4315    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4316    ITScope it_scope(this, &cond);
4317    umulls(cond, rdlo, rdhi, rn, rm);
4318  }
4319  void Umulls(Register rdlo, Register rdhi, Register rn, Register rm) {
4320    Umulls(al, rdlo, rdhi, rn, rm);
4321  }
4322
4323  void Uqadd16(Condition cond, Register rd, Register rn, Register rm) {
4324    VIXL_ASSERT(allow_macro_instructions_);
4325    VIXL_ASSERT(OutsideITBlock());
4326    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4327    ITScope it_scope(this, &cond);
4328    uqadd16(cond, rd, rn, rm);
4329  }
4330  void Uqadd16(Register rd, Register rn, Register rm) {
4331    Uqadd16(al, rd, rn, rm);
4332  }
4333
4334  void Uqadd8(Condition cond, Register rd, Register rn, Register rm) {
4335    VIXL_ASSERT(allow_macro_instructions_);
4336    VIXL_ASSERT(OutsideITBlock());
4337    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4338    ITScope it_scope(this, &cond);
4339    uqadd8(cond, rd, rn, rm);
4340  }
4341  void Uqadd8(Register rd, Register rn, Register rm) { Uqadd8(al, rd, rn, rm); }
4342
4343  void Uqasx(Condition cond, Register rd, Register rn, Register rm) {
4344    VIXL_ASSERT(allow_macro_instructions_);
4345    VIXL_ASSERT(OutsideITBlock());
4346    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4347    ITScope it_scope(this, &cond);
4348    uqasx(cond, rd, rn, rm);
4349  }
4350  void Uqasx(Register rd, Register rn, Register rm) { Uqasx(al, rd, rn, rm); }
4351
4352  void Uqsax(Condition cond, Register rd, Register rn, Register rm) {
4353    VIXL_ASSERT(allow_macro_instructions_);
4354    VIXL_ASSERT(OutsideITBlock());
4355    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4356    ITScope it_scope(this, &cond);
4357    uqsax(cond, rd, rn, rm);
4358  }
4359  void Uqsax(Register rd, Register rn, Register rm) { Uqsax(al, rd, rn, rm); }
4360
4361  void Uqsub16(Condition cond, Register rd, Register rn, Register rm) {
4362    VIXL_ASSERT(allow_macro_instructions_);
4363    VIXL_ASSERT(OutsideITBlock());
4364    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4365    ITScope it_scope(this, &cond);
4366    uqsub16(cond, rd, rn, rm);
4367  }
4368  void Uqsub16(Register rd, Register rn, Register rm) {
4369    Uqsub16(al, rd, rn, rm);
4370  }
4371
4372  void Uqsub8(Condition cond, Register rd, Register rn, Register rm) {
4373    VIXL_ASSERT(allow_macro_instructions_);
4374    VIXL_ASSERT(OutsideITBlock());
4375    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4376    ITScope it_scope(this, &cond);
4377    uqsub8(cond, rd, rn, rm);
4378  }
4379  void Uqsub8(Register rd, Register rn, Register rm) { Uqsub8(al, rd, rn, rm); }
4380
4381  void Usad8(Condition cond, Register rd, Register rn, Register rm) {
4382    VIXL_ASSERT(allow_macro_instructions_);
4383    VIXL_ASSERT(OutsideITBlock());
4384    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4385    ITScope it_scope(this, &cond);
4386    usad8(cond, rd, rn, rm);
4387  }
4388  void Usad8(Register rd, Register rn, Register rm) { Usad8(al, rd, rn, rm); }
4389
4390  void Usada8(
4391      Condition cond, Register rd, Register rn, Register rm, Register ra) {
4392    VIXL_ASSERT(allow_macro_instructions_);
4393    VIXL_ASSERT(OutsideITBlock());
4394    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4395    ITScope it_scope(this, &cond);
4396    usada8(cond, rd, rn, rm, ra);
4397  }
4398  void Usada8(Register rd, Register rn, Register rm, Register ra) {
4399    Usada8(al, rd, rn, rm, ra);
4400  }
4401
4402  void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
4403    VIXL_ASSERT(allow_macro_instructions_);
4404    VIXL_ASSERT(OutsideITBlock());
4405    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4406    ITScope it_scope(this, &cond);
4407    usat(cond, rd, imm, operand);
4408  }
4409  void Usat(Register rd, uint32_t imm, const Operand& operand) {
4410    Usat(al, rd, imm, operand);
4411  }
4412
4413  void Usat16(Condition cond, Register rd, uint32_t imm, Register rn) {
4414    VIXL_ASSERT(allow_macro_instructions_);
4415    VIXL_ASSERT(OutsideITBlock());
4416    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4417    ITScope it_scope(this, &cond);
4418    usat16(cond, rd, imm, rn);
4419  }
4420  void Usat16(Register rd, uint32_t imm, Register rn) {
4421    Usat16(al, rd, imm, rn);
4422  }
4423
4424  void Usax(Condition cond, Register rd, Register rn, Register rm) {
4425    VIXL_ASSERT(allow_macro_instructions_);
4426    VIXL_ASSERT(OutsideITBlock());
4427    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4428    ITScope it_scope(this, &cond);
4429    usax(cond, rd, rn, rm);
4430  }
4431  void Usax(Register rd, Register rn, Register rm) { Usax(al, rd, rn, rm); }
4432
4433  void Usub16(Condition cond, Register rd, Register rn, Register rm) {
4434    VIXL_ASSERT(allow_macro_instructions_);
4435    VIXL_ASSERT(OutsideITBlock());
4436    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4437    ITScope it_scope(this, &cond);
4438    usub16(cond, rd, rn, rm);
4439  }
4440  void Usub16(Register rd, Register rn, Register rm) { Usub16(al, rd, rn, rm); }
4441
4442  void Usub8(Condition cond, Register rd, Register rn, Register rm) {
4443    VIXL_ASSERT(allow_macro_instructions_);
4444    VIXL_ASSERT(OutsideITBlock());
4445    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4446    ITScope it_scope(this, &cond);
4447    usub8(cond, rd, rn, rm);
4448  }
4449  void Usub8(Register rd, Register rn, Register rm) { Usub8(al, rd, rn, rm); }
4450
4451  void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
4452    VIXL_ASSERT(allow_macro_instructions_);
4453    VIXL_ASSERT(OutsideITBlock());
4454    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4455    ITScope it_scope(this, &cond);
4456    uxtab(cond, rd, rn, operand);
4457  }
4458  void Uxtab(Register rd, Register rn, const Operand& operand) {
4459    Uxtab(al, rd, rn, operand);
4460  }
4461
4462  void Uxtab16(Condition cond,
4463               Register rd,
4464               Register rn,
4465               const Operand& operand) {
4466    VIXL_ASSERT(allow_macro_instructions_);
4467    VIXL_ASSERT(OutsideITBlock());
4468    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4469    ITScope it_scope(this, &cond);
4470    uxtab16(cond, rd, rn, operand);
4471  }
4472  void Uxtab16(Register rd, Register rn, const Operand& operand) {
4473    Uxtab16(al, rd, rn, operand);
4474  }
4475
4476  void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
4477    VIXL_ASSERT(allow_macro_instructions_);
4478    VIXL_ASSERT(OutsideITBlock());
4479    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4480    ITScope it_scope(this, &cond);
4481    uxtah(cond, rd, rn, operand);
4482  }
4483  void Uxtah(Register rd, Register rn, const Operand& operand) {
4484    Uxtah(al, rd, rn, operand);
4485  }
4486
4487  void Uxtb(Condition cond, Register rd, const Operand& operand) {
4488    VIXL_ASSERT(allow_macro_instructions_);
4489    VIXL_ASSERT(OutsideITBlock());
4490    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4491    ITScope it_scope(this, &cond);
4492    uxtb(cond, rd, operand);
4493  }
4494  void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); }
4495
4496  void Uxtb16(Condition cond, Register rd, const Operand& operand) {
4497    VIXL_ASSERT(allow_macro_instructions_);
4498    VIXL_ASSERT(OutsideITBlock());
4499    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4500    ITScope it_scope(this, &cond);
4501    uxtb16(cond, rd, operand);
4502  }
4503  void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); }
4504
4505  void Uxth(Condition cond, Register rd, const Operand& operand) {
4506    VIXL_ASSERT(allow_macro_instructions_);
4507    VIXL_ASSERT(OutsideITBlock());
4508    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4509    ITScope it_scope(this, &cond);
4510    uxth(cond, rd, operand);
4511  }
4512  void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); }
4513
4514  void Vaba(
4515      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4516    VIXL_ASSERT(allow_macro_instructions_);
4517    VIXL_ASSERT(OutsideITBlock());
4518    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4519    ITScope it_scope(this, &cond);
4520    vaba(cond, dt, rd, rn, rm);
4521  }
4522  void Vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4523    Vaba(al, dt, rd, rn, rm);
4524  }
4525
4526  void Vaba(
4527      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4528    VIXL_ASSERT(allow_macro_instructions_);
4529    VIXL_ASSERT(OutsideITBlock());
4530    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4531    ITScope it_scope(this, &cond);
4532    vaba(cond, dt, rd, rn, rm);
4533  }
4534  void Vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4535    Vaba(al, dt, rd, rn, rm);
4536  }
4537
4538  void Vabal(
4539      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4540    VIXL_ASSERT(allow_macro_instructions_);
4541    VIXL_ASSERT(OutsideITBlock());
4542    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4543    ITScope it_scope(this, &cond);
4544    vabal(cond, dt, rd, rn, rm);
4545  }
4546  void Vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4547    Vabal(al, dt, rd, rn, rm);
4548  }
4549
4550  void Vabd(
4551      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4552    VIXL_ASSERT(allow_macro_instructions_);
4553    VIXL_ASSERT(OutsideITBlock());
4554    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4555    ITScope it_scope(this, &cond);
4556    vabd(cond, dt, rd, rn, rm);
4557  }
4558  void Vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4559    Vabd(al, dt, rd, rn, rm);
4560  }
4561
4562  void Vabd(
4563      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4564    VIXL_ASSERT(allow_macro_instructions_);
4565    VIXL_ASSERT(OutsideITBlock());
4566    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4567    ITScope it_scope(this, &cond);
4568    vabd(cond, dt, rd, rn, rm);
4569  }
4570  void Vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4571    Vabd(al, dt, rd, rn, rm);
4572  }
4573
4574  void Vabdl(
4575      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4576    VIXL_ASSERT(allow_macro_instructions_);
4577    VIXL_ASSERT(OutsideITBlock());
4578    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4579    ITScope it_scope(this, &cond);
4580    vabdl(cond, dt, rd, rn, rm);
4581  }
4582  void Vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4583    Vabdl(al, dt, rd, rn, rm);
4584  }
4585
4586  void Vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
4587    VIXL_ASSERT(allow_macro_instructions_);
4588    VIXL_ASSERT(OutsideITBlock());
4589    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4590    ITScope it_scope(this, &cond);
4591    vabs(cond, dt, rd, rm);
4592  }
4593  void Vabs(DataType dt, DRegister rd, DRegister rm) { Vabs(al, dt, rd, rm); }
4594
4595  void Vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
4596    VIXL_ASSERT(allow_macro_instructions_);
4597    VIXL_ASSERT(OutsideITBlock());
4598    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4599    ITScope it_scope(this, &cond);
4600    vabs(cond, dt, rd, rm);
4601  }
4602  void Vabs(DataType dt, QRegister rd, QRegister rm) { Vabs(al, dt, rd, rm); }
4603
4604  void Vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {
4605    VIXL_ASSERT(allow_macro_instructions_);
4606    VIXL_ASSERT(OutsideITBlock());
4607    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4608    ITScope it_scope(this, &cond);
4609    vabs(cond, dt, rd, rm);
4610  }
4611  void Vabs(DataType dt, SRegister rd, SRegister rm) { Vabs(al, dt, rd, rm); }
4612
4613  void Vacge(
4614      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4615    VIXL_ASSERT(allow_macro_instructions_);
4616    VIXL_ASSERT(OutsideITBlock());
4617    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4618    ITScope it_scope(this, &cond);
4619    vacge(cond, dt, rd, rn, rm);
4620  }
4621  void Vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4622    Vacge(al, dt, rd, rn, rm);
4623  }
4624
4625  void Vacge(
4626      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4627    VIXL_ASSERT(allow_macro_instructions_);
4628    VIXL_ASSERT(OutsideITBlock());
4629    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4630    ITScope it_scope(this, &cond);
4631    vacge(cond, dt, rd, rn, rm);
4632  }
4633  void Vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4634    Vacge(al, dt, rd, rn, rm);
4635  }
4636
4637  void Vacgt(
4638      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4639    VIXL_ASSERT(allow_macro_instructions_);
4640    VIXL_ASSERT(OutsideITBlock());
4641    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4642    ITScope it_scope(this, &cond);
4643    vacgt(cond, dt, rd, rn, rm);
4644  }
4645  void Vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4646    Vacgt(al, dt, rd, rn, rm);
4647  }
4648
4649  void Vacgt(
4650      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4651    VIXL_ASSERT(allow_macro_instructions_);
4652    VIXL_ASSERT(OutsideITBlock());
4653    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4654    ITScope it_scope(this, &cond);
4655    vacgt(cond, dt, rd, rn, rm);
4656  }
4657  void Vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4658    Vacgt(al, dt, rd, rn, rm);
4659  }
4660
4661  void Vacle(
4662      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4663    VIXL_ASSERT(allow_macro_instructions_);
4664    VIXL_ASSERT(OutsideITBlock());
4665    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4666    ITScope it_scope(this, &cond);
4667    vacle(cond, dt, rd, rn, rm);
4668  }
4669  void Vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4670    Vacle(al, dt, rd, rn, rm);
4671  }
4672
4673  void Vacle(
4674      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4675    VIXL_ASSERT(allow_macro_instructions_);
4676    VIXL_ASSERT(OutsideITBlock());
4677    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4678    ITScope it_scope(this, &cond);
4679    vacle(cond, dt, rd, rn, rm);
4680  }
4681  void Vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4682    Vacle(al, dt, rd, rn, rm);
4683  }
4684
4685  void Vaclt(
4686      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4687    VIXL_ASSERT(allow_macro_instructions_);
4688    VIXL_ASSERT(OutsideITBlock());
4689    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4690    ITScope it_scope(this, &cond);
4691    vaclt(cond, dt, rd, rn, rm);
4692  }
4693  void Vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4694    Vaclt(al, dt, rd, rn, rm);
4695  }
4696
4697  void Vaclt(
4698      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4699    VIXL_ASSERT(allow_macro_instructions_);
4700    VIXL_ASSERT(OutsideITBlock());
4701    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4702    ITScope it_scope(this, &cond);
4703    vaclt(cond, dt, rd, rn, rm);
4704  }
4705  void Vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4706    Vaclt(al, dt, rd, rn, rm);
4707  }
4708
4709  void Vadd(
4710      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4711    VIXL_ASSERT(allow_macro_instructions_);
4712    VIXL_ASSERT(OutsideITBlock());
4713    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4714    ITScope it_scope(this, &cond);
4715    vadd(cond, dt, rd, rn, rm);
4716  }
4717  void Vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4718    Vadd(al, dt, rd, rn, rm);
4719  }
4720
4721  void Vadd(
4722      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4723    VIXL_ASSERT(allow_macro_instructions_);
4724    VIXL_ASSERT(OutsideITBlock());
4725    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4726    ITScope it_scope(this, &cond);
4727    vadd(cond, dt, rd, rn, rm);
4728  }
4729  void Vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4730    Vadd(al, dt, rd, rn, rm);
4731  }
4732
4733  void Vadd(
4734      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4735    VIXL_ASSERT(allow_macro_instructions_);
4736    VIXL_ASSERT(OutsideITBlock());
4737    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4738    ITScope it_scope(this, &cond);
4739    vadd(cond, dt, rd, rn, rm);
4740  }
4741  void Vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4742    Vadd(al, dt, rd, rn, rm);
4743  }
4744
4745  void Vaddhn(
4746      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
4747    VIXL_ASSERT(allow_macro_instructions_);
4748    VIXL_ASSERT(OutsideITBlock());
4749    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4750    ITScope it_scope(this, &cond);
4751    vaddhn(cond, dt, rd, rn, rm);
4752  }
4753  void Vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
4754    Vaddhn(al, dt, rd, rn, rm);
4755  }
4756
4757  void Vaddl(
4758      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4759    VIXL_ASSERT(allow_macro_instructions_);
4760    VIXL_ASSERT(OutsideITBlock());
4761    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4762    ITScope it_scope(this, &cond);
4763    vaddl(cond, dt, rd, rn, rm);
4764  }
4765  void Vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4766    Vaddl(al, dt, rd, rn, rm);
4767  }
4768
4769  void Vaddw(
4770      Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
4771    VIXL_ASSERT(allow_macro_instructions_);
4772    VIXL_ASSERT(OutsideITBlock());
4773    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4774    ITScope it_scope(this, &cond);
4775    vaddw(cond, dt, rd, rn, rm);
4776  }
4777  void Vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
4778    Vaddw(al, dt, rd, rn, rm);
4779  }
4780
4781  void Vand(Condition cond,
4782            DataType dt,
4783            DRegister rd,
4784            DRegister rn,
4785            const DOperand& operand) {
4786    VIXL_ASSERT(allow_macro_instructions_);
4787    VIXL_ASSERT(OutsideITBlock());
4788    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4789    ITScope it_scope(this, &cond);
4790    vand(cond, dt, rd, rn, operand);
4791  }
4792  void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
4793    Vand(al, dt, rd, rn, operand);
4794  }
4795
4796  void Vand(Condition cond,
4797            DataType dt,
4798            QRegister rd,
4799            QRegister rn,
4800            const QOperand& operand) {
4801    VIXL_ASSERT(allow_macro_instructions_);
4802    VIXL_ASSERT(OutsideITBlock());
4803    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4804    ITScope it_scope(this, &cond);
4805    vand(cond, dt, rd, rn, operand);
4806  }
4807  void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
4808    Vand(al, dt, rd, rn, operand);
4809  }
4810
4811  void Vbic(Condition cond,
4812            DataType dt,
4813            DRegister rd,
4814            DRegister rn,
4815            const DOperand& operand) {
4816    VIXL_ASSERT(allow_macro_instructions_);
4817    VIXL_ASSERT(OutsideITBlock());
4818    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4819    ITScope it_scope(this, &cond);
4820    vbic(cond, dt, rd, rn, operand);
4821  }
4822  void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
4823    Vbic(al, dt, rd, rn, operand);
4824  }
4825
4826  void Vbic(Condition cond,
4827            DataType dt,
4828            QRegister rd,
4829            QRegister rn,
4830            const QOperand& operand) {
4831    VIXL_ASSERT(allow_macro_instructions_);
4832    VIXL_ASSERT(OutsideITBlock());
4833    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4834    ITScope it_scope(this, &cond);
4835    vbic(cond, dt, rd, rn, operand);
4836  }
4837  void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
4838    Vbic(al, dt, rd, rn, operand);
4839  }
4840
4841  void Vbif(
4842      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4843    VIXL_ASSERT(allow_macro_instructions_);
4844    VIXL_ASSERT(OutsideITBlock());
4845    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4846    ITScope it_scope(this, &cond);
4847    vbif(cond, dt, rd, rn, rm);
4848  }
4849  void Vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4850    Vbif(al, dt, rd, rn, rm);
4851  }
4852  void Vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
4853    Vbif(cond, kDataTypeValueNone, rd, rn, rm);
4854  }
4855  void Vbif(DRegister rd, DRegister rn, DRegister rm) {
4856    Vbif(al, kDataTypeValueNone, rd, rn, rm);
4857  }
4858
4859  void Vbif(
4860      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4861    VIXL_ASSERT(allow_macro_instructions_);
4862    VIXL_ASSERT(OutsideITBlock());
4863    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4864    ITScope it_scope(this, &cond);
4865    vbif(cond, dt, rd, rn, rm);
4866  }
4867  void Vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4868    Vbif(al, dt, rd, rn, rm);
4869  }
4870  void Vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
4871    Vbif(cond, kDataTypeValueNone, rd, rn, rm);
4872  }
4873  void Vbif(QRegister rd, QRegister rn, QRegister rm) {
4874    Vbif(al, kDataTypeValueNone, rd, rn, rm);
4875  }
4876
4877  void Vbit(
4878      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4879    VIXL_ASSERT(allow_macro_instructions_);
4880    VIXL_ASSERT(OutsideITBlock());
4881    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4882    ITScope it_scope(this, &cond);
4883    vbit(cond, dt, rd, rn, rm);
4884  }
4885  void Vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4886    Vbit(al, dt, rd, rn, rm);
4887  }
4888  void Vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
4889    Vbit(cond, kDataTypeValueNone, rd, rn, rm);
4890  }
4891  void Vbit(DRegister rd, DRegister rn, DRegister rm) {
4892    Vbit(al, kDataTypeValueNone, rd, rn, rm);
4893  }
4894
4895  void Vbit(
4896      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4897    VIXL_ASSERT(allow_macro_instructions_);
4898    VIXL_ASSERT(OutsideITBlock());
4899    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4900    ITScope it_scope(this, &cond);
4901    vbit(cond, dt, rd, rn, rm);
4902  }
4903  void Vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4904    Vbit(al, dt, rd, rn, rm);
4905  }
4906  void Vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
4907    Vbit(cond, kDataTypeValueNone, rd, rn, rm);
4908  }
4909  void Vbit(QRegister rd, QRegister rn, QRegister rm) {
4910    Vbit(al, kDataTypeValueNone, rd, rn, rm);
4911  }
4912
4913  void Vbsl(
4914      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4915    VIXL_ASSERT(allow_macro_instructions_);
4916    VIXL_ASSERT(OutsideITBlock());
4917    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4918    ITScope it_scope(this, &cond);
4919    vbsl(cond, dt, rd, rn, rm);
4920  }
4921  void Vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4922    Vbsl(al, dt, rd, rn, rm);
4923  }
4924  void Vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
4925    Vbsl(cond, kDataTypeValueNone, rd, rn, rm);
4926  }
4927  void Vbsl(DRegister rd, DRegister rn, DRegister rm) {
4928    Vbsl(al, kDataTypeValueNone, rd, rn, rm);
4929  }
4930
4931  void Vbsl(
4932      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4933    VIXL_ASSERT(allow_macro_instructions_);
4934    VIXL_ASSERT(OutsideITBlock());
4935    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4936    ITScope it_scope(this, &cond);
4937    vbsl(cond, dt, rd, rn, rm);
4938  }
4939  void Vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4940    Vbsl(al, dt, rd, rn, rm);
4941  }
4942  void Vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
4943    Vbsl(cond, kDataTypeValueNone, rd, rn, rm);
4944  }
4945  void Vbsl(QRegister rd, QRegister rn, QRegister rm) {
4946    Vbsl(al, kDataTypeValueNone, rd, rn, rm);
4947  }
4948
4949  void Vceq(Condition cond,
4950            DataType dt,
4951            DRegister rd,
4952            DRegister rm,
4953            const DOperand& operand) {
4954    VIXL_ASSERT(allow_macro_instructions_);
4955    VIXL_ASSERT(OutsideITBlock());
4956    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4957    ITScope it_scope(this, &cond);
4958    vceq(cond, dt, rd, rm, operand);
4959  }
4960  void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
4961    Vceq(al, dt, rd, rm, operand);
4962  }
4963
4964  void Vceq(Condition cond,
4965            DataType dt,
4966            QRegister rd,
4967            QRegister rm,
4968            const QOperand& operand) {
4969    VIXL_ASSERT(allow_macro_instructions_);
4970    VIXL_ASSERT(OutsideITBlock());
4971    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4972    ITScope it_scope(this, &cond);
4973    vceq(cond, dt, rd, rm, operand);
4974  }
4975  void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
4976    Vceq(al, dt, rd, rm, operand);
4977  }
4978
4979  void Vceq(
4980      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4981    VIXL_ASSERT(allow_macro_instructions_);
4982    VIXL_ASSERT(OutsideITBlock());
4983    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4984    ITScope it_scope(this, &cond);
4985    vceq(cond, dt, rd, rn, rm);
4986  }
4987  void Vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4988    Vceq(al, dt, rd, rn, rm);
4989  }
4990
4991  void Vceq(
4992      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4993    VIXL_ASSERT(allow_macro_instructions_);
4994    VIXL_ASSERT(OutsideITBlock());
4995    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
4996    ITScope it_scope(this, &cond);
4997    vceq(cond, dt, rd, rn, rm);
4998  }
4999  void Vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5000    Vceq(al, dt, rd, rn, rm);
5001  }
5002
5003  void Vcge(Condition cond,
5004            DataType dt,
5005            DRegister rd,
5006            DRegister rm,
5007            const DOperand& operand) {
5008    VIXL_ASSERT(allow_macro_instructions_);
5009    VIXL_ASSERT(OutsideITBlock());
5010    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5011    ITScope it_scope(this, &cond);
5012    vcge(cond, dt, rd, rm, operand);
5013  }
5014  void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5015    Vcge(al, dt, rd, rm, operand);
5016  }
5017
5018  void Vcge(Condition cond,
5019            DataType dt,
5020            QRegister rd,
5021            QRegister rm,
5022            const QOperand& operand) {
5023    VIXL_ASSERT(allow_macro_instructions_);
5024    VIXL_ASSERT(OutsideITBlock());
5025    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5026    ITScope it_scope(this, &cond);
5027    vcge(cond, dt, rd, rm, operand);
5028  }
5029  void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5030    Vcge(al, dt, rd, rm, operand);
5031  }
5032
5033  void Vcge(
5034      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5035    VIXL_ASSERT(allow_macro_instructions_);
5036    VIXL_ASSERT(OutsideITBlock());
5037    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5038    ITScope it_scope(this, &cond);
5039    vcge(cond, dt, rd, rn, rm);
5040  }
5041  void Vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5042    Vcge(al, dt, rd, rn, rm);
5043  }
5044
5045  void Vcge(
5046      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5047    VIXL_ASSERT(allow_macro_instructions_);
5048    VIXL_ASSERT(OutsideITBlock());
5049    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5050    ITScope it_scope(this, &cond);
5051    vcge(cond, dt, rd, rn, rm);
5052  }
5053  void Vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5054    Vcge(al, dt, rd, rn, rm);
5055  }
5056
5057  void Vcgt(Condition cond,
5058            DataType dt,
5059            DRegister rd,
5060            DRegister rm,
5061            const DOperand& operand) {
5062    VIXL_ASSERT(allow_macro_instructions_);
5063    VIXL_ASSERT(OutsideITBlock());
5064    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5065    ITScope it_scope(this, &cond);
5066    vcgt(cond, dt, rd, rm, operand);
5067  }
5068  void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5069    Vcgt(al, dt, rd, rm, operand);
5070  }
5071
5072  void Vcgt(Condition cond,
5073            DataType dt,
5074            QRegister rd,
5075            QRegister rm,
5076            const QOperand& operand) {
5077    VIXL_ASSERT(allow_macro_instructions_);
5078    VIXL_ASSERT(OutsideITBlock());
5079    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5080    ITScope it_scope(this, &cond);
5081    vcgt(cond, dt, rd, rm, operand);
5082  }
5083  void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5084    Vcgt(al, dt, rd, rm, operand);
5085  }
5086
5087  void Vcgt(
5088      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5089    VIXL_ASSERT(allow_macro_instructions_);
5090    VIXL_ASSERT(OutsideITBlock());
5091    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5092    ITScope it_scope(this, &cond);
5093    vcgt(cond, dt, rd, rn, rm);
5094  }
5095  void Vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5096    Vcgt(al, dt, rd, rn, rm);
5097  }
5098
5099  void Vcgt(
5100      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5101    VIXL_ASSERT(allow_macro_instructions_);
5102    VIXL_ASSERT(OutsideITBlock());
5103    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5104    ITScope it_scope(this, &cond);
5105    vcgt(cond, dt, rd, rn, rm);
5106  }
5107  void Vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5108    Vcgt(al, dt, rd, rn, rm);
5109  }
5110
5111  void Vcle(Condition cond,
5112            DataType dt,
5113            DRegister rd,
5114            DRegister rm,
5115            const DOperand& operand) {
5116    VIXL_ASSERT(allow_macro_instructions_);
5117    VIXL_ASSERT(OutsideITBlock());
5118    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5119    ITScope it_scope(this, &cond);
5120    vcle(cond, dt, rd, rm, operand);
5121  }
5122  void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5123    Vcle(al, dt, rd, rm, operand);
5124  }
5125
5126  void Vcle(Condition cond,
5127            DataType dt,
5128            QRegister rd,
5129            QRegister rm,
5130            const QOperand& operand) {
5131    VIXL_ASSERT(allow_macro_instructions_);
5132    VIXL_ASSERT(OutsideITBlock());
5133    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5134    ITScope it_scope(this, &cond);
5135    vcle(cond, dt, rd, rm, operand);
5136  }
5137  void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5138    Vcle(al, dt, rd, rm, operand);
5139  }
5140
5141  void Vcle(
5142      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5143    VIXL_ASSERT(allow_macro_instructions_);
5144    VIXL_ASSERT(OutsideITBlock());
5145    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5146    ITScope it_scope(this, &cond);
5147    vcle(cond, dt, rd, rn, rm);
5148  }
5149  void Vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5150    Vcle(al, dt, rd, rn, rm);
5151  }
5152
5153  void Vcle(
5154      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5155    VIXL_ASSERT(allow_macro_instructions_);
5156    VIXL_ASSERT(OutsideITBlock());
5157    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5158    ITScope it_scope(this, &cond);
5159    vcle(cond, dt, rd, rn, rm);
5160  }
5161  void Vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5162    Vcle(al, dt, rd, rn, rm);
5163  }
5164
5165  void Vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {
5166    VIXL_ASSERT(allow_macro_instructions_);
5167    VIXL_ASSERT(OutsideITBlock());
5168    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5169    ITScope it_scope(this, &cond);
5170    vcls(cond, dt, rd, rm);
5171  }
5172  void Vcls(DataType dt, DRegister rd, DRegister rm) { Vcls(al, dt, rd, rm); }
5173
5174  void Vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {
5175    VIXL_ASSERT(allow_macro_instructions_);
5176    VIXL_ASSERT(OutsideITBlock());
5177    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5178    ITScope it_scope(this, &cond);
5179    vcls(cond, dt, rd, rm);
5180  }
5181  void Vcls(DataType dt, QRegister rd, QRegister rm) { Vcls(al, dt, rd, rm); }
5182
5183  void Vclt(Condition cond,
5184            DataType dt,
5185            DRegister rd,
5186            DRegister rm,
5187            const DOperand& operand) {
5188    VIXL_ASSERT(allow_macro_instructions_);
5189    VIXL_ASSERT(OutsideITBlock());
5190    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5191    ITScope it_scope(this, &cond);
5192    vclt(cond, dt, rd, rm, operand);
5193  }
5194  void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5195    Vclt(al, dt, rd, rm, operand);
5196  }
5197
5198  void Vclt(Condition cond,
5199            DataType dt,
5200            QRegister rd,
5201            QRegister rm,
5202            const QOperand& operand) {
5203    VIXL_ASSERT(allow_macro_instructions_);
5204    VIXL_ASSERT(OutsideITBlock());
5205    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5206    ITScope it_scope(this, &cond);
5207    vclt(cond, dt, rd, rm, operand);
5208  }
5209  void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5210    Vclt(al, dt, rd, rm, operand);
5211  }
5212
5213  void Vclt(
5214      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5215    VIXL_ASSERT(allow_macro_instructions_);
5216    VIXL_ASSERT(OutsideITBlock());
5217    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5218    ITScope it_scope(this, &cond);
5219    vclt(cond, dt, rd, rn, rm);
5220  }
5221  void Vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5222    Vclt(al, dt, rd, rn, rm);
5223  }
5224
5225  void Vclt(
5226      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5227    VIXL_ASSERT(allow_macro_instructions_);
5228    VIXL_ASSERT(OutsideITBlock());
5229    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5230    ITScope it_scope(this, &cond);
5231    vclt(cond, dt, rd, rn, rm);
5232  }
5233  void Vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5234    Vclt(al, dt, rd, rn, rm);
5235  }
5236
5237  void Vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {
5238    VIXL_ASSERT(allow_macro_instructions_);
5239    VIXL_ASSERT(OutsideITBlock());
5240    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5241    ITScope it_scope(this, &cond);
5242    vclz(cond, dt, rd, rm);
5243  }
5244  void Vclz(DataType dt, DRegister rd, DRegister rm) { Vclz(al, dt, rd, rm); }
5245
5246  void Vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {
5247    VIXL_ASSERT(allow_macro_instructions_);
5248    VIXL_ASSERT(OutsideITBlock());
5249    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5250    ITScope it_scope(this, &cond);
5251    vclz(cond, dt, rd, rm);
5252  }
5253  void Vclz(DataType dt, QRegister rd, QRegister rm) { Vclz(al, dt, rd, rm); }
5254
5255  void Vcmp(Condition cond, DataType dt, SRegister rd, SRegister rm) {
5256    VIXL_ASSERT(allow_macro_instructions_);
5257    VIXL_ASSERT(OutsideITBlock());
5258    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5259    ITScope it_scope(this, &cond);
5260    vcmp(cond, dt, rd, rm);
5261  }
5262  void Vcmp(DataType dt, SRegister rd, SRegister rm) { Vcmp(al, dt, rd, rm); }
5263
5264  void Vcmp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
5265    VIXL_ASSERT(allow_macro_instructions_);
5266    VIXL_ASSERT(OutsideITBlock());
5267    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5268    ITScope it_scope(this, &cond);
5269    vcmp(cond, dt, rd, rm);
5270  }
5271  void Vcmp(DataType dt, DRegister rd, DRegister rm) { Vcmp(al, dt, rd, rm); }
5272
5273  void Vcmp(Condition cond, DataType dt, SRegister rd, double imm) {
5274    VIXL_ASSERT(allow_macro_instructions_);
5275    VIXL_ASSERT(OutsideITBlock());
5276    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5277    ITScope it_scope(this, &cond);
5278    vcmp(cond, dt, rd, imm);
5279  }
5280  void Vcmp(DataType dt, SRegister rd, double imm) { Vcmp(al, dt, rd, imm); }
5281
5282  void Vcmp(Condition cond, DataType dt, DRegister rd, double imm) {
5283    VIXL_ASSERT(allow_macro_instructions_);
5284    VIXL_ASSERT(OutsideITBlock());
5285    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5286    ITScope it_scope(this, &cond);
5287    vcmp(cond, dt, rd, imm);
5288  }
5289  void Vcmp(DataType dt, DRegister rd, double imm) { Vcmp(al, dt, rd, imm); }
5290
5291  void Vcmpe(Condition cond, DataType dt, SRegister rd, SRegister rm) {
5292    VIXL_ASSERT(allow_macro_instructions_);
5293    VIXL_ASSERT(OutsideITBlock());
5294    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5295    ITScope it_scope(this, &cond);
5296    vcmpe(cond, dt, rd, rm);
5297  }
5298  void Vcmpe(DataType dt, SRegister rd, SRegister rm) { Vcmpe(al, dt, rd, rm); }
5299
5300  void Vcmpe(Condition cond, DataType dt, DRegister rd, DRegister rm) {
5301    VIXL_ASSERT(allow_macro_instructions_);
5302    VIXL_ASSERT(OutsideITBlock());
5303    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5304    ITScope it_scope(this, &cond);
5305    vcmpe(cond, dt, rd, rm);
5306  }
5307  void Vcmpe(DataType dt, DRegister rd, DRegister rm) { Vcmpe(al, dt, rd, rm); }
5308
5309  void Vcmpe(Condition cond, DataType dt, SRegister rd, double imm) {
5310    VIXL_ASSERT(allow_macro_instructions_);
5311    VIXL_ASSERT(OutsideITBlock());
5312    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5313    ITScope it_scope(this, &cond);
5314    vcmpe(cond, dt, rd, imm);
5315  }
5316  void Vcmpe(DataType dt, SRegister rd, double imm) { Vcmpe(al, dt, rd, imm); }
5317
5318  void Vcmpe(Condition cond, DataType dt, DRegister rd, double imm) {
5319    VIXL_ASSERT(allow_macro_instructions_);
5320    VIXL_ASSERT(OutsideITBlock());
5321    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5322    ITScope it_scope(this, &cond);
5323    vcmpe(cond, dt, rd, imm);
5324  }
5325  void Vcmpe(DataType dt, DRegister rd, double imm) { Vcmpe(al, dt, rd, imm); }
5326
5327  void Vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
5328    VIXL_ASSERT(allow_macro_instructions_);
5329    VIXL_ASSERT(OutsideITBlock());
5330    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5331    ITScope it_scope(this, &cond);
5332    vcnt(cond, dt, rd, rm);
5333  }
5334  void Vcnt(DataType dt, DRegister rd, DRegister rm) { Vcnt(al, dt, rd, rm); }
5335
5336  void Vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {
5337    VIXL_ASSERT(allow_macro_instructions_);
5338    VIXL_ASSERT(OutsideITBlock());
5339    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5340    ITScope it_scope(this, &cond);
5341    vcnt(cond, dt, rd, rm);
5342  }
5343  void Vcnt(DataType dt, QRegister rd, QRegister rm) { Vcnt(al, dt, rd, rm); }
5344
5345  void Vcvt(
5346      Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
5347    VIXL_ASSERT(allow_macro_instructions_);
5348    VIXL_ASSERT(OutsideITBlock());
5349    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5350    ITScope it_scope(this, &cond);
5351    vcvt(cond, dt1, dt2, rd, rm);
5352  }
5353  void Vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
5354    Vcvt(al, dt1, dt2, rd, rm);
5355  }
5356
5357  void Vcvt(
5358      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5359    VIXL_ASSERT(allow_macro_instructions_);
5360    VIXL_ASSERT(OutsideITBlock());
5361    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5362    ITScope it_scope(this, &cond);
5363    vcvt(cond, dt1, dt2, rd, rm);
5364  }
5365  void Vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5366    Vcvt(al, dt1, dt2, rd, rm);
5367  }
5368
5369  void Vcvt(Condition cond,
5370            DataType dt1,
5371            DataType dt2,
5372            DRegister rd,
5373            DRegister rm,
5374            int32_t fbits) {
5375    VIXL_ASSERT(allow_macro_instructions_);
5376    VIXL_ASSERT(OutsideITBlock());
5377    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5378    ITScope it_scope(this, &cond);
5379    vcvt(cond, dt1, dt2, rd, rm, fbits);
5380  }
5381  void Vcvt(
5382      DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) {
5383    Vcvt(al, dt1, dt2, rd, rm, fbits);
5384  }
5385
5386  void Vcvt(Condition cond,
5387            DataType dt1,
5388            DataType dt2,
5389            QRegister rd,
5390            QRegister rm,
5391            int32_t fbits) {
5392    VIXL_ASSERT(allow_macro_instructions_);
5393    VIXL_ASSERT(OutsideITBlock());
5394    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5395    ITScope it_scope(this, &cond);
5396    vcvt(cond, dt1, dt2, rd, rm, fbits);
5397  }
5398  void Vcvt(
5399      DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) {
5400    Vcvt(al, dt1, dt2, rd, rm, fbits);
5401  }
5402
5403  void Vcvt(Condition cond,
5404            DataType dt1,
5405            DataType dt2,
5406            SRegister rd,
5407            SRegister rm,
5408            int32_t fbits) {
5409    VIXL_ASSERT(allow_macro_instructions_);
5410    VIXL_ASSERT(OutsideITBlock());
5411    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5412    ITScope it_scope(this, &cond);
5413    vcvt(cond, dt1, dt2, rd, rm, fbits);
5414  }
5415  void Vcvt(
5416      DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) {
5417    Vcvt(al, dt1, dt2, rd, rm, fbits);
5418  }
5419
5420  void Vcvt(
5421      Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
5422    VIXL_ASSERT(allow_macro_instructions_);
5423    VIXL_ASSERT(OutsideITBlock());
5424    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5425    ITScope it_scope(this, &cond);
5426    vcvt(cond, dt1, dt2, rd, rm);
5427  }
5428  void Vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
5429    Vcvt(al, dt1, dt2, rd, rm);
5430  }
5431
5432  void Vcvt(
5433      Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
5434    VIXL_ASSERT(allow_macro_instructions_);
5435    VIXL_ASSERT(OutsideITBlock());
5436    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5437    ITScope it_scope(this, &cond);
5438    vcvt(cond, dt1, dt2, rd, rm);
5439  }
5440  void Vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
5441    Vcvt(al, dt1, dt2, rd, rm);
5442  }
5443
5444  void Vcvt(
5445      Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
5446    VIXL_ASSERT(allow_macro_instructions_);
5447    VIXL_ASSERT(OutsideITBlock());
5448    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5449    ITScope it_scope(this, &cond);
5450    vcvt(cond, dt1, dt2, rd, rm);
5451  }
5452  void Vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
5453    Vcvt(al, dt1, dt2, rd, rm);
5454  }
5455
5456  void Vcvt(
5457      Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
5458    VIXL_ASSERT(allow_macro_instructions_);
5459    VIXL_ASSERT(OutsideITBlock());
5460    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5461    ITScope it_scope(this, &cond);
5462    vcvt(cond, dt1, dt2, rd, rm);
5463  }
5464  void Vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
5465    Vcvt(al, dt1, dt2, rd, rm);
5466  }
5467
5468  void Vcvt(
5469      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5470    VIXL_ASSERT(allow_macro_instructions_);
5471    VIXL_ASSERT(OutsideITBlock());
5472    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5473    ITScope it_scope(this, &cond);
5474    vcvt(cond, dt1, dt2, rd, rm);
5475  }
5476  void Vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5477    Vcvt(al, dt1, dt2, rd, rm);
5478  }
5479
5480  void Vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
5481    VIXL_ASSERT(allow_macro_instructions_);
5482    VIXL_ASSERT(OutsideITBlock());
5483    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5484    vcvta(dt1, dt2, rd, rm);
5485  }
5486
5487  void Vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
5488    VIXL_ASSERT(allow_macro_instructions_);
5489    VIXL_ASSERT(OutsideITBlock());
5490    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5491    vcvta(dt1, dt2, rd, rm);
5492  }
5493
5494  void Vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5495    VIXL_ASSERT(allow_macro_instructions_);
5496    VIXL_ASSERT(OutsideITBlock());
5497    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5498    vcvta(dt1, dt2, rd, rm);
5499  }
5500
5501  void Vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5502    VIXL_ASSERT(allow_macro_instructions_);
5503    VIXL_ASSERT(OutsideITBlock());
5504    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5505    vcvta(dt1, dt2, rd, rm);
5506  }
5507
5508  void Vcvtb(
5509      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5510    VIXL_ASSERT(allow_macro_instructions_);
5511    VIXL_ASSERT(OutsideITBlock());
5512    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5513    ITScope it_scope(this, &cond);
5514    vcvtb(cond, dt1, dt2, rd, rm);
5515  }
5516  void Vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5517    Vcvtb(al, dt1, dt2, rd, rm);
5518  }
5519
5520  void Vcvtb(
5521      Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
5522    VIXL_ASSERT(allow_macro_instructions_);
5523    VIXL_ASSERT(OutsideITBlock());
5524    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5525    ITScope it_scope(this, &cond);
5526    vcvtb(cond, dt1, dt2, rd, rm);
5527  }
5528  void Vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
5529    Vcvtb(al, dt1, dt2, rd, rm);
5530  }
5531
5532  void Vcvtb(
5533      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5534    VIXL_ASSERT(allow_macro_instructions_);
5535    VIXL_ASSERT(OutsideITBlock());
5536    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5537    ITScope it_scope(this, &cond);
5538    vcvtb(cond, dt1, dt2, rd, rm);
5539  }
5540  void Vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5541    Vcvtb(al, dt1, dt2, rd, rm);
5542  }
5543
5544  void Vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
5545    VIXL_ASSERT(allow_macro_instructions_);
5546    VIXL_ASSERT(OutsideITBlock());
5547    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5548    vcvtm(dt1, dt2, rd, rm);
5549  }
5550
5551  void Vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
5552    VIXL_ASSERT(allow_macro_instructions_);
5553    VIXL_ASSERT(OutsideITBlock());
5554    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5555    vcvtm(dt1, dt2, rd, rm);
5556  }
5557
5558  void Vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5559    VIXL_ASSERT(allow_macro_instructions_);
5560    VIXL_ASSERT(OutsideITBlock());
5561    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5562    vcvtm(dt1, dt2, rd, rm);
5563  }
5564
5565  void Vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5566    VIXL_ASSERT(allow_macro_instructions_);
5567    VIXL_ASSERT(OutsideITBlock());
5568    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5569    vcvtm(dt1, dt2, rd, rm);
5570  }
5571
5572  void Vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
5573    VIXL_ASSERT(allow_macro_instructions_);
5574    VIXL_ASSERT(OutsideITBlock());
5575    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5576    vcvtn(dt1, dt2, rd, rm);
5577  }
5578
5579  void Vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
5580    VIXL_ASSERT(allow_macro_instructions_);
5581    VIXL_ASSERT(OutsideITBlock());
5582    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5583    vcvtn(dt1, dt2, rd, rm);
5584  }
5585
5586  void Vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5587    VIXL_ASSERT(allow_macro_instructions_);
5588    VIXL_ASSERT(OutsideITBlock());
5589    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5590    vcvtn(dt1, dt2, rd, rm);
5591  }
5592
5593  void Vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5594    VIXL_ASSERT(allow_macro_instructions_);
5595    VIXL_ASSERT(OutsideITBlock());
5596    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5597    vcvtn(dt1, dt2, rd, rm);
5598  }
5599
5600  void Vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
5601    VIXL_ASSERT(allow_macro_instructions_);
5602    VIXL_ASSERT(OutsideITBlock());
5603    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5604    vcvtp(dt1, dt2, rd, rm);
5605  }
5606
5607  void Vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
5608    VIXL_ASSERT(allow_macro_instructions_);
5609    VIXL_ASSERT(OutsideITBlock());
5610    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5611    vcvtp(dt1, dt2, rd, rm);
5612  }
5613
5614  void Vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5615    VIXL_ASSERT(allow_macro_instructions_);
5616    VIXL_ASSERT(OutsideITBlock());
5617    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5618    vcvtp(dt1, dt2, rd, rm);
5619  }
5620
5621  void Vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5622    VIXL_ASSERT(allow_macro_instructions_);
5623    VIXL_ASSERT(OutsideITBlock());
5624    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5625    vcvtp(dt1, dt2, rd, rm);
5626  }
5627
5628  void Vcvtr(
5629      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5630    VIXL_ASSERT(allow_macro_instructions_);
5631    VIXL_ASSERT(OutsideITBlock());
5632    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5633    ITScope it_scope(this, &cond);
5634    vcvtr(cond, dt1, dt2, rd, rm);
5635  }
5636  void Vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5637    Vcvtr(al, dt1, dt2, rd, rm);
5638  }
5639
5640  void Vcvtr(
5641      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5642    VIXL_ASSERT(allow_macro_instructions_);
5643    VIXL_ASSERT(OutsideITBlock());
5644    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5645    ITScope it_scope(this, &cond);
5646    vcvtr(cond, dt1, dt2, rd, rm);
5647  }
5648  void Vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5649    Vcvtr(al, dt1, dt2, rd, rm);
5650  }
5651
5652  void Vcvtt(
5653      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5654    VIXL_ASSERT(allow_macro_instructions_);
5655    VIXL_ASSERT(OutsideITBlock());
5656    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5657    ITScope it_scope(this, &cond);
5658    vcvtt(cond, dt1, dt2, rd, rm);
5659  }
5660  void Vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
5661    Vcvtt(al, dt1, dt2, rd, rm);
5662  }
5663
5664  void Vcvtt(
5665      Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
5666    VIXL_ASSERT(allow_macro_instructions_);
5667    VIXL_ASSERT(OutsideITBlock());
5668    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5669    ITScope it_scope(this, &cond);
5670    vcvtt(cond, dt1, dt2, rd, rm);
5671  }
5672  void Vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
5673    Vcvtt(al, dt1, dt2, rd, rm);
5674  }
5675
5676  void Vcvtt(
5677      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5678    VIXL_ASSERT(allow_macro_instructions_);
5679    VIXL_ASSERT(OutsideITBlock());
5680    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5681    ITScope it_scope(this, &cond);
5682    vcvtt(cond, dt1, dt2, rd, rm);
5683  }
5684  void Vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
5685    Vcvtt(al, dt1, dt2, rd, rm);
5686  }
5687
5688  void Vdiv(
5689      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5690    VIXL_ASSERT(allow_macro_instructions_);
5691    VIXL_ASSERT(OutsideITBlock());
5692    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5693    ITScope it_scope(this, &cond);
5694    vdiv(cond, dt, rd, rn, rm);
5695  }
5696  void Vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5697    Vdiv(al, dt, rd, rn, rm);
5698  }
5699
5700  void Vdiv(
5701      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5702    VIXL_ASSERT(allow_macro_instructions_);
5703    VIXL_ASSERT(OutsideITBlock());
5704    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5705    ITScope it_scope(this, &cond);
5706    vdiv(cond, dt, rd, rn, rm);
5707  }
5708  void Vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5709    Vdiv(al, dt, rd, rn, rm);
5710  }
5711
5712  void Vdup(Condition cond, DataType dt, QRegister rd, Register rt) {
5713    VIXL_ASSERT(allow_macro_instructions_);
5714    VIXL_ASSERT(OutsideITBlock());
5715    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5716    ITScope it_scope(this, &cond);
5717    vdup(cond, dt, rd, rt);
5718  }
5719  void Vdup(DataType dt, QRegister rd, Register rt) { Vdup(al, dt, rd, rt); }
5720
5721  void Vdup(Condition cond, DataType dt, DRegister rd, Register rt) {
5722    VIXL_ASSERT(allow_macro_instructions_);
5723    VIXL_ASSERT(OutsideITBlock());
5724    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5725    ITScope it_scope(this, &cond);
5726    vdup(cond, dt, rd, rt);
5727  }
5728  void Vdup(DataType dt, DRegister rd, Register rt) { Vdup(al, dt, rd, rt); }
5729
5730  void Vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm) {
5731    VIXL_ASSERT(allow_macro_instructions_);
5732    VIXL_ASSERT(OutsideITBlock());
5733    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5734    ITScope it_scope(this, &cond);
5735    vdup(cond, dt, rd, rm);
5736  }
5737  void Vdup(DataType dt, DRegister rd, DRegisterLane rm) {
5738    Vdup(al, dt, rd, rm);
5739  }
5740
5741  void Vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm) {
5742    VIXL_ASSERT(allow_macro_instructions_);
5743    VIXL_ASSERT(OutsideITBlock());
5744    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5745    ITScope it_scope(this, &cond);
5746    vdup(cond, dt, rd, rm);
5747  }
5748  void Vdup(DataType dt, QRegister rd, DRegisterLane rm) {
5749    Vdup(al, dt, rd, rm);
5750  }
5751
5752  void Veor(
5753      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5754    VIXL_ASSERT(allow_macro_instructions_);
5755    VIXL_ASSERT(OutsideITBlock());
5756    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5757    ITScope it_scope(this, &cond);
5758    veor(cond, dt, rd, rn, rm);
5759  }
5760  void Veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5761    Veor(al, dt, rd, rn, rm);
5762  }
5763  void Veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
5764    Veor(cond, kDataTypeValueNone, rd, rn, rm);
5765  }
5766  void Veor(DRegister rd, DRegister rn, DRegister rm) {
5767    Veor(al, kDataTypeValueNone, rd, rn, rm);
5768  }
5769
5770  void Veor(
5771      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5772    VIXL_ASSERT(allow_macro_instructions_);
5773    VIXL_ASSERT(OutsideITBlock());
5774    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5775    ITScope it_scope(this, &cond);
5776    veor(cond, dt, rd, rn, rm);
5777  }
5778  void Veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5779    Veor(al, dt, rd, rn, rm);
5780  }
5781  void Veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
5782    Veor(cond, kDataTypeValueNone, rd, rn, rm);
5783  }
5784  void Veor(QRegister rd, QRegister rn, QRegister rm) {
5785    Veor(al, kDataTypeValueNone, rd, rn, rm);
5786  }
5787
5788  void Vext(Condition cond,
5789            DataType dt,
5790            DRegister rd,
5791            DRegister rn,
5792            DRegister rm,
5793            const DOperand& operand) {
5794    VIXL_ASSERT(allow_macro_instructions_);
5795    VIXL_ASSERT(OutsideITBlock());
5796    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5797    ITScope it_scope(this, &cond);
5798    vext(cond, dt, rd, rn, rm, operand);
5799  }
5800  void Vext(DataType dt,
5801            DRegister rd,
5802            DRegister rn,
5803            DRegister rm,
5804            const DOperand& operand) {
5805    Vext(al, dt, rd, rn, rm, operand);
5806  }
5807
5808  void Vext(Condition cond,
5809            DataType dt,
5810            QRegister rd,
5811            QRegister rn,
5812            QRegister rm,
5813            const QOperand& operand) {
5814    VIXL_ASSERT(allow_macro_instructions_);
5815    VIXL_ASSERT(OutsideITBlock());
5816    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5817    ITScope it_scope(this, &cond);
5818    vext(cond, dt, rd, rn, rm, operand);
5819  }
5820  void Vext(DataType dt,
5821            QRegister rd,
5822            QRegister rn,
5823            QRegister rm,
5824            const QOperand& operand) {
5825    Vext(al, dt, rd, rn, rm, operand);
5826  }
5827
5828  void Vfma(
5829      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5830    VIXL_ASSERT(allow_macro_instructions_);
5831    VIXL_ASSERT(OutsideITBlock());
5832    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5833    ITScope it_scope(this, &cond);
5834    vfma(cond, dt, rd, rn, rm);
5835  }
5836  void Vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5837    Vfma(al, dt, rd, rn, rm);
5838  }
5839
5840  void Vfma(
5841      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5842    VIXL_ASSERT(allow_macro_instructions_);
5843    VIXL_ASSERT(OutsideITBlock());
5844    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5845    ITScope it_scope(this, &cond);
5846    vfma(cond, dt, rd, rn, rm);
5847  }
5848  void Vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5849    Vfma(al, dt, rd, rn, rm);
5850  }
5851
5852  void Vfma(
5853      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5854    VIXL_ASSERT(allow_macro_instructions_);
5855    VIXL_ASSERT(OutsideITBlock());
5856    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5857    ITScope it_scope(this, &cond);
5858    vfma(cond, dt, rd, rn, rm);
5859  }
5860  void Vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5861    Vfma(al, dt, rd, rn, rm);
5862  }
5863
5864  void Vfms(
5865      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5866    VIXL_ASSERT(allow_macro_instructions_);
5867    VIXL_ASSERT(OutsideITBlock());
5868    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5869    ITScope it_scope(this, &cond);
5870    vfms(cond, dt, rd, rn, rm);
5871  }
5872  void Vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5873    Vfms(al, dt, rd, rn, rm);
5874  }
5875
5876  void Vfms(
5877      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5878    VIXL_ASSERT(allow_macro_instructions_);
5879    VIXL_ASSERT(OutsideITBlock());
5880    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5881    ITScope it_scope(this, &cond);
5882    vfms(cond, dt, rd, rn, rm);
5883  }
5884  void Vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5885    Vfms(al, dt, rd, rn, rm);
5886  }
5887
5888  void Vfms(
5889      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5890    VIXL_ASSERT(allow_macro_instructions_);
5891    VIXL_ASSERT(OutsideITBlock());
5892    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5893    ITScope it_scope(this, &cond);
5894    vfms(cond, dt, rd, rn, rm);
5895  }
5896  void Vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5897    Vfms(al, dt, rd, rn, rm);
5898  }
5899
5900  void Vfnma(
5901      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5902    VIXL_ASSERT(allow_macro_instructions_);
5903    VIXL_ASSERT(OutsideITBlock());
5904    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5905    ITScope it_scope(this, &cond);
5906    vfnma(cond, dt, rd, rn, rm);
5907  }
5908  void Vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5909    Vfnma(al, dt, rd, rn, rm);
5910  }
5911
5912  void Vfnma(
5913      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5914    VIXL_ASSERT(allow_macro_instructions_);
5915    VIXL_ASSERT(OutsideITBlock());
5916    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5917    ITScope it_scope(this, &cond);
5918    vfnma(cond, dt, rd, rn, rm);
5919  }
5920  void Vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5921    Vfnma(al, dt, rd, rn, rm);
5922  }
5923
5924  void Vfnms(
5925      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5926    VIXL_ASSERT(allow_macro_instructions_);
5927    VIXL_ASSERT(OutsideITBlock());
5928    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5929    ITScope it_scope(this, &cond);
5930    vfnms(cond, dt, rd, rn, rm);
5931  }
5932  void Vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5933    Vfnms(al, dt, rd, rn, rm);
5934  }
5935
5936  void Vfnms(
5937      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5938    VIXL_ASSERT(allow_macro_instructions_);
5939    VIXL_ASSERT(OutsideITBlock());
5940    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5941    ITScope it_scope(this, &cond);
5942    vfnms(cond, dt, rd, rn, rm);
5943  }
5944  void Vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5945    Vfnms(al, dt, rd, rn, rm);
5946  }
5947
5948  void Vhadd(
5949      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5950    VIXL_ASSERT(allow_macro_instructions_);
5951    VIXL_ASSERT(OutsideITBlock());
5952    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5953    ITScope it_scope(this, &cond);
5954    vhadd(cond, dt, rd, rn, rm);
5955  }
5956  void Vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5957    Vhadd(al, dt, rd, rn, rm);
5958  }
5959
5960  void Vhadd(
5961      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5962    VIXL_ASSERT(allow_macro_instructions_);
5963    VIXL_ASSERT(OutsideITBlock());
5964    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5965    ITScope it_scope(this, &cond);
5966    vhadd(cond, dt, rd, rn, rm);
5967  }
5968  void Vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5969    Vhadd(al, dt, rd, rn, rm);
5970  }
5971
5972  void Vhsub(
5973      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5974    VIXL_ASSERT(allow_macro_instructions_);
5975    VIXL_ASSERT(OutsideITBlock());
5976    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5977    ITScope it_scope(this, &cond);
5978    vhsub(cond, dt, rd, rn, rm);
5979  }
5980  void Vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5981    Vhsub(al, dt, rd, rn, rm);
5982  }
5983
5984  void Vhsub(
5985      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5986    VIXL_ASSERT(allow_macro_instructions_);
5987    VIXL_ASSERT(OutsideITBlock());
5988    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
5989    ITScope it_scope(this, &cond);
5990    vhsub(cond, dt, rd, rn, rm);
5991  }
5992  void Vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5993    Vhsub(al, dt, rd, rn, rm);
5994  }
5995
5996  void Vld1(Condition cond,
5997            DataType dt,
5998            const NeonRegisterList& nreglist,
5999            const AlignedMemOperand& operand) {
6000    VIXL_ASSERT(allow_macro_instructions_);
6001    VIXL_ASSERT(OutsideITBlock());
6002    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6003    ITScope it_scope(this, &cond);
6004    vld1(cond, dt, nreglist, operand);
6005  }
6006  void Vld1(DataType dt,
6007            const NeonRegisterList& nreglist,
6008            const AlignedMemOperand& operand) {
6009    Vld1(al, dt, nreglist, operand);
6010  }
6011
6012  void Vld2(Condition cond,
6013            DataType dt,
6014            const NeonRegisterList& nreglist,
6015            const AlignedMemOperand& operand) {
6016    VIXL_ASSERT(allow_macro_instructions_);
6017    VIXL_ASSERT(OutsideITBlock());
6018    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6019    ITScope it_scope(this, &cond);
6020    vld2(cond, dt, nreglist, operand);
6021  }
6022  void Vld2(DataType dt,
6023            const NeonRegisterList& nreglist,
6024            const AlignedMemOperand& operand) {
6025    Vld2(al, dt, nreglist, operand);
6026  }
6027
6028  void Vld3(Condition cond,
6029            DataType dt,
6030            const NeonRegisterList& nreglist,
6031            const AlignedMemOperand& operand) {
6032    VIXL_ASSERT(allow_macro_instructions_);
6033    VIXL_ASSERT(OutsideITBlock());
6034    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6035    ITScope it_scope(this, &cond);
6036    vld3(cond, dt, nreglist, operand);
6037  }
6038  void Vld3(DataType dt,
6039            const NeonRegisterList& nreglist,
6040            const AlignedMemOperand& operand) {
6041    Vld3(al, dt, nreglist, operand);
6042  }
6043
6044  void Vld3(Condition cond,
6045            DataType dt,
6046            const NeonRegisterList& nreglist,
6047            const MemOperand& operand) {
6048    VIXL_ASSERT(allow_macro_instructions_);
6049    VIXL_ASSERT(OutsideITBlock());
6050    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6051    ITScope it_scope(this, &cond);
6052    vld3(cond, dt, nreglist, operand);
6053  }
6054  void Vld3(DataType dt,
6055            const NeonRegisterList& nreglist,
6056            const MemOperand& operand) {
6057    Vld3(al, dt, nreglist, operand);
6058  }
6059
6060  void Vld4(Condition cond,
6061            DataType dt,
6062            const NeonRegisterList& nreglist,
6063            const AlignedMemOperand& operand) {
6064    VIXL_ASSERT(allow_macro_instructions_);
6065    VIXL_ASSERT(OutsideITBlock());
6066    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6067    ITScope it_scope(this, &cond);
6068    vld4(cond, dt, nreglist, operand);
6069  }
6070  void Vld4(DataType dt,
6071            const NeonRegisterList& nreglist,
6072            const AlignedMemOperand& operand) {
6073    Vld4(al, dt, nreglist, operand);
6074  }
6075
6076  void Vldm(Condition cond,
6077            DataType dt,
6078            Register rn,
6079            WriteBack write_back,
6080            DRegisterList dreglist) {
6081    VIXL_ASSERT(allow_macro_instructions_);
6082    VIXL_ASSERT(OutsideITBlock());
6083    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6084    ITScope it_scope(this, &cond);
6085    vldm(cond, dt, rn, write_back, dreglist);
6086  }
6087  void Vldm(DataType dt,
6088            Register rn,
6089            WriteBack write_back,
6090            DRegisterList dreglist) {
6091    Vldm(al, dt, rn, write_back, dreglist);
6092  }
6093  void Vldm(Condition cond,
6094            Register rn,
6095            WriteBack write_back,
6096            DRegisterList dreglist) {
6097    Vldm(cond, kDataTypeValueNone, rn, write_back, dreglist);
6098  }
6099  void Vldm(Register rn, WriteBack write_back, DRegisterList dreglist) {
6100    Vldm(al, kDataTypeValueNone, rn, write_back, dreglist);
6101  }
6102
6103  void Vldm(Condition cond,
6104            DataType dt,
6105            Register rn,
6106            WriteBack write_back,
6107            SRegisterList sreglist) {
6108    VIXL_ASSERT(allow_macro_instructions_);
6109    VIXL_ASSERT(OutsideITBlock());
6110    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6111    ITScope it_scope(this, &cond);
6112    vldm(cond, dt, rn, write_back, sreglist);
6113  }
6114  void Vldm(DataType dt,
6115            Register rn,
6116            WriteBack write_back,
6117            SRegisterList sreglist) {
6118    Vldm(al, dt, rn, write_back, sreglist);
6119  }
6120  void Vldm(Condition cond,
6121            Register rn,
6122            WriteBack write_back,
6123            SRegisterList sreglist) {
6124    Vldm(cond, kDataTypeValueNone, rn, write_back, sreglist);
6125  }
6126  void Vldm(Register rn, WriteBack write_back, SRegisterList sreglist) {
6127    Vldm(al, kDataTypeValueNone, rn, write_back, sreglist);
6128  }
6129
6130  void Vldmdb(Condition cond,
6131              DataType dt,
6132              Register rn,
6133              WriteBack write_back,
6134              DRegisterList dreglist) {
6135    VIXL_ASSERT(allow_macro_instructions_);
6136    VIXL_ASSERT(OutsideITBlock());
6137    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6138    ITScope it_scope(this, &cond);
6139    vldmdb(cond, dt, rn, write_back, dreglist);
6140  }
6141  void Vldmdb(DataType dt,
6142              Register rn,
6143              WriteBack write_back,
6144              DRegisterList dreglist) {
6145    Vldmdb(al, dt, rn, write_back, dreglist);
6146  }
6147  void Vldmdb(Condition cond,
6148              Register rn,
6149              WriteBack write_back,
6150              DRegisterList dreglist) {
6151    Vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist);
6152  }
6153  void Vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) {
6154    Vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist);
6155  }
6156
6157  void Vldmdb(Condition cond,
6158              DataType dt,
6159              Register rn,
6160              WriteBack write_back,
6161              SRegisterList sreglist) {
6162    VIXL_ASSERT(allow_macro_instructions_);
6163    VIXL_ASSERT(OutsideITBlock());
6164    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6165    ITScope it_scope(this, &cond);
6166    vldmdb(cond, dt, rn, write_back, sreglist);
6167  }
6168  void Vldmdb(DataType dt,
6169              Register rn,
6170              WriteBack write_back,
6171              SRegisterList sreglist) {
6172    Vldmdb(al, dt, rn, write_back, sreglist);
6173  }
6174  void Vldmdb(Condition cond,
6175              Register rn,
6176              WriteBack write_back,
6177              SRegisterList sreglist) {
6178    Vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist);
6179  }
6180  void Vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) {
6181    Vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist);
6182  }
6183
6184  void Vldmia(Condition cond,
6185              DataType dt,
6186              Register rn,
6187              WriteBack write_back,
6188              DRegisterList dreglist) {
6189    VIXL_ASSERT(allow_macro_instructions_);
6190    VIXL_ASSERT(OutsideITBlock());
6191    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6192    ITScope it_scope(this, &cond);
6193    vldmia(cond, dt, rn, write_back, dreglist);
6194  }
6195  void Vldmia(DataType dt,
6196              Register rn,
6197              WriteBack write_back,
6198              DRegisterList dreglist) {
6199    Vldmia(al, dt, rn, write_back, dreglist);
6200  }
6201  void Vldmia(Condition cond,
6202              Register rn,
6203              WriteBack write_back,
6204              DRegisterList dreglist) {
6205    Vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist);
6206  }
6207  void Vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) {
6208    Vldmia(al, kDataTypeValueNone, rn, write_back, dreglist);
6209  }
6210
6211  void Vldmia(Condition cond,
6212              DataType dt,
6213              Register rn,
6214              WriteBack write_back,
6215              SRegisterList sreglist) {
6216    VIXL_ASSERT(allow_macro_instructions_);
6217    VIXL_ASSERT(OutsideITBlock());
6218    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6219    ITScope it_scope(this, &cond);
6220    vldmia(cond, dt, rn, write_back, sreglist);
6221  }
6222  void Vldmia(DataType dt,
6223              Register rn,
6224              WriteBack write_back,
6225              SRegisterList sreglist) {
6226    Vldmia(al, dt, rn, write_back, sreglist);
6227  }
6228  void Vldmia(Condition cond,
6229              Register rn,
6230              WriteBack write_back,
6231              SRegisterList sreglist) {
6232    Vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist);
6233  }
6234  void Vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) {
6235    Vldmia(al, kDataTypeValueNone, rn, write_back, sreglist);
6236  }
6237
6238  void Vldr(Condition cond, DataType dt, DRegister rd, Label* label) {
6239    VIXL_ASSERT(allow_macro_instructions_);
6240    VIXL_ASSERT(OutsideITBlock());
6241    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6242    ITScope it_scope(this, &cond);
6243    vldr(cond, dt, rd, label);
6244  }
6245  void Vldr(DataType dt, DRegister rd, Label* label) {
6246    Vldr(al, dt, rd, label);
6247  }
6248  void Vldr(Condition cond, DRegister rd, Label* label) {
6249    Vldr(cond, Untyped64, rd, label);
6250  }
6251  void Vldr(DRegister rd, Label* label) { Vldr(al, Untyped64, rd, label); }
6252
6253  void Vldr(Condition cond,
6254            DataType dt,
6255            DRegister rd,
6256            const MemOperand& operand) {
6257    VIXL_ASSERT(allow_macro_instructions_);
6258    VIXL_ASSERT(OutsideITBlock());
6259    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6260    ITScope it_scope(this, &cond);
6261    vldr(cond, dt, rd, operand);
6262  }
6263  void Vldr(DataType dt, DRegister rd, const MemOperand& operand) {
6264    Vldr(al, dt, rd, operand);
6265  }
6266  void Vldr(Condition cond, DRegister rd, const MemOperand& operand) {
6267    Vldr(cond, Untyped64, rd, operand);
6268  }
6269  void Vldr(DRegister rd, const MemOperand& operand) {
6270    Vldr(al, Untyped64, rd, operand);
6271  }
6272
6273  void Vldr(Condition cond, DataType dt, SRegister rd, Label* label) {
6274    VIXL_ASSERT(allow_macro_instructions_);
6275    VIXL_ASSERT(OutsideITBlock());
6276    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6277    ITScope it_scope(this, &cond);
6278    vldr(cond, dt, rd, label);
6279  }
6280  void Vldr(DataType dt, SRegister rd, Label* label) {
6281    Vldr(al, dt, rd, label);
6282  }
6283  void Vldr(Condition cond, SRegister rd, Label* label) {
6284    Vldr(cond, Untyped32, rd, label);
6285  }
6286  void Vldr(SRegister rd, Label* label) { Vldr(al, Untyped32, rd, label); }
6287
6288  void Vldr(Condition cond,
6289            DataType dt,
6290            SRegister rd,
6291            const MemOperand& operand) {
6292    VIXL_ASSERT(allow_macro_instructions_);
6293    VIXL_ASSERT(OutsideITBlock());
6294    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6295    ITScope it_scope(this, &cond);
6296    vldr(cond, dt, rd, operand);
6297  }
6298  void Vldr(DataType dt, SRegister rd, const MemOperand& operand) {
6299    Vldr(al, dt, rd, operand);
6300  }
6301  void Vldr(Condition cond, SRegister rd, const MemOperand& operand) {
6302    Vldr(cond, Untyped32, rd, operand);
6303  }
6304  void Vldr(SRegister rd, const MemOperand& operand) {
6305    Vldr(al, Untyped32, rd, operand);
6306  }
6307
6308  void Vmax(
6309      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6310    VIXL_ASSERT(allow_macro_instructions_);
6311    VIXL_ASSERT(OutsideITBlock());
6312    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6313    ITScope it_scope(this, &cond);
6314    vmax(cond, dt, rd, rn, rm);
6315  }
6316  void Vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6317    Vmax(al, dt, rd, rn, rm);
6318  }
6319
6320  void Vmax(
6321      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6322    VIXL_ASSERT(allow_macro_instructions_);
6323    VIXL_ASSERT(OutsideITBlock());
6324    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6325    ITScope it_scope(this, &cond);
6326    vmax(cond, dt, rd, rn, rm);
6327  }
6328  void Vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6329    Vmax(al, dt, rd, rn, rm);
6330  }
6331
6332  void Vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6333    VIXL_ASSERT(allow_macro_instructions_);
6334    VIXL_ASSERT(OutsideITBlock());
6335    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6336    vmaxnm(dt, rd, rn, rm);
6337  }
6338
6339  void Vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6340    VIXL_ASSERT(allow_macro_instructions_);
6341    VIXL_ASSERT(OutsideITBlock());
6342    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6343    vmaxnm(dt, rd, rn, rm);
6344  }
6345
6346  void Vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6347    VIXL_ASSERT(allow_macro_instructions_);
6348    VIXL_ASSERT(OutsideITBlock());
6349    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6350    vmaxnm(dt, rd, rn, rm);
6351  }
6352
6353  void Vmin(
6354      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6355    VIXL_ASSERT(allow_macro_instructions_);
6356    VIXL_ASSERT(OutsideITBlock());
6357    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6358    ITScope it_scope(this, &cond);
6359    vmin(cond, dt, rd, rn, rm);
6360  }
6361  void Vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6362    Vmin(al, dt, rd, rn, rm);
6363  }
6364
6365  void Vmin(
6366      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6367    VIXL_ASSERT(allow_macro_instructions_);
6368    VIXL_ASSERT(OutsideITBlock());
6369    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6370    ITScope it_scope(this, &cond);
6371    vmin(cond, dt, rd, rn, rm);
6372  }
6373  void Vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6374    Vmin(al, dt, rd, rn, rm);
6375  }
6376
6377  void Vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6378    VIXL_ASSERT(allow_macro_instructions_);
6379    VIXL_ASSERT(OutsideITBlock());
6380    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6381    vminnm(dt, rd, rn, rm);
6382  }
6383
6384  void Vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6385    VIXL_ASSERT(allow_macro_instructions_);
6386    VIXL_ASSERT(OutsideITBlock());
6387    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6388    vminnm(dt, rd, rn, rm);
6389  }
6390
6391  void Vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6392    VIXL_ASSERT(allow_macro_instructions_);
6393    VIXL_ASSERT(OutsideITBlock());
6394    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6395    vminnm(dt, rd, rn, rm);
6396  }
6397
6398  void Vmla(Condition cond,
6399            DataType dt,
6400            DRegister rd,
6401            DRegister rn,
6402            DRegisterLane rm) {
6403    VIXL_ASSERT(allow_macro_instructions_);
6404    VIXL_ASSERT(OutsideITBlock());
6405    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6406    ITScope it_scope(this, &cond);
6407    vmla(cond, dt, rd, rn, rm);
6408  }
6409  void Vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
6410    Vmla(al, dt, rd, rn, rm);
6411  }
6412
6413  void Vmla(Condition cond,
6414            DataType dt,
6415            QRegister rd,
6416            QRegister rn,
6417            DRegisterLane rm) {
6418    VIXL_ASSERT(allow_macro_instructions_);
6419    VIXL_ASSERT(OutsideITBlock());
6420    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6421    ITScope it_scope(this, &cond);
6422    vmla(cond, dt, rd, rn, rm);
6423  }
6424  void Vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
6425    Vmla(al, dt, rd, rn, rm);
6426  }
6427
6428  void Vmla(
6429      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6430    VIXL_ASSERT(allow_macro_instructions_);
6431    VIXL_ASSERT(OutsideITBlock());
6432    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6433    ITScope it_scope(this, &cond);
6434    vmla(cond, dt, rd, rn, rm);
6435  }
6436  void Vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6437    Vmla(al, dt, rd, rn, rm);
6438  }
6439
6440  void Vmla(
6441      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6442    VIXL_ASSERT(allow_macro_instructions_);
6443    VIXL_ASSERT(OutsideITBlock());
6444    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6445    ITScope it_scope(this, &cond);
6446    vmla(cond, dt, rd, rn, rm);
6447  }
6448  void Vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6449    Vmla(al, dt, rd, rn, rm);
6450  }
6451
6452  void Vmla(
6453      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6454    VIXL_ASSERT(allow_macro_instructions_);
6455    VIXL_ASSERT(OutsideITBlock());
6456    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6457    ITScope it_scope(this, &cond);
6458    vmla(cond, dt, rd, rn, rm);
6459  }
6460  void Vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6461    Vmla(al, dt, rd, rn, rm);
6462  }
6463
6464  void Vmlal(Condition cond,
6465             DataType dt,
6466             QRegister rd,
6467             DRegister rn,
6468             DRegisterLane rm) {
6469    VIXL_ASSERT(allow_macro_instructions_);
6470    VIXL_ASSERT(OutsideITBlock());
6471    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6472    ITScope it_scope(this, &cond);
6473    vmlal(cond, dt, rd, rn, rm);
6474  }
6475  void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
6476    Vmlal(al, dt, rd, rn, rm);
6477  }
6478
6479  void Vmlal(
6480      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6481    VIXL_ASSERT(allow_macro_instructions_);
6482    VIXL_ASSERT(OutsideITBlock());
6483    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6484    ITScope it_scope(this, &cond);
6485    vmlal(cond, dt, rd, rn, rm);
6486  }
6487  void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6488    Vmlal(al, dt, rd, rn, rm);
6489  }
6490
6491  void Vmls(Condition cond,
6492            DataType dt,
6493            DRegister rd,
6494            DRegister rn,
6495            DRegisterLane rm) {
6496    VIXL_ASSERT(allow_macro_instructions_);
6497    VIXL_ASSERT(OutsideITBlock());
6498    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6499    ITScope it_scope(this, &cond);
6500    vmls(cond, dt, rd, rn, rm);
6501  }
6502  void Vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
6503    Vmls(al, dt, rd, rn, rm);
6504  }
6505
6506  void Vmls(Condition cond,
6507            DataType dt,
6508            QRegister rd,
6509            QRegister rn,
6510            DRegisterLane rm) {
6511    VIXL_ASSERT(allow_macro_instructions_);
6512    VIXL_ASSERT(OutsideITBlock());
6513    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6514    ITScope it_scope(this, &cond);
6515    vmls(cond, dt, rd, rn, rm);
6516  }
6517  void Vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
6518    Vmls(al, dt, rd, rn, rm);
6519  }
6520
6521  void Vmls(
6522      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6523    VIXL_ASSERT(allow_macro_instructions_);
6524    VIXL_ASSERT(OutsideITBlock());
6525    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6526    ITScope it_scope(this, &cond);
6527    vmls(cond, dt, rd, rn, rm);
6528  }
6529  void Vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6530    Vmls(al, dt, rd, rn, rm);
6531  }
6532
6533  void Vmls(
6534      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6535    VIXL_ASSERT(allow_macro_instructions_);
6536    VIXL_ASSERT(OutsideITBlock());
6537    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6538    ITScope it_scope(this, &cond);
6539    vmls(cond, dt, rd, rn, rm);
6540  }
6541  void Vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6542    Vmls(al, dt, rd, rn, rm);
6543  }
6544
6545  void Vmls(
6546      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6547    VIXL_ASSERT(allow_macro_instructions_);
6548    VIXL_ASSERT(OutsideITBlock());
6549    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6550    ITScope it_scope(this, &cond);
6551    vmls(cond, dt, rd, rn, rm);
6552  }
6553  void Vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6554    Vmls(al, dt, rd, rn, rm);
6555  }
6556
6557  void Vmlsl(Condition cond,
6558             DataType dt,
6559             QRegister rd,
6560             DRegister rn,
6561             DRegisterLane rm) {
6562    VIXL_ASSERT(allow_macro_instructions_);
6563    VIXL_ASSERT(OutsideITBlock());
6564    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6565    ITScope it_scope(this, &cond);
6566    vmlsl(cond, dt, rd, rn, rm);
6567  }
6568  void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
6569    Vmlsl(al, dt, rd, rn, rm);
6570  }
6571
6572  void Vmlsl(
6573      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6574    VIXL_ASSERT(allow_macro_instructions_);
6575    VIXL_ASSERT(OutsideITBlock());
6576    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6577    ITScope it_scope(this, &cond);
6578    vmlsl(cond, dt, rd, rn, rm);
6579  }
6580  void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6581    Vmlsl(al, dt, rd, rn, rm);
6582  }
6583
6584  void Vmov(Condition cond, Register rt, SRegister rn) {
6585    VIXL_ASSERT(allow_macro_instructions_);
6586    VIXL_ASSERT(OutsideITBlock());
6587    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6588    ITScope it_scope(this, &cond);
6589    vmov(cond, rt, rn);
6590  }
6591  void Vmov(Register rt, SRegister rn) { Vmov(al, rt, rn); }
6592
6593  void Vmov(Condition cond, SRegister rn, Register rt) {
6594    VIXL_ASSERT(allow_macro_instructions_);
6595    VIXL_ASSERT(OutsideITBlock());
6596    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6597    ITScope it_scope(this, &cond);
6598    vmov(cond, rn, rt);
6599  }
6600  void Vmov(SRegister rn, Register rt) { Vmov(al, rn, rt); }
6601
6602  void Vmov(Condition cond, Register rt, Register rt2, DRegister rm) {
6603    VIXL_ASSERT(allow_macro_instructions_);
6604    VIXL_ASSERT(OutsideITBlock());
6605    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6606    ITScope it_scope(this, &cond);
6607    vmov(cond, rt, rt2, rm);
6608  }
6609  void Vmov(Register rt, Register rt2, DRegister rm) { Vmov(al, rt, rt2, rm); }
6610
6611  void Vmov(Condition cond, DRegister rm, Register rt, Register rt2) {
6612    VIXL_ASSERT(allow_macro_instructions_);
6613    VIXL_ASSERT(OutsideITBlock());
6614    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6615    ITScope it_scope(this, &cond);
6616    vmov(cond, rm, rt, rt2);
6617  }
6618  void Vmov(DRegister rm, Register rt, Register rt2) { Vmov(al, rm, rt, rt2); }
6619
6620  void Vmov(
6621      Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) {
6622    VIXL_ASSERT(allow_macro_instructions_);
6623    VIXL_ASSERT(OutsideITBlock());
6624    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6625    ITScope it_scope(this, &cond);
6626    vmov(cond, rt, rt2, rm, rm1);
6627  }
6628  void Vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) {
6629    Vmov(al, rt, rt2, rm, rm1);
6630  }
6631
6632  void Vmov(
6633      Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) {
6634    VIXL_ASSERT(allow_macro_instructions_);
6635    VIXL_ASSERT(OutsideITBlock());
6636    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6637    ITScope it_scope(this, &cond);
6638    vmov(cond, rm, rm1, rt, rt2);
6639  }
6640  void Vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) {
6641    Vmov(al, rm, rm1, rt, rt2);
6642  }
6643
6644  void Vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt) {
6645    VIXL_ASSERT(allow_macro_instructions_);
6646    VIXL_ASSERT(OutsideITBlock());
6647    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6648    ITScope it_scope(this, &cond);
6649    vmov(cond, dt, rd, rt);
6650  }
6651  void Vmov(DataType dt, DRegisterLane rd, Register rt) {
6652    Vmov(al, dt, rd, rt);
6653  }
6654  void Vmov(Condition cond, DRegisterLane rd, Register rt) {
6655    Vmov(cond, kDataTypeValueNone, rd, rt);
6656  }
6657  void Vmov(DRegisterLane rd, Register rt) {
6658    Vmov(al, kDataTypeValueNone, rd, rt);
6659  }
6660
6661  void Vmov(Condition cond,
6662            DataType dt,
6663            DRegister rd,
6664            const DOperand& operand) {
6665    VIXL_ASSERT(allow_macro_instructions_);
6666    VIXL_ASSERT(OutsideITBlock());
6667    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6668    ITScope it_scope(this, &cond);
6669    vmov(cond, dt, rd, operand);
6670  }
6671  void Vmov(DataType dt, DRegister rd, const DOperand& operand) {
6672    Vmov(al, dt, rd, operand);
6673  }
6674
6675  void Vmov(Condition cond,
6676            DataType dt,
6677            QRegister rd,
6678            const QOperand& operand) {
6679    VIXL_ASSERT(allow_macro_instructions_);
6680    VIXL_ASSERT(OutsideITBlock());
6681    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6682    ITScope it_scope(this, &cond);
6683    vmov(cond, dt, rd, operand);
6684  }
6685  void Vmov(DataType dt, QRegister rd, const QOperand& operand) {
6686    Vmov(al, dt, rd, operand);
6687  }
6688
6689  void Vmov(Condition cond,
6690            DataType dt,
6691            SRegister rd,
6692            const SOperand& operand) {
6693    VIXL_ASSERT(allow_macro_instructions_);
6694    VIXL_ASSERT(OutsideITBlock());
6695    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6696    ITScope it_scope(this, &cond);
6697    vmov(cond, dt, rd, operand);
6698  }
6699  void Vmov(DataType dt, SRegister rd, const SOperand& operand) {
6700    Vmov(al, dt, rd, operand);
6701  }
6702
6703  void Vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn) {
6704    VIXL_ASSERT(allow_macro_instructions_);
6705    VIXL_ASSERT(OutsideITBlock());
6706    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6707    ITScope it_scope(this, &cond);
6708    vmov(cond, dt, rt, rn);
6709  }
6710  void Vmov(DataType dt, Register rt, DRegisterLane rn) {
6711    Vmov(al, dt, rt, rn);
6712  }
6713  void Vmov(Condition cond, Register rt, DRegisterLane rn) {
6714    Vmov(cond, kDataTypeValueNone, rt, rn);
6715  }
6716  void Vmov(Register rt, DRegisterLane rn) {
6717    Vmov(al, kDataTypeValueNone, rt, rn);
6718  }
6719
6720  void Vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {
6721    VIXL_ASSERT(allow_macro_instructions_);
6722    VIXL_ASSERT(OutsideITBlock());
6723    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6724    ITScope it_scope(this, &cond);
6725    vmovl(cond, dt, rd, rm);
6726  }
6727  void Vmovl(DataType dt, QRegister rd, DRegister rm) { Vmovl(al, dt, rd, rm); }
6728
6729  void Vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
6730    VIXL_ASSERT(allow_macro_instructions_);
6731    VIXL_ASSERT(OutsideITBlock());
6732    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6733    ITScope it_scope(this, &cond);
6734    vmovn(cond, dt, rd, rm);
6735  }
6736  void Vmovn(DataType dt, DRegister rd, QRegister rm) { Vmovn(al, dt, rd, rm); }
6737
6738  void Vmrs(Condition cond,
6739            RegisterOrAPSR_nzcv rt,
6740            SpecialFPRegister spec_reg) {
6741    VIXL_ASSERT(allow_macro_instructions_);
6742    VIXL_ASSERT(OutsideITBlock());
6743    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6744    ITScope it_scope(this, &cond);
6745    vmrs(cond, rt, spec_reg);
6746  }
6747  void Vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) {
6748    Vmrs(al, rt, spec_reg);
6749  }
6750
6751  void Vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) {
6752    VIXL_ASSERT(allow_macro_instructions_);
6753    VIXL_ASSERT(OutsideITBlock());
6754    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6755    ITScope it_scope(this, &cond);
6756    vmsr(cond, spec_reg, rt);
6757  }
6758  void Vmsr(SpecialFPRegister spec_reg, Register rt) { Vmsr(al, spec_reg, rt); }
6759
6760  void Vmul(Condition cond,
6761            DataType dt,
6762            DRegister rd,
6763            DRegister rn,
6764            DRegister dm,
6765            unsigned index) {
6766    VIXL_ASSERT(allow_macro_instructions_);
6767    VIXL_ASSERT(OutsideITBlock());
6768    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6769    ITScope it_scope(this, &cond);
6770    vmul(cond, dt, rd, rn, dm, index);
6771  }
6772  void Vmul(
6773      DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) {
6774    Vmul(al, dt, rd, rn, dm, index);
6775  }
6776
6777  void Vmul(Condition cond,
6778            DataType dt,
6779            QRegister rd,
6780            QRegister rn,
6781            DRegister dm,
6782            unsigned index) {
6783    VIXL_ASSERT(allow_macro_instructions_);
6784    VIXL_ASSERT(OutsideITBlock());
6785    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6786    ITScope it_scope(this, &cond);
6787    vmul(cond, dt, rd, rn, dm, index);
6788  }
6789  void Vmul(
6790      DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) {
6791    Vmul(al, dt, rd, rn, dm, index);
6792  }
6793
6794  void Vmul(
6795      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6796    VIXL_ASSERT(allow_macro_instructions_);
6797    VIXL_ASSERT(OutsideITBlock());
6798    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6799    ITScope it_scope(this, &cond);
6800    vmul(cond, dt, rd, rn, rm);
6801  }
6802  void Vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6803    Vmul(al, dt, rd, rn, rm);
6804  }
6805
6806  void Vmul(
6807      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6808    VIXL_ASSERT(allow_macro_instructions_);
6809    VIXL_ASSERT(OutsideITBlock());
6810    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6811    ITScope it_scope(this, &cond);
6812    vmul(cond, dt, rd, rn, rm);
6813  }
6814  void Vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6815    Vmul(al, dt, rd, rn, rm);
6816  }
6817
6818  void Vmul(
6819      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6820    VIXL_ASSERT(allow_macro_instructions_);
6821    VIXL_ASSERT(OutsideITBlock());
6822    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6823    ITScope it_scope(this, &cond);
6824    vmul(cond, dt, rd, rn, rm);
6825  }
6826  void Vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6827    Vmul(al, dt, rd, rn, rm);
6828  }
6829
6830  void Vmull(Condition cond,
6831             DataType dt,
6832             QRegister rd,
6833             DRegister rn,
6834             DRegister dm,
6835             unsigned index) {
6836    VIXL_ASSERT(allow_macro_instructions_);
6837    VIXL_ASSERT(OutsideITBlock());
6838    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6839    ITScope it_scope(this, &cond);
6840    vmull(cond, dt, rd, rn, dm, index);
6841  }
6842  void Vmull(
6843      DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
6844    Vmull(al, dt, rd, rn, dm, index);
6845  }
6846
6847  void Vmull(
6848      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6849    VIXL_ASSERT(allow_macro_instructions_);
6850    VIXL_ASSERT(OutsideITBlock());
6851    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6852    ITScope it_scope(this, &cond);
6853    vmull(cond, dt, rd, rn, rm);
6854  }
6855  void Vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6856    Vmull(al, dt, rd, rn, rm);
6857  }
6858
6859  void Vmvn(Condition cond,
6860            DataType dt,
6861            DRegister rd,
6862            const DOperand& operand) {
6863    VIXL_ASSERT(allow_macro_instructions_);
6864    VIXL_ASSERT(OutsideITBlock());
6865    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6866    ITScope it_scope(this, &cond);
6867    vmvn(cond, dt, rd, operand);
6868  }
6869  void Vmvn(DataType dt, DRegister rd, const DOperand& operand) {
6870    Vmvn(al, dt, rd, operand);
6871  }
6872
6873  void Vmvn(Condition cond,
6874            DataType dt,
6875            QRegister rd,
6876            const QOperand& operand) {
6877    VIXL_ASSERT(allow_macro_instructions_);
6878    VIXL_ASSERT(OutsideITBlock());
6879    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6880    ITScope it_scope(this, &cond);
6881    vmvn(cond, dt, rd, operand);
6882  }
6883  void Vmvn(DataType dt, QRegister rd, const QOperand& operand) {
6884    Vmvn(al, dt, rd, operand);
6885  }
6886
6887  void Vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
6888    VIXL_ASSERT(allow_macro_instructions_);
6889    VIXL_ASSERT(OutsideITBlock());
6890    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6891    ITScope it_scope(this, &cond);
6892    vneg(cond, dt, rd, rm);
6893  }
6894  void Vneg(DataType dt, DRegister rd, DRegister rm) { Vneg(al, dt, rd, rm); }
6895
6896  void Vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
6897    VIXL_ASSERT(allow_macro_instructions_);
6898    VIXL_ASSERT(OutsideITBlock());
6899    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6900    ITScope it_scope(this, &cond);
6901    vneg(cond, dt, rd, rm);
6902  }
6903  void Vneg(DataType dt, QRegister rd, QRegister rm) { Vneg(al, dt, rd, rm); }
6904
6905  void Vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {
6906    VIXL_ASSERT(allow_macro_instructions_);
6907    VIXL_ASSERT(OutsideITBlock());
6908    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6909    ITScope it_scope(this, &cond);
6910    vneg(cond, dt, rd, rm);
6911  }
6912  void Vneg(DataType dt, SRegister rd, SRegister rm) { Vneg(al, dt, rd, rm); }
6913
6914  void Vnmla(
6915      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6916    VIXL_ASSERT(allow_macro_instructions_);
6917    VIXL_ASSERT(OutsideITBlock());
6918    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6919    ITScope it_scope(this, &cond);
6920    vnmla(cond, dt, rd, rn, rm);
6921  }
6922  void Vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6923    Vnmla(al, dt, rd, rn, rm);
6924  }
6925
6926  void Vnmla(
6927      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6928    VIXL_ASSERT(allow_macro_instructions_);
6929    VIXL_ASSERT(OutsideITBlock());
6930    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6931    ITScope it_scope(this, &cond);
6932    vnmla(cond, dt, rd, rn, rm);
6933  }
6934  void Vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6935    Vnmla(al, dt, rd, rn, rm);
6936  }
6937
6938  void Vnmls(
6939      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6940    VIXL_ASSERT(allow_macro_instructions_);
6941    VIXL_ASSERT(OutsideITBlock());
6942    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6943    ITScope it_scope(this, &cond);
6944    vnmls(cond, dt, rd, rn, rm);
6945  }
6946  void Vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6947    Vnmls(al, dt, rd, rn, rm);
6948  }
6949
6950  void Vnmls(
6951      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6952    VIXL_ASSERT(allow_macro_instructions_);
6953    VIXL_ASSERT(OutsideITBlock());
6954    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6955    ITScope it_scope(this, &cond);
6956    vnmls(cond, dt, rd, rn, rm);
6957  }
6958  void Vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6959    Vnmls(al, dt, rd, rn, rm);
6960  }
6961
6962  void Vnmul(
6963      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6964    VIXL_ASSERT(allow_macro_instructions_);
6965    VIXL_ASSERT(OutsideITBlock());
6966    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6967    ITScope it_scope(this, &cond);
6968    vnmul(cond, dt, rd, rn, rm);
6969  }
6970  void Vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6971    Vnmul(al, dt, rd, rn, rm);
6972  }
6973
6974  void Vnmul(
6975      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6976    VIXL_ASSERT(allow_macro_instructions_);
6977    VIXL_ASSERT(OutsideITBlock());
6978    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6979    ITScope it_scope(this, &cond);
6980    vnmul(cond, dt, rd, rn, rm);
6981  }
6982  void Vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6983    Vnmul(al, dt, rd, rn, rm);
6984  }
6985
6986  void Vorn(Condition cond,
6987            DataType dt,
6988            DRegister rd,
6989            DRegister rn,
6990            const DOperand& operand) {
6991    VIXL_ASSERT(allow_macro_instructions_);
6992    VIXL_ASSERT(OutsideITBlock());
6993    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
6994    ITScope it_scope(this, &cond);
6995    vorn(cond, dt, rd, rn, operand);
6996  }
6997  void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
6998    Vorn(al, dt, rd, rn, operand);
6999  }
7000
7001  void Vorn(Condition cond,
7002            DataType dt,
7003            QRegister rd,
7004            QRegister rn,
7005            const QOperand& operand) {
7006    VIXL_ASSERT(allow_macro_instructions_);
7007    VIXL_ASSERT(OutsideITBlock());
7008    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7009    ITScope it_scope(this, &cond);
7010    vorn(cond, dt, rd, rn, operand);
7011  }
7012  void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
7013    Vorn(al, dt, rd, rn, operand);
7014  }
7015
7016  void Vorr(Condition cond,
7017            DataType dt,
7018            DRegister rd,
7019            DRegister rn,
7020            const DOperand& operand) {
7021    VIXL_ASSERT(allow_macro_instructions_);
7022    VIXL_ASSERT(OutsideITBlock());
7023    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7024    ITScope it_scope(this, &cond);
7025    vorr(cond, dt, rd, rn, operand);
7026  }
7027  void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
7028    Vorr(al, dt, rd, rn, operand);
7029  }
7030  void Vorr(Condition cond,
7031            DRegister rd,
7032            DRegister rn,
7033            const DOperand& operand) {
7034    Vorr(cond, kDataTypeValueNone, rd, rn, operand);
7035  }
7036  void Vorr(DRegister rd, DRegister rn, const DOperand& operand) {
7037    Vorr(al, kDataTypeValueNone, rd, rn, operand);
7038  }
7039
7040  void Vorr(Condition cond,
7041            DataType dt,
7042            QRegister rd,
7043            QRegister rn,
7044            const QOperand& operand) {
7045    VIXL_ASSERT(allow_macro_instructions_);
7046    VIXL_ASSERT(OutsideITBlock());
7047    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7048    ITScope it_scope(this, &cond);
7049    vorr(cond, dt, rd, rn, operand);
7050  }
7051  void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
7052    Vorr(al, dt, rd, rn, operand);
7053  }
7054  void Vorr(Condition cond,
7055            QRegister rd,
7056            QRegister rn,
7057            const QOperand& operand) {
7058    Vorr(cond, kDataTypeValueNone, rd, rn, operand);
7059  }
7060  void Vorr(QRegister rd, QRegister rn, const QOperand& operand) {
7061    Vorr(al, kDataTypeValueNone, rd, rn, operand);
7062  }
7063
7064  void Vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7065    VIXL_ASSERT(allow_macro_instructions_);
7066    VIXL_ASSERT(OutsideITBlock());
7067    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7068    ITScope it_scope(this, &cond);
7069    vpadal(cond, dt, rd, rm);
7070  }
7071  void Vpadal(DataType dt, DRegister rd, DRegister rm) {
7072    Vpadal(al, dt, rd, rm);
7073  }
7074
7075  void Vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7076    VIXL_ASSERT(allow_macro_instructions_);
7077    VIXL_ASSERT(OutsideITBlock());
7078    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7079    ITScope it_scope(this, &cond);
7080    vpadal(cond, dt, rd, rm);
7081  }
7082  void Vpadal(DataType dt, QRegister rd, QRegister rm) {
7083    Vpadal(al, dt, rd, rm);
7084  }
7085
7086  void Vpadd(
7087      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7088    VIXL_ASSERT(allow_macro_instructions_);
7089    VIXL_ASSERT(OutsideITBlock());
7090    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7091    ITScope it_scope(this, &cond);
7092    vpadd(cond, dt, rd, rn, rm);
7093  }
7094  void Vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7095    Vpadd(al, dt, rd, rn, rm);
7096  }
7097
7098  void Vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7099    VIXL_ASSERT(allow_macro_instructions_);
7100    VIXL_ASSERT(OutsideITBlock());
7101    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7102    ITScope it_scope(this, &cond);
7103    vpaddl(cond, dt, rd, rm);
7104  }
7105  void Vpaddl(DataType dt, DRegister rd, DRegister rm) {
7106    Vpaddl(al, dt, rd, rm);
7107  }
7108
7109  void Vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7110    VIXL_ASSERT(allow_macro_instructions_);
7111    VIXL_ASSERT(OutsideITBlock());
7112    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7113    ITScope it_scope(this, &cond);
7114    vpaddl(cond, dt, rd, rm);
7115  }
7116  void Vpaddl(DataType dt, QRegister rd, QRegister rm) {
7117    Vpaddl(al, dt, rd, rm);
7118  }
7119
7120  void Vpmax(
7121      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7122    VIXL_ASSERT(allow_macro_instructions_);
7123    VIXL_ASSERT(OutsideITBlock());
7124    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7125    ITScope it_scope(this, &cond);
7126    vpmax(cond, dt, rd, rn, rm);
7127  }
7128  void Vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7129    Vpmax(al, dt, rd, rn, rm);
7130  }
7131
7132  void Vpmin(
7133      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7134    VIXL_ASSERT(allow_macro_instructions_);
7135    VIXL_ASSERT(OutsideITBlock());
7136    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7137    ITScope it_scope(this, &cond);
7138    vpmin(cond, dt, rd, rn, rm);
7139  }
7140  void Vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7141    Vpmin(al, dt, rd, rn, rm);
7142  }
7143
7144  void Vpop(Condition cond, DataType dt, DRegisterList dreglist) {
7145    VIXL_ASSERT(allow_macro_instructions_);
7146    VIXL_ASSERT(OutsideITBlock());
7147    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7148    ITScope it_scope(this, &cond);
7149    vpop(cond, dt, dreglist);
7150  }
7151  void Vpop(DataType dt, DRegisterList dreglist) { Vpop(al, dt, dreglist); }
7152  void Vpop(Condition cond, DRegisterList dreglist) {
7153    Vpop(cond, kDataTypeValueNone, dreglist);
7154  }
7155  void Vpop(DRegisterList dreglist) { Vpop(al, kDataTypeValueNone, dreglist); }
7156
7157  void Vpop(Condition cond, DataType dt, SRegisterList sreglist) {
7158    VIXL_ASSERT(allow_macro_instructions_);
7159    VIXL_ASSERT(OutsideITBlock());
7160    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7161    ITScope it_scope(this, &cond);
7162    vpop(cond, dt, sreglist);
7163  }
7164  void Vpop(DataType dt, SRegisterList sreglist) { Vpop(al, dt, sreglist); }
7165  void Vpop(Condition cond, SRegisterList sreglist) {
7166    Vpop(cond, kDataTypeValueNone, sreglist);
7167  }
7168  void Vpop(SRegisterList sreglist) { Vpop(al, kDataTypeValueNone, sreglist); }
7169
7170  void Vpush(Condition cond, DataType dt, DRegisterList dreglist) {
7171    VIXL_ASSERT(allow_macro_instructions_);
7172    VIXL_ASSERT(OutsideITBlock());
7173    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7174    ITScope it_scope(this, &cond);
7175    vpush(cond, dt, dreglist);
7176  }
7177  void Vpush(DataType dt, DRegisterList dreglist) { Vpush(al, dt, dreglist); }
7178  void Vpush(Condition cond, DRegisterList dreglist) {
7179    Vpush(cond, kDataTypeValueNone, dreglist);
7180  }
7181  void Vpush(DRegisterList dreglist) {
7182    Vpush(al, kDataTypeValueNone, dreglist);
7183  }
7184
7185  void Vpush(Condition cond, DataType dt, SRegisterList sreglist) {
7186    VIXL_ASSERT(allow_macro_instructions_);
7187    VIXL_ASSERT(OutsideITBlock());
7188    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7189    ITScope it_scope(this, &cond);
7190    vpush(cond, dt, sreglist);
7191  }
7192  void Vpush(DataType dt, SRegisterList sreglist) { Vpush(al, dt, sreglist); }
7193  void Vpush(Condition cond, SRegisterList sreglist) {
7194    Vpush(cond, kDataTypeValueNone, sreglist);
7195  }
7196  void Vpush(SRegisterList sreglist) {
7197    Vpush(al, kDataTypeValueNone, sreglist);
7198  }
7199
7200  void Vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7201    VIXL_ASSERT(allow_macro_instructions_);
7202    VIXL_ASSERT(OutsideITBlock());
7203    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7204    ITScope it_scope(this, &cond);
7205    vqabs(cond, dt, rd, rm);
7206  }
7207  void Vqabs(DataType dt, DRegister rd, DRegister rm) { Vqabs(al, dt, rd, rm); }
7208
7209  void Vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7210    VIXL_ASSERT(allow_macro_instructions_);
7211    VIXL_ASSERT(OutsideITBlock());
7212    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7213    ITScope it_scope(this, &cond);
7214    vqabs(cond, dt, rd, rm);
7215  }
7216  void Vqabs(DataType dt, QRegister rd, QRegister rm) { Vqabs(al, dt, rd, rm); }
7217
7218  void Vqadd(
7219      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7220    VIXL_ASSERT(allow_macro_instructions_);
7221    VIXL_ASSERT(OutsideITBlock());
7222    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7223    ITScope it_scope(this, &cond);
7224    vqadd(cond, dt, rd, rn, rm);
7225  }
7226  void Vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7227    Vqadd(al, dt, rd, rn, rm);
7228  }
7229
7230  void Vqadd(
7231      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7232    VIXL_ASSERT(allow_macro_instructions_);
7233    VIXL_ASSERT(OutsideITBlock());
7234    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7235    ITScope it_scope(this, &cond);
7236    vqadd(cond, dt, rd, rn, rm);
7237  }
7238  void Vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7239    Vqadd(al, dt, rd, rn, rm);
7240  }
7241
7242  void Vqdmlal(
7243      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7244    VIXL_ASSERT(allow_macro_instructions_);
7245    VIXL_ASSERT(OutsideITBlock());
7246    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7247    ITScope it_scope(this, &cond);
7248    vqdmlal(cond, dt, rd, rn, rm);
7249  }
7250  void Vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7251    Vqdmlal(al, dt, rd, rn, rm);
7252  }
7253
7254  void Vqdmlal(Condition cond,
7255               DataType dt,
7256               QRegister rd,
7257               DRegister rn,
7258               DRegister dm,
7259               unsigned index) {
7260    VIXL_ASSERT(allow_macro_instructions_);
7261    VIXL_ASSERT(OutsideITBlock());
7262    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7263    ITScope it_scope(this, &cond);
7264    vqdmlal(cond, dt, rd, rn, dm, index);
7265  }
7266  void Vqdmlal(
7267      DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
7268    Vqdmlal(al, dt, rd, rn, dm, index);
7269  }
7270
7271  void Vqdmlsl(
7272      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7273    VIXL_ASSERT(allow_macro_instructions_);
7274    VIXL_ASSERT(OutsideITBlock());
7275    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7276    ITScope it_scope(this, &cond);
7277    vqdmlsl(cond, dt, rd, rn, rm);
7278  }
7279  void Vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7280    Vqdmlsl(al, dt, rd, rn, rm);
7281  }
7282
7283  void Vqdmlsl(Condition cond,
7284               DataType dt,
7285               QRegister rd,
7286               DRegister rn,
7287               DRegister dm,
7288               unsigned index) {
7289    VIXL_ASSERT(allow_macro_instructions_);
7290    VIXL_ASSERT(OutsideITBlock());
7291    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7292    ITScope it_scope(this, &cond);
7293    vqdmlsl(cond, dt, rd, rn, dm, index);
7294  }
7295  void Vqdmlsl(
7296      DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
7297    Vqdmlsl(al, dt, rd, rn, dm, index);
7298  }
7299
7300  void Vqdmulh(
7301      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7302    VIXL_ASSERT(allow_macro_instructions_);
7303    VIXL_ASSERT(OutsideITBlock());
7304    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7305    ITScope it_scope(this, &cond);
7306    vqdmulh(cond, dt, rd, rn, rm);
7307  }
7308  void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7309    Vqdmulh(al, dt, rd, rn, rm);
7310  }
7311
7312  void Vqdmulh(
7313      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7314    VIXL_ASSERT(allow_macro_instructions_);
7315    VIXL_ASSERT(OutsideITBlock());
7316    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7317    ITScope it_scope(this, &cond);
7318    vqdmulh(cond, dt, rd, rn, rm);
7319  }
7320  void Vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7321    Vqdmulh(al, dt, rd, rn, rm);
7322  }
7323
7324  void Vqdmulh(Condition cond,
7325               DataType dt,
7326               DRegister rd,
7327               DRegister rn,
7328               DRegisterLane rm) {
7329    VIXL_ASSERT(allow_macro_instructions_);
7330    VIXL_ASSERT(OutsideITBlock());
7331    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7332    ITScope it_scope(this, &cond);
7333    vqdmulh(cond, dt, rd, rn, rm);
7334  }
7335  void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
7336    Vqdmulh(al, dt, rd, rn, rm);
7337  }
7338
7339  void Vqdmulh(Condition cond,
7340               DataType dt,
7341               QRegister rd,
7342               QRegister rn,
7343               DRegisterLane rm) {
7344    VIXL_ASSERT(allow_macro_instructions_);
7345    VIXL_ASSERT(OutsideITBlock());
7346    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7347    ITScope it_scope(this, &cond);
7348    vqdmulh(cond, dt, rd, rn, rm);
7349  }
7350  void Vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
7351    Vqdmulh(al, dt, rd, rn, rm);
7352  }
7353
7354  void Vqdmull(
7355      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7356    VIXL_ASSERT(allow_macro_instructions_);
7357    VIXL_ASSERT(OutsideITBlock());
7358    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7359    ITScope it_scope(this, &cond);
7360    vqdmull(cond, dt, rd, rn, rm);
7361  }
7362  void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7363    Vqdmull(al, dt, rd, rn, rm);
7364  }
7365
7366  void Vqdmull(Condition cond,
7367               DataType dt,
7368               QRegister rd,
7369               DRegister rn,
7370               DRegisterLane rm) {
7371    VIXL_ASSERT(allow_macro_instructions_);
7372    VIXL_ASSERT(OutsideITBlock());
7373    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7374    ITScope it_scope(this, &cond);
7375    vqdmull(cond, dt, rd, rn, rm);
7376  }
7377  void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
7378    Vqdmull(al, dt, rd, rn, rm);
7379  }
7380
7381  void Vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
7382    VIXL_ASSERT(allow_macro_instructions_);
7383    VIXL_ASSERT(OutsideITBlock());
7384    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7385    ITScope it_scope(this, &cond);
7386    vqmovn(cond, dt, rd, rm);
7387  }
7388  void Vqmovn(DataType dt, DRegister rd, QRegister rm) {
7389    Vqmovn(al, dt, rd, rm);
7390  }
7391
7392  void Vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm) {
7393    VIXL_ASSERT(allow_macro_instructions_);
7394    VIXL_ASSERT(OutsideITBlock());
7395    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7396    ITScope it_scope(this, &cond);
7397    vqmovun(cond, dt, rd, rm);
7398  }
7399  void Vqmovun(DataType dt, DRegister rd, QRegister rm) {
7400    Vqmovun(al, dt, rd, rm);
7401  }
7402
7403  void Vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7404    VIXL_ASSERT(allow_macro_instructions_);
7405    VIXL_ASSERT(OutsideITBlock());
7406    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7407    ITScope it_scope(this, &cond);
7408    vqneg(cond, dt, rd, rm);
7409  }
7410  void Vqneg(DataType dt, DRegister rd, DRegister rm) { Vqneg(al, dt, rd, rm); }
7411
7412  void Vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7413    VIXL_ASSERT(allow_macro_instructions_);
7414    VIXL_ASSERT(OutsideITBlock());
7415    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7416    ITScope it_scope(this, &cond);
7417    vqneg(cond, dt, rd, rm);
7418  }
7419  void Vqneg(DataType dt, QRegister rd, QRegister rm) { Vqneg(al, dt, rd, rm); }
7420
7421  void Vqrdmulh(
7422      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7423    VIXL_ASSERT(allow_macro_instructions_);
7424    VIXL_ASSERT(OutsideITBlock());
7425    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7426    ITScope it_scope(this, &cond);
7427    vqrdmulh(cond, dt, rd, rn, rm);
7428  }
7429  void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7430    Vqrdmulh(al, dt, rd, rn, rm);
7431  }
7432
7433  void Vqrdmulh(
7434      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7435    VIXL_ASSERT(allow_macro_instructions_);
7436    VIXL_ASSERT(OutsideITBlock());
7437    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7438    ITScope it_scope(this, &cond);
7439    vqrdmulh(cond, dt, rd, rn, rm);
7440  }
7441  void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7442    Vqrdmulh(al, dt, rd, rn, rm);
7443  }
7444
7445  void Vqrdmulh(Condition cond,
7446                DataType dt,
7447                DRegister rd,
7448                DRegister rn,
7449                DRegisterLane rm) {
7450    VIXL_ASSERT(allow_macro_instructions_);
7451    VIXL_ASSERT(OutsideITBlock());
7452    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7453    ITScope it_scope(this, &cond);
7454    vqrdmulh(cond, dt, rd, rn, rm);
7455  }
7456  void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
7457    Vqrdmulh(al, dt, rd, rn, rm);
7458  }
7459
7460  void Vqrdmulh(Condition cond,
7461                DataType dt,
7462                QRegister rd,
7463                QRegister rn,
7464                DRegisterLane rm) {
7465    VIXL_ASSERT(allow_macro_instructions_);
7466    VIXL_ASSERT(OutsideITBlock());
7467    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7468    ITScope it_scope(this, &cond);
7469    vqrdmulh(cond, dt, rd, rn, rm);
7470  }
7471  void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
7472    Vqrdmulh(al, dt, rd, rn, rm);
7473  }
7474
7475  void Vqrshl(
7476      Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
7477    VIXL_ASSERT(allow_macro_instructions_);
7478    VIXL_ASSERT(OutsideITBlock());
7479    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7480    ITScope it_scope(this, &cond);
7481    vqrshl(cond, dt, rd, rm, rn);
7482  }
7483  void Vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
7484    Vqrshl(al, dt, rd, rm, rn);
7485  }
7486
7487  void Vqrshl(
7488      Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
7489    VIXL_ASSERT(allow_macro_instructions_);
7490    VIXL_ASSERT(OutsideITBlock());
7491    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7492    ITScope it_scope(this, &cond);
7493    vqrshl(cond, dt, rd, rm, rn);
7494  }
7495  void Vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
7496    Vqrshl(al, dt, rd, rm, rn);
7497  }
7498
7499  void Vqrshrn(Condition cond,
7500               DataType dt,
7501               DRegister rd,
7502               QRegister rm,
7503               const QOperand& operand) {
7504    VIXL_ASSERT(allow_macro_instructions_);
7505    VIXL_ASSERT(OutsideITBlock());
7506    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7507    ITScope it_scope(this, &cond);
7508    vqrshrn(cond, dt, rd, rm, operand);
7509  }
7510  void Vqrshrn(DataType dt,
7511               DRegister rd,
7512               QRegister rm,
7513               const QOperand& operand) {
7514    Vqrshrn(al, dt, rd, rm, operand);
7515  }
7516
7517  void Vqrshrun(Condition cond,
7518                DataType dt,
7519                DRegister rd,
7520                QRegister rm,
7521                const QOperand& operand) {
7522    VIXL_ASSERT(allow_macro_instructions_);
7523    VIXL_ASSERT(OutsideITBlock());
7524    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7525    ITScope it_scope(this, &cond);
7526    vqrshrun(cond, dt, rd, rm, operand);
7527  }
7528  void Vqrshrun(DataType dt,
7529                DRegister rd,
7530                QRegister rm,
7531                const QOperand& operand) {
7532    Vqrshrun(al, dt, rd, rm, operand);
7533  }
7534
7535  void Vqshl(Condition cond,
7536             DataType dt,
7537             DRegister rd,
7538             DRegister rm,
7539             const DOperand& operand) {
7540    VIXL_ASSERT(allow_macro_instructions_);
7541    VIXL_ASSERT(OutsideITBlock());
7542    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7543    ITScope it_scope(this, &cond);
7544    vqshl(cond, dt, rd, rm, operand);
7545  }
7546  void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7547    Vqshl(al, dt, rd, rm, operand);
7548  }
7549
7550  void Vqshl(Condition cond,
7551             DataType dt,
7552             QRegister rd,
7553             QRegister rm,
7554             const QOperand& operand) {
7555    VIXL_ASSERT(allow_macro_instructions_);
7556    VIXL_ASSERT(OutsideITBlock());
7557    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7558    ITScope it_scope(this, &cond);
7559    vqshl(cond, dt, rd, rm, operand);
7560  }
7561  void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7562    Vqshl(al, dt, rd, rm, operand);
7563  }
7564
7565  void Vqshlu(Condition cond,
7566              DataType dt,
7567              DRegister rd,
7568              DRegister rm,
7569              const DOperand& operand) {
7570    VIXL_ASSERT(allow_macro_instructions_);
7571    VIXL_ASSERT(OutsideITBlock());
7572    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7573    ITScope it_scope(this, &cond);
7574    vqshlu(cond, dt, rd, rm, operand);
7575  }
7576  void Vqshlu(DataType dt,
7577              DRegister rd,
7578              DRegister rm,
7579              const DOperand& operand) {
7580    Vqshlu(al, dt, rd, rm, operand);
7581  }
7582
7583  void Vqshlu(Condition cond,
7584              DataType dt,
7585              QRegister rd,
7586              QRegister rm,
7587              const QOperand& operand) {
7588    VIXL_ASSERT(allow_macro_instructions_);
7589    VIXL_ASSERT(OutsideITBlock());
7590    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7591    ITScope it_scope(this, &cond);
7592    vqshlu(cond, dt, rd, rm, operand);
7593  }
7594  void Vqshlu(DataType dt,
7595              QRegister rd,
7596              QRegister rm,
7597              const QOperand& operand) {
7598    Vqshlu(al, dt, rd, rm, operand);
7599  }
7600
7601  void Vqshrn(Condition cond,
7602              DataType dt,
7603              DRegister rd,
7604              QRegister rm,
7605              const QOperand& operand) {
7606    VIXL_ASSERT(allow_macro_instructions_);
7607    VIXL_ASSERT(OutsideITBlock());
7608    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7609    ITScope it_scope(this, &cond);
7610    vqshrn(cond, dt, rd, rm, operand);
7611  }
7612  void Vqshrn(DataType dt,
7613              DRegister rd,
7614              QRegister rm,
7615              const QOperand& operand) {
7616    Vqshrn(al, dt, rd, rm, operand);
7617  }
7618
7619  void Vqshrun(Condition cond,
7620               DataType dt,
7621               DRegister rd,
7622               QRegister rm,
7623               const QOperand& operand) {
7624    VIXL_ASSERT(allow_macro_instructions_);
7625    VIXL_ASSERT(OutsideITBlock());
7626    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7627    ITScope it_scope(this, &cond);
7628    vqshrun(cond, dt, rd, rm, operand);
7629  }
7630  void Vqshrun(DataType dt,
7631               DRegister rd,
7632               QRegister rm,
7633               const QOperand& operand) {
7634    Vqshrun(al, dt, rd, rm, operand);
7635  }
7636
7637  void Vqsub(
7638      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7639    VIXL_ASSERT(allow_macro_instructions_);
7640    VIXL_ASSERT(OutsideITBlock());
7641    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7642    ITScope it_scope(this, &cond);
7643    vqsub(cond, dt, rd, rn, rm);
7644  }
7645  void Vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7646    Vqsub(al, dt, rd, rn, rm);
7647  }
7648
7649  void Vqsub(
7650      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7651    VIXL_ASSERT(allow_macro_instructions_);
7652    VIXL_ASSERT(OutsideITBlock());
7653    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7654    ITScope it_scope(this, &cond);
7655    vqsub(cond, dt, rd, rn, rm);
7656  }
7657  void Vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7658    Vqsub(al, dt, rd, rn, rm);
7659  }
7660
7661  void Vraddhn(
7662      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
7663    VIXL_ASSERT(allow_macro_instructions_);
7664    VIXL_ASSERT(OutsideITBlock());
7665    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7666    ITScope it_scope(this, &cond);
7667    vraddhn(cond, dt, rd, rn, rm);
7668  }
7669  void Vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
7670    Vraddhn(al, dt, rd, rn, rm);
7671  }
7672
7673  void Vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7674    VIXL_ASSERT(allow_macro_instructions_);
7675    VIXL_ASSERT(OutsideITBlock());
7676    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7677    ITScope it_scope(this, &cond);
7678    vrecpe(cond, dt, rd, rm);
7679  }
7680  void Vrecpe(DataType dt, DRegister rd, DRegister rm) {
7681    Vrecpe(al, dt, rd, rm);
7682  }
7683
7684  void Vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7685    VIXL_ASSERT(allow_macro_instructions_);
7686    VIXL_ASSERT(OutsideITBlock());
7687    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7688    ITScope it_scope(this, &cond);
7689    vrecpe(cond, dt, rd, rm);
7690  }
7691  void Vrecpe(DataType dt, QRegister rd, QRegister rm) {
7692    Vrecpe(al, dt, rd, rm);
7693  }
7694
7695  void Vrecps(
7696      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7697    VIXL_ASSERT(allow_macro_instructions_);
7698    VIXL_ASSERT(OutsideITBlock());
7699    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7700    ITScope it_scope(this, &cond);
7701    vrecps(cond, dt, rd, rn, rm);
7702  }
7703  void Vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7704    Vrecps(al, dt, rd, rn, rm);
7705  }
7706
7707  void Vrecps(
7708      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7709    VIXL_ASSERT(allow_macro_instructions_);
7710    VIXL_ASSERT(OutsideITBlock());
7711    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7712    ITScope it_scope(this, &cond);
7713    vrecps(cond, dt, rd, rn, rm);
7714  }
7715  void Vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7716    Vrecps(al, dt, rd, rn, rm);
7717  }
7718
7719  void Vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7720    VIXL_ASSERT(allow_macro_instructions_);
7721    VIXL_ASSERT(OutsideITBlock());
7722    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7723    ITScope it_scope(this, &cond);
7724    vrev16(cond, dt, rd, rm);
7725  }
7726  void Vrev16(DataType dt, DRegister rd, DRegister rm) {
7727    Vrev16(al, dt, rd, rm);
7728  }
7729
7730  void Vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7731    VIXL_ASSERT(allow_macro_instructions_);
7732    VIXL_ASSERT(OutsideITBlock());
7733    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7734    ITScope it_scope(this, &cond);
7735    vrev16(cond, dt, rd, rm);
7736  }
7737  void Vrev16(DataType dt, QRegister rd, QRegister rm) {
7738    Vrev16(al, dt, rd, rm);
7739  }
7740
7741  void Vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7742    VIXL_ASSERT(allow_macro_instructions_);
7743    VIXL_ASSERT(OutsideITBlock());
7744    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7745    ITScope it_scope(this, &cond);
7746    vrev32(cond, dt, rd, rm);
7747  }
7748  void Vrev32(DataType dt, DRegister rd, DRegister rm) {
7749    Vrev32(al, dt, rd, rm);
7750  }
7751
7752  void Vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7753    VIXL_ASSERT(allow_macro_instructions_);
7754    VIXL_ASSERT(OutsideITBlock());
7755    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7756    ITScope it_scope(this, &cond);
7757    vrev32(cond, dt, rd, rm);
7758  }
7759  void Vrev32(DataType dt, QRegister rd, QRegister rm) {
7760    Vrev32(al, dt, rd, rm);
7761  }
7762
7763  void Vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7764    VIXL_ASSERT(allow_macro_instructions_);
7765    VIXL_ASSERT(OutsideITBlock());
7766    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7767    ITScope it_scope(this, &cond);
7768    vrev64(cond, dt, rd, rm);
7769  }
7770  void Vrev64(DataType dt, DRegister rd, DRegister rm) {
7771    Vrev64(al, dt, rd, rm);
7772  }
7773
7774  void Vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7775    VIXL_ASSERT(allow_macro_instructions_);
7776    VIXL_ASSERT(OutsideITBlock());
7777    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7778    ITScope it_scope(this, &cond);
7779    vrev64(cond, dt, rd, rm);
7780  }
7781  void Vrev64(DataType dt, QRegister rd, QRegister rm) {
7782    Vrev64(al, dt, rd, rm);
7783  }
7784
7785  void Vrhadd(
7786      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7787    VIXL_ASSERT(allow_macro_instructions_);
7788    VIXL_ASSERT(OutsideITBlock());
7789    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7790    ITScope it_scope(this, &cond);
7791    vrhadd(cond, dt, rd, rn, rm);
7792  }
7793  void Vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7794    Vrhadd(al, dt, rd, rn, rm);
7795  }
7796
7797  void Vrhadd(
7798      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7799    VIXL_ASSERT(allow_macro_instructions_);
7800    VIXL_ASSERT(OutsideITBlock());
7801    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7802    ITScope it_scope(this, &cond);
7803    vrhadd(cond, dt, rd, rn, rm);
7804  }
7805  void Vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7806    Vrhadd(al, dt, rd, rn, rm);
7807  }
7808
7809  void Vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7810    VIXL_ASSERT(allow_macro_instructions_);
7811    VIXL_ASSERT(OutsideITBlock());
7812    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7813    vrinta(dt1, dt2, rd, rm);
7814  }
7815
7816  void Vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7817    VIXL_ASSERT(allow_macro_instructions_);
7818    VIXL_ASSERT(OutsideITBlock());
7819    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7820    vrinta(dt1, dt2, rd, rm);
7821  }
7822
7823  void Vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7824    VIXL_ASSERT(allow_macro_instructions_);
7825    VIXL_ASSERT(OutsideITBlock());
7826    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7827    vrinta(dt1, dt2, rd, rm);
7828  }
7829
7830  void Vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7831    VIXL_ASSERT(allow_macro_instructions_);
7832    VIXL_ASSERT(OutsideITBlock());
7833    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7834    vrintm(dt1, dt2, rd, rm);
7835  }
7836
7837  void Vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7838    VIXL_ASSERT(allow_macro_instructions_);
7839    VIXL_ASSERT(OutsideITBlock());
7840    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7841    vrintm(dt1, dt2, rd, rm);
7842  }
7843
7844  void Vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7845    VIXL_ASSERT(allow_macro_instructions_);
7846    VIXL_ASSERT(OutsideITBlock());
7847    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7848    vrintm(dt1, dt2, rd, rm);
7849  }
7850
7851  void Vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7852    VIXL_ASSERT(allow_macro_instructions_);
7853    VIXL_ASSERT(OutsideITBlock());
7854    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7855    vrintn(dt1, dt2, rd, rm);
7856  }
7857
7858  void Vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7859    VIXL_ASSERT(allow_macro_instructions_);
7860    VIXL_ASSERT(OutsideITBlock());
7861    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7862    vrintn(dt1, dt2, rd, rm);
7863  }
7864
7865  void Vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7866    VIXL_ASSERT(allow_macro_instructions_);
7867    VIXL_ASSERT(OutsideITBlock());
7868    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7869    vrintn(dt1, dt2, rd, rm);
7870  }
7871
7872  void Vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7873    VIXL_ASSERT(allow_macro_instructions_);
7874    VIXL_ASSERT(OutsideITBlock());
7875    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7876    vrintp(dt1, dt2, rd, rm);
7877  }
7878
7879  void Vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7880    VIXL_ASSERT(allow_macro_instructions_);
7881    VIXL_ASSERT(OutsideITBlock());
7882    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7883    vrintp(dt1, dt2, rd, rm);
7884  }
7885
7886  void Vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7887    VIXL_ASSERT(allow_macro_instructions_);
7888    VIXL_ASSERT(OutsideITBlock());
7889    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7890    vrintp(dt1, dt2, rd, rm);
7891  }
7892
7893  void Vrintr(
7894      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7895    VIXL_ASSERT(allow_macro_instructions_);
7896    VIXL_ASSERT(OutsideITBlock());
7897    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7898    ITScope it_scope(this, &cond);
7899    vrintr(cond, dt1, dt2, rd, rm);
7900  }
7901  void Vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7902    Vrintr(al, dt1, dt2, rd, rm);
7903  }
7904
7905  void Vrintr(
7906      Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7907    VIXL_ASSERT(allow_macro_instructions_);
7908    VIXL_ASSERT(OutsideITBlock());
7909    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7910    ITScope it_scope(this, &cond);
7911    vrintr(cond, dt1, dt2, rd, rm);
7912  }
7913  void Vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7914    Vrintr(al, dt1, dt2, rd, rm);
7915  }
7916
7917  void Vrintx(
7918      Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7919    VIXL_ASSERT(allow_macro_instructions_);
7920    VIXL_ASSERT(OutsideITBlock());
7921    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7922    ITScope it_scope(this, &cond);
7923    vrintx(cond, dt1, dt2, rd, rm);
7924  }
7925  void Vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7926    Vrintx(al, dt1, dt2, rd, rm);
7927  }
7928
7929  void Vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7930    VIXL_ASSERT(allow_macro_instructions_);
7931    VIXL_ASSERT(OutsideITBlock());
7932    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7933    vrintx(dt1, dt2, rd, rm);
7934  }
7935
7936  void Vrintx(
7937      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7938    VIXL_ASSERT(allow_macro_instructions_);
7939    VIXL_ASSERT(OutsideITBlock());
7940    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7941    ITScope it_scope(this, &cond);
7942    vrintx(cond, dt1, dt2, rd, rm);
7943  }
7944  void Vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7945    Vrintx(al, dt1, dt2, rd, rm);
7946  }
7947
7948  void Vrintz(
7949      Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7950    VIXL_ASSERT(allow_macro_instructions_);
7951    VIXL_ASSERT(OutsideITBlock());
7952    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7953    ITScope it_scope(this, &cond);
7954    vrintz(cond, dt1, dt2, rd, rm);
7955  }
7956  void Vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7957    Vrintz(al, dt1, dt2, rd, rm);
7958  }
7959
7960  void Vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7961    VIXL_ASSERT(allow_macro_instructions_);
7962    VIXL_ASSERT(OutsideITBlock());
7963    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7964    vrintz(dt1, dt2, rd, rm);
7965  }
7966
7967  void Vrintz(
7968      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7969    VIXL_ASSERT(allow_macro_instructions_);
7970    VIXL_ASSERT(OutsideITBlock());
7971    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7972    ITScope it_scope(this, &cond);
7973    vrintz(cond, dt1, dt2, rd, rm);
7974  }
7975  void Vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7976    Vrintz(al, dt1, dt2, rd, rm);
7977  }
7978
7979  void Vrshl(
7980      Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
7981    VIXL_ASSERT(allow_macro_instructions_);
7982    VIXL_ASSERT(OutsideITBlock());
7983    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7984    ITScope it_scope(this, &cond);
7985    vrshl(cond, dt, rd, rm, rn);
7986  }
7987  void Vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
7988    Vrshl(al, dt, rd, rm, rn);
7989  }
7990
7991  void Vrshl(
7992      Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
7993    VIXL_ASSERT(allow_macro_instructions_);
7994    VIXL_ASSERT(OutsideITBlock());
7995    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
7996    ITScope it_scope(this, &cond);
7997    vrshl(cond, dt, rd, rm, rn);
7998  }
7999  void Vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
8000    Vrshl(al, dt, rd, rm, rn);
8001  }
8002
8003  void Vrshr(Condition cond,
8004             DataType dt,
8005             DRegister rd,
8006             DRegister rm,
8007             const DOperand& operand) {
8008    VIXL_ASSERT(allow_macro_instructions_);
8009    VIXL_ASSERT(OutsideITBlock());
8010    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8011    ITScope it_scope(this, &cond);
8012    vrshr(cond, dt, rd, rm, operand);
8013  }
8014  void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8015    Vrshr(al, dt, rd, rm, operand);
8016  }
8017
8018  void Vrshr(Condition cond,
8019             DataType dt,
8020             QRegister rd,
8021             QRegister rm,
8022             const QOperand& operand) {
8023    VIXL_ASSERT(allow_macro_instructions_);
8024    VIXL_ASSERT(OutsideITBlock());
8025    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8026    ITScope it_scope(this, &cond);
8027    vrshr(cond, dt, rd, rm, operand);
8028  }
8029  void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8030    Vrshr(al, dt, rd, rm, operand);
8031  }
8032
8033  void Vrshrn(Condition cond,
8034              DataType dt,
8035              DRegister rd,
8036              QRegister rm,
8037              const QOperand& operand) {
8038    VIXL_ASSERT(allow_macro_instructions_);
8039    VIXL_ASSERT(OutsideITBlock());
8040    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8041    ITScope it_scope(this, &cond);
8042    vrshrn(cond, dt, rd, rm, operand);
8043  }
8044  void Vrshrn(DataType dt,
8045              DRegister rd,
8046              QRegister rm,
8047              const QOperand& operand) {
8048    Vrshrn(al, dt, rd, rm, operand);
8049  }
8050
8051  void Vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8052    VIXL_ASSERT(allow_macro_instructions_);
8053    VIXL_ASSERT(OutsideITBlock());
8054    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8055    ITScope it_scope(this, &cond);
8056    vrsqrte(cond, dt, rd, rm);
8057  }
8058  void Vrsqrte(DataType dt, DRegister rd, DRegister rm) {
8059    Vrsqrte(al, dt, rd, rm);
8060  }
8061
8062  void Vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8063    VIXL_ASSERT(allow_macro_instructions_);
8064    VIXL_ASSERT(OutsideITBlock());
8065    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8066    ITScope it_scope(this, &cond);
8067    vrsqrte(cond, dt, rd, rm);
8068  }
8069  void Vrsqrte(DataType dt, QRegister rd, QRegister rm) {
8070    Vrsqrte(al, dt, rd, rm);
8071  }
8072
8073  void Vrsqrts(
8074      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8075    VIXL_ASSERT(allow_macro_instructions_);
8076    VIXL_ASSERT(OutsideITBlock());
8077    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8078    ITScope it_scope(this, &cond);
8079    vrsqrts(cond, dt, rd, rn, rm);
8080  }
8081  void Vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8082    Vrsqrts(al, dt, rd, rn, rm);
8083  }
8084
8085  void Vrsqrts(
8086      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8087    VIXL_ASSERT(allow_macro_instructions_);
8088    VIXL_ASSERT(OutsideITBlock());
8089    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8090    ITScope it_scope(this, &cond);
8091    vrsqrts(cond, dt, rd, rn, rm);
8092  }
8093  void Vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8094    Vrsqrts(al, dt, rd, rn, rm);
8095  }
8096
8097  void Vrsra(Condition cond,
8098             DataType dt,
8099             DRegister rd,
8100             DRegister rm,
8101             const DOperand& operand) {
8102    VIXL_ASSERT(allow_macro_instructions_);
8103    VIXL_ASSERT(OutsideITBlock());
8104    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8105    ITScope it_scope(this, &cond);
8106    vrsra(cond, dt, rd, rm, operand);
8107  }
8108  void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8109    Vrsra(al, dt, rd, rm, operand);
8110  }
8111
8112  void Vrsra(Condition cond,
8113             DataType dt,
8114             QRegister rd,
8115             QRegister rm,
8116             const QOperand& operand) {
8117    VIXL_ASSERT(allow_macro_instructions_);
8118    VIXL_ASSERT(OutsideITBlock());
8119    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8120    ITScope it_scope(this, &cond);
8121    vrsra(cond, dt, rd, rm, operand);
8122  }
8123  void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8124    Vrsra(al, dt, rd, rm, operand);
8125  }
8126
8127  void Vrsubhn(
8128      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
8129    VIXL_ASSERT(allow_macro_instructions_);
8130    VIXL_ASSERT(OutsideITBlock());
8131    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8132    ITScope it_scope(this, &cond);
8133    vrsubhn(cond, dt, rd, rn, rm);
8134  }
8135  void Vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
8136    Vrsubhn(al, dt, rd, rn, rm);
8137  }
8138
8139  void Vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8140    VIXL_ASSERT(allow_macro_instructions_);
8141    VIXL_ASSERT(OutsideITBlock());
8142    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8143    vseleq(dt, rd, rn, rm);
8144  }
8145
8146  void Vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8147    VIXL_ASSERT(allow_macro_instructions_);
8148    VIXL_ASSERT(OutsideITBlock());
8149    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8150    vseleq(dt, rd, rn, rm);
8151  }
8152
8153  void Vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8154    VIXL_ASSERT(allow_macro_instructions_);
8155    VIXL_ASSERT(OutsideITBlock());
8156    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8157    vselge(dt, rd, rn, rm);
8158  }
8159
8160  void Vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8161    VIXL_ASSERT(allow_macro_instructions_);
8162    VIXL_ASSERT(OutsideITBlock());
8163    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8164    vselge(dt, rd, rn, rm);
8165  }
8166
8167  void Vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8168    VIXL_ASSERT(allow_macro_instructions_);
8169    VIXL_ASSERT(OutsideITBlock());
8170    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8171    vselgt(dt, rd, rn, rm);
8172  }
8173
8174  void Vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8175    VIXL_ASSERT(allow_macro_instructions_);
8176    VIXL_ASSERT(OutsideITBlock());
8177    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8178    vselgt(dt, rd, rn, rm);
8179  }
8180
8181  void Vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8182    VIXL_ASSERT(allow_macro_instructions_);
8183    VIXL_ASSERT(OutsideITBlock());
8184    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8185    vselvs(dt, rd, rn, rm);
8186  }
8187
8188  void Vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8189    VIXL_ASSERT(allow_macro_instructions_);
8190    VIXL_ASSERT(OutsideITBlock());
8191    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8192    vselvs(dt, rd, rn, rm);
8193  }
8194
8195  void Vshl(Condition cond,
8196            DataType dt,
8197            DRegister rd,
8198            DRegister rm,
8199            const DOperand& operand) {
8200    VIXL_ASSERT(allow_macro_instructions_);
8201    VIXL_ASSERT(OutsideITBlock());
8202    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8203    ITScope it_scope(this, &cond);
8204    vshl(cond, dt, rd, rm, operand);
8205  }
8206  void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8207    Vshl(al, dt, rd, rm, operand);
8208  }
8209
8210  void Vshl(Condition cond,
8211            DataType dt,
8212            QRegister rd,
8213            QRegister rm,
8214            const QOperand& operand) {
8215    VIXL_ASSERT(allow_macro_instructions_);
8216    VIXL_ASSERT(OutsideITBlock());
8217    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8218    ITScope it_scope(this, &cond);
8219    vshl(cond, dt, rd, rm, operand);
8220  }
8221  void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8222    Vshl(al, dt, rd, rm, operand);
8223  }
8224
8225  void Vshll(Condition cond,
8226             DataType dt,
8227             QRegister rd,
8228             DRegister rm,
8229             const DOperand& operand) {
8230    VIXL_ASSERT(allow_macro_instructions_);
8231    VIXL_ASSERT(OutsideITBlock());
8232    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8233    ITScope it_scope(this, &cond);
8234    vshll(cond, dt, rd, rm, operand);
8235  }
8236  void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) {
8237    Vshll(al, dt, rd, rm, operand);
8238  }
8239
8240  void Vshr(Condition cond,
8241            DataType dt,
8242            DRegister rd,
8243            DRegister rm,
8244            const DOperand& operand) {
8245    VIXL_ASSERT(allow_macro_instructions_);
8246    VIXL_ASSERT(OutsideITBlock());
8247    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8248    ITScope it_scope(this, &cond);
8249    vshr(cond, dt, rd, rm, operand);
8250  }
8251  void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8252    Vshr(al, dt, rd, rm, operand);
8253  }
8254
8255  void Vshr(Condition cond,
8256            DataType dt,
8257            QRegister rd,
8258            QRegister rm,
8259            const QOperand& operand) {
8260    VIXL_ASSERT(allow_macro_instructions_);
8261    VIXL_ASSERT(OutsideITBlock());
8262    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8263    ITScope it_scope(this, &cond);
8264    vshr(cond, dt, rd, rm, operand);
8265  }
8266  void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8267    Vshr(al, dt, rd, rm, operand);
8268  }
8269
8270  void Vshrn(Condition cond,
8271             DataType dt,
8272             DRegister rd,
8273             QRegister rm,
8274             const QOperand& operand) {
8275    VIXL_ASSERT(allow_macro_instructions_);
8276    VIXL_ASSERT(OutsideITBlock());
8277    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8278    ITScope it_scope(this, &cond);
8279    vshrn(cond, dt, rd, rm, operand);
8280  }
8281  void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) {
8282    Vshrn(al, dt, rd, rm, operand);
8283  }
8284
8285  void Vsli(Condition cond,
8286            DataType dt,
8287            DRegister rd,
8288            DRegister rm,
8289            const DOperand& operand) {
8290    VIXL_ASSERT(allow_macro_instructions_);
8291    VIXL_ASSERT(OutsideITBlock());
8292    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8293    ITScope it_scope(this, &cond);
8294    vsli(cond, dt, rd, rm, operand);
8295  }
8296  void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8297    Vsli(al, dt, rd, rm, operand);
8298  }
8299
8300  void Vsli(Condition cond,
8301            DataType dt,
8302            QRegister rd,
8303            QRegister rm,
8304            const QOperand& operand) {
8305    VIXL_ASSERT(allow_macro_instructions_);
8306    VIXL_ASSERT(OutsideITBlock());
8307    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8308    ITScope it_scope(this, &cond);
8309    vsli(cond, dt, rd, rm, operand);
8310  }
8311  void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8312    Vsli(al, dt, rd, rm, operand);
8313  }
8314
8315  void Vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {
8316    VIXL_ASSERT(allow_macro_instructions_);
8317    VIXL_ASSERT(OutsideITBlock());
8318    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8319    ITScope it_scope(this, &cond);
8320    vsqrt(cond, dt, rd, rm);
8321  }
8322  void Vsqrt(DataType dt, SRegister rd, SRegister rm) { Vsqrt(al, dt, rd, rm); }
8323
8324  void Vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8325    VIXL_ASSERT(allow_macro_instructions_);
8326    VIXL_ASSERT(OutsideITBlock());
8327    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8328    ITScope it_scope(this, &cond);
8329    vsqrt(cond, dt, rd, rm);
8330  }
8331  void Vsqrt(DataType dt, DRegister rd, DRegister rm) { Vsqrt(al, dt, rd, rm); }
8332
8333  void Vsra(Condition cond,
8334            DataType dt,
8335            DRegister rd,
8336            DRegister rm,
8337            const DOperand& operand) {
8338    VIXL_ASSERT(allow_macro_instructions_);
8339    VIXL_ASSERT(OutsideITBlock());
8340    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8341    ITScope it_scope(this, &cond);
8342    vsra(cond, dt, rd, rm, operand);
8343  }
8344  void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8345    Vsra(al, dt, rd, rm, operand);
8346  }
8347
8348  void Vsra(Condition cond,
8349            DataType dt,
8350            QRegister rd,
8351            QRegister rm,
8352            const QOperand& operand) {
8353    VIXL_ASSERT(allow_macro_instructions_);
8354    VIXL_ASSERT(OutsideITBlock());
8355    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8356    ITScope it_scope(this, &cond);
8357    vsra(cond, dt, rd, rm, operand);
8358  }
8359  void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8360    Vsra(al, dt, rd, rm, operand);
8361  }
8362
8363  void Vsri(Condition cond,
8364            DataType dt,
8365            DRegister rd,
8366            DRegister rm,
8367            const DOperand& operand) {
8368    VIXL_ASSERT(allow_macro_instructions_);
8369    VIXL_ASSERT(OutsideITBlock());
8370    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8371    ITScope it_scope(this, &cond);
8372    vsri(cond, dt, rd, rm, operand);
8373  }
8374  void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8375    Vsri(al, dt, rd, rm, operand);
8376  }
8377
8378  void Vsri(Condition cond,
8379            DataType dt,
8380            QRegister rd,
8381            QRegister rm,
8382            const QOperand& operand) {
8383    VIXL_ASSERT(allow_macro_instructions_);
8384    VIXL_ASSERT(OutsideITBlock());
8385    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8386    ITScope it_scope(this, &cond);
8387    vsri(cond, dt, rd, rm, operand);
8388  }
8389  void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8390    Vsri(al, dt, rd, rm, operand);
8391  }
8392
8393  void Vst1(Condition cond,
8394            DataType dt,
8395            const NeonRegisterList& nreglist,
8396            const AlignedMemOperand& operand) {
8397    VIXL_ASSERT(allow_macro_instructions_);
8398    VIXL_ASSERT(OutsideITBlock());
8399    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8400    ITScope it_scope(this, &cond);
8401    vst1(cond, dt, nreglist, operand);
8402  }
8403  void Vst1(DataType dt,
8404            const NeonRegisterList& nreglist,
8405            const AlignedMemOperand& operand) {
8406    Vst1(al, dt, nreglist, operand);
8407  }
8408
8409  void Vst2(Condition cond,
8410            DataType dt,
8411            const NeonRegisterList& nreglist,
8412            const AlignedMemOperand& operand) {
8413    VIXL_ASSERT(allow_macro_instructions_);
8414    VIXL_ASSERT(OutsideITBlock());
8415    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8416    ITScope it_scope(this, &cond);
8417    vst2(cond, dt, nreglist, operand);
8418  }
8419  void Vst2(DataType dt,
8420            const NeonRegisterList& nreglist,
8421            const AlignedMemOperand& operand) {
8422    Vst2(al, dt, nreglist, operand);
8423  }
8424
8425  void Vst3(Condition cond,
8426            DataType dt,
8427            const NeonRegisterList& nreglist,
8428            const AlignedMemOperand& operand) {
8429    VIXL_ASSERT(allow_macro_instructions_);
8430    VIXL_ASSERT(OutsideITBlock());
8431    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8432    ITScope it_scope(this, &cond);
8433    vst3(cond, dt, nreglist, operand);
8434  }
8435  void Vst3(DataType dt,
8436            const NeonRegisterList& nreglist,
8437            const AlignedMemOperand& operand) {
8438    Vst3(al, dt, nreglist, operand);
8439  }
8440
8441  void Vst3(Condition cond,
8442            DataType dt,
8443            const NeonRegisterList& nreglist,
8444            const MemOperand& operand) {
8445    VIXL_ASSERT(allow_macro_instructions_);
8446    VIXL_ASSERT(OutsideITBlock());
8447    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8448    ITScope it_scope(this, &cond);
8449    vst3(cond, dt, nreglist, operand);
8450  }
8451  void Vst3(DataType dt,
8452            const NeonRegisterList& nreglist,
8453            const MemOperand& operand) {
8454    Vst3(al, dt, nreglist, operand);
8455  }
8456
8457  void Vst4(Condition cond,
8458            DataType dt,
8459            const NeonRegisterList& nreglist,
8460            const AlignedMemOperand& operand) {
8461    VIXL_ASSERT(allow_macro_instructions_);
8462    VIXL_ASSERT(OutsideITBlock());
8463    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8464    ITScope it_scope(this, &cond);
8465    vst4(cond, dt, nreglist, operand);
8466  }
8467  void Vst4(DataType dt,
8468            const NeonRegisterList& nreglist,
8469            const AlignedMemOperand& operand) {
8470    Vst4(al, dt, nreglist, operand);
8471  }
8472
8473  void Vstm(Condition cond,
8474            DataType dt,
8475            Register rn,
8476            WriteBack write_back,
8477            DRegisterList dreglist) {
8478    VIXL_ASSERT(allow_macro_instructions_);
8479    VIXL_ASSERT(OutsideITBlock());
8480    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8481    ITScope it_scope(this, &cond);
8482    vstm(cond, dt, rn, write_back, dreglist);
8483  }
8484  void Vstm(DataType dt,
8485            Register rn,
8486            WriteBack write_back,
8487            DRegisterList dreglist) {
8488    Vstm(al, dt, rn, write_back, dreglist);
8489  }
8490  void Vstm(Condition cond,
8491            Register rn,
8492            WriteBack write_back,
8493            DRegisterList dreglist) {
8494    Vstm(cond, kDataTypeValueNone, rn, write_back, dreglist);
8495  }
8496  void Vstm(Register rn, WriteBack write_back, DRegisterList dreglist) {
8497    Vstm(al, kDataTypeValueNone, rn, write_back, dreglist);
8498  }
8499
8500  void Vstm(Condition cond,
8501            DataType dt,
8502            Register rn,
8503            WriteBack write_back,
8504            SRegisterList sreglist) {
8505    VIXL_ASSERT(allow_macro_instructions_);
8506    VIXL_ASSERT(OutsideITBlock());
8507    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8508    ITScope it_scope(this, &cond);
8509    vstm(cond, dt, rn, write_back, sreglist);
8510  }
8511  void Vstm(DataType dt,
8512            Register rn,
8513            WriteBack write_back,
8514            SRegisterList sreglist) {
8515    Vstm(al, dt, rn, write_back, sreglist);
8516  }
8517  void Vstm(Condition cond,
8518            Register rn,
8519            WriteBack write_back,
8520            SRegisterList sreglist) {
8521    Vstm(cond, kDataTypeValueNone, rn, write_back, sreglist);
8522  }
8523  void Vstm(Register rn, WriteBack write_back, SRegisterList sreglist) {
8524    Vstm(al, kDataTypeValueNone, rn, write_back, sreglist);
8525  }
8526
8527  void Vstmdb(Condition cond,
8528              DataType dt,
8529              Register rn,
8530              WriteBack write_back,
8531              DRegisterList dreglist) {
8532    VIXL_ASSERT(allow_macro_instructions_);
8533    VIXL_ASSERT(OutsideITBlock());
8534    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8535    ITScope it_scope(this, &cond);
8536    vstmdb(cond, dt, rn, write_back, dreglist);
8537  }
8538  void Vstmdb(DataType dt,
8539              Register rn,
8540              WriteBack write_back,
8541              DRegisterList dreglist) {
8542    Vstmdb(al, dt, rn, write_back, dreglist);
8543  }
8544  void Vstmdb(Condition cond,
8545              Register rn,
8546              WriteBack write_back,
8547              DRegisterList dreglist) {
8548    Vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist);
8549  }
8550  void Vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) {
8551    Vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist);
8552  }
8553
8554  void Vstmdb(Condition cond,
8555              DataType dt,
8556              Register rn,
8557              WriteBack write_back,
8558              SRegisterList sreglist) {
8559    VIXL_ASSERT(allow_macro_instructions_);
8560    VIXL_ASSERT(OutsideITBlock());
8561    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8562    ITScope it_scope(this, &cond);
8563    vstmdb(cond, dt, rn, write_back, sreglist);
8564  }
8565  void Vstmdb(DataType dt,
8566              Register rn,
8567              WriteBack write_back,
8568              SRegisterList sreglist) {
8569    Vstmdb(al, dt, rn, write_back, sreglist);
8570  }
8571  void Vstmdb(Condition cond,
8572              Register rn,
8573              WriteBack write_back,
8574              SRegisterList sreglist) {
8575    Vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist);
8576  }
8577  void Vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) {
8578    Vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist);
8579  }
8580
8581  void Vstmia(Condition cond,
8582              DataType dt,
8583              Register rn,
8584              WriteBack write_back,
8585              DRegisterList dreglist) {
8586    VIXL_ASSERT(allow_macro_instructions_);
8587    VIXL_ASSERT(OutsideITBlock());
8588    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8589    ITScope it_scope(this, &cond);
8590    vstmia(cond, dt, rn, write_back, dreglist);
8591  }
8592  void Vstmia(DataType dt,
8593              Register rn,
8594              WriteBack write_back,
8595              DRegisterList dreglist) {
8596    Vstmia(al, dt, rn, write_back, dreglist);
8597  }
8598  void Vstmia(Condition cond,
8599              Register rn,
8600              WriteBack write_back,
8601              DRegisterList dreglist) {
8602    Vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist);
8603  }
8604  void Vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) {
8605    Vstmia(al, kDataTypeValueNone, rn, write_back, dreglist);
8606  }
8607
8608  void Vstmia(Condition cond,
8609              DataType dt,
8610              Register rn,
8611              WriteBack write_back,
8612              SRegisterList sreglist) {
8613    VIXL_ASSERT(allow_macro_instructions_);
8614    VIXL_ASSERT(OutsideITBlock());
8615    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8616    ITScope it_scope(this, &cond);
8617    vstmia(cond, dt, rn, write_back, sreglist);
8618  }
8619  void Vstmia(DataType dt,
8620              Register rn,
8621              WriteBack write_back,
8622              SRegisterList sreglist) {
8623    Vstmia(al, dt, rn, write_back, sreglist);
8624  }
8625  void Vstmia(Condition cond,
8626              Register rn,
8627              WriteBack write_back,
8628              SRegisterList sreglist) {
8629    Vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist);
8630  }
8631  void Vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) {
8632    Vstmia(al, kDataTypeValueNone, rn, write_back, sreglist);
8633  }
8634
8635  void Vstr(Condition cond,
8636            DataType dt,
8637            DRegister rd,
8638            const MemOperand& operand) {
8639    VIXL_ASSERT(allow_macro_instructions_);
8640    VIXL_ASSERT(OutsideITBlock());
8641    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8642    ITScope it_scope(this, &cond);
8643    vstr(cond, dt, rd, operand);
8644  }
8645  void Vstr(DataType dt, DRegister rd, const MemOperand& operand) {
8646    Vstr(al, dt, rd, operand);
8647  }
8648  void Vstr(Condition cond, DRegister rd, const MemOperand& operand) {
8649    Vstr(cond, Untyped64, rd, operand);
8650  }
8651  void Vstr(DRegister rd, const MemOperand& operand) {
8652    Vstr(al, Untyped64, rd, operand);
8653  }
8654
8655  void Vstr(Condition cond,
8656            DataType dt,
8657            SRegister rd,
8658            const MemOperand& operand) {
8659    VIXL_ASSERT(allow_macro_instructions_);
8660    VIXL_ASSERT(OutsideITBlock());
8661    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8662    ITScope it_scope(this, &cond);
8663    vstr(cond, dt, rd, operand);
8664  }
8665  void Vstr(DataType dt, SRegister rd, const MemOperand& operand) {
8666    Vstr(al, dt, rd, operand);
8667  }
8668  void Vstr(Condition cond, SRegister rd, const MemOperand& operand) {
8669    Vstr(cond, Untyped32, rd, operand);
8670  }
8671  void Vstr(SRegister rd, const MemOperand& operand) {
8672    Vstr(al, Untyped32, rd, operand);
8673  }
8674
8675  void Vsub(
8676      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8677    VIXL_ASSERT(allow_macro_instructions_);
8678    VIXL_ASSERT(OutsideITBlock());
8679    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8680    ITScope it_scope(this, &cond);
8681    vsub(cond, dt, rd, rn, rm);
8682  }
8683  void Vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8684    Vsub(al, dt, rd, rn, rm);
8685  }
8686
8687  void Vsub(
8688      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8689    VIXL_ASSERT(allow_macro_instructions_);
8690    VIXL_ASSERT(OutsideITBlock());
8691    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8692    ITScope it_scope(this, &cond);
8693    vsub(cond, dt, rd, rn, rm);
8694  }
8695  void Vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8696    Vsub(al, dt, rd, rn, rm);
8697  }
8698
8699  void Vsub(
8700      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8701    VIXL_ASSERT(allow_macro_instructions_);
8702    VIXL_ASSERT(OutsideITBlock());
8703    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8704    ITScope it_scope(this, &cond);
8705    vsub(cond, dt, rd, rn, rm);
8706  }
8707  void Vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8708    Vsub(al, dt, rd, rn, rm);
8709  }
8710
8711  void Vsubhn(
8712      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
8713    VIXL_ASSERT(allow_macro_instructions_);
8714    VIXL_ASSERT(OutsideITBlock());
8715    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8716    ITScope it_scope(this, &cond);
8717    vsubhn(cond, dt, rd, rn, rm);
8718  }
8719  void Vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
8720    Vsubhn(al, dt, rd, rn, rm);
8721  }
8722
8723  void Vsubl(
8724      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8725    VIXL_ASSERT(allow_macro_instructions_);
8726    VIXL_ASSERT(OutsideITBlock());
8727    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8728    ITScope it_scope(this, &cond);
8729    vsubl(cond, dt, rd, rn, rm);
8730  }
8731  void Vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8732    Vsubl(al, dt, rd, rn, rm);
8733  }
8734
8735  void Vsubw(
8736      Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
8737    VIXL_ASSERT(allow_macro_instructions_);
8738    VIXL_ASSERT(OutsideITBlock());
8739    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8740    ITScope it_scope(this, &cond);
8741    vsubw(cond, dt, rd, rn, rm);
8742  }
8743  void Vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
8744    Vsubw(al, dt, rd, rn, rm);
8745  }
8746
8747  void Vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8748    VIXL_ASSERT(allow_macro_instructions_);
8749    VIXL_ASSERT(OutsideITBlock());
8750    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8751    ITScope it_scope(this, &cond);
8752    vswp(cond, dt, rd, rm);
8753  }
8754  void Vswp(DataType dt, DRegister rd, DRegister rm) { Vswp(al, dt, rd, rm); }
8755  void Vswp(Condition cond, DRegister rd, DRegister rm) {
8756    Vswp(cond, kDataTypeValueNone, rd, rm);
8757  }
8758  void Vswp(DRegister rd, DRegister rm) {
8759    Vswp(al, kDataTypeValueNone, rd, rm);
8760  }
8761
8762  void Vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8763    VIXL_ASSERT(allow_macro_instructions_);
8764    VIXL_ASSERT(OutsideITBlock());
8765    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8766    ITScope it_scope(this, &cond);
8767    vswp(cond, dt, rd, rm);
8768  }
8769  void Vswp(DataType dt, QRegister rd, QRegister rm) { Vswp(al, dt, rd, rm); }
8770  void Vswp(Condition cond, QRegister rd, QRegister rm) {
8771    Vswp(cond, kDataTypeValueNone, rd, rm);
8772  }
8773  void Vswp(QRegister rd, QRegister rm) {
8774    Vswp(al, kDataTypeValueNone, rd, rm);
8775  }
8776
8777  void Vtbl(Condition cond,
8778            DataType dt,
8779            DRegister rd,
8780            const NeonRegisterList& nreglist,
8781            DRegister rm) {
8782    VIXL_ASSERT(allow_macro_instructions_);
8783    VIXL_ASSERT(OutsideITBlock());
8784    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8785    ITScope it_scope(this, &cond);
8786    vtbl(cond, dt, rd, nreglist, rm);
8787  }
8788  void Vtbl(DataType dt,
8789            DRegister rd,
8790            const NeonRegisterList& nreglist,
8791            DRegister rm) {
8792    Vtbl(al, dt, rd, nreglist, rm);
8793  }
8794
8795  void Vtbx(Condition cond,
8796            DataType dt,
8797            DRegister rd,
8798            const NeonRegisterList& nreglist,
8799            DRegister rm) {
8800    VIXL_ASSERT(allow_macro_instructions_);
8801    VIXL_ASSERT(OutsideITBlock());
8802    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8803    ITScope it_scope(this, &cond);
8804    vtbx(cond, dt, rd, nreglist, rm);
8805  }
8806  void Vtbx(DataType dt,
8807            DRegister rd,
8808            const NeonRegisterList& nreglist,
8809            DRegister rm) {
8810    Vtbx(al, dt, rd, nreglist, rm);
8811  }
8812
8813  void Vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8814    VIXL_ASSERT(allow_macro_instructions_);
8815    VIXL_ASSERT(OutsideITBlock());
8816    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8817    ITScope it_scope(this, &cond);
8818    vtrn(cond, dt, rd, rm);
8819  }
8820  void Vtrn(DataType dt, DRegister rd, DRegister rm) { Vtrn(al, dt, rd, rm); }
8821
8822  void Vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8823    VIXL_ASSERT(allow_macro_instructions_);
8824    VIXL_ASSERT(OutsideITBlock());
8825    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8826    ITScope it_scope(this, &cond);
8827    vtrn(cond, dt, rd, rm);
8828  }
8829  void Vtrn(DataType dt, QRegister rd, QRegister rm) { Vtrn(al, dt, rd, rm); }
8830
8831  void Vtst(
8832      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8833    VIXL_ASSERT(allow_macro_instructions_);
8834    VIXL_ASSERT(OutsideITBlock());
8835    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8836    ITScope it_scope(this, &cond);
8837    vtst(cond, dt, rd, rn, rm);
8838  }
8839  void Vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8840    Vtst(al, dt, rd, rn, rm);
8841  }
8842
8843  void Vtst(
8844      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8845    VIXL_ASSERT(allow_macro_instructions_);
8846    VIXL_ASSERT(OutsideITBlock());
8847    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8848    ITScope it_scope(this, &cond);
8849    vtst(cond, dt, rd, rn, rm);
8850  }
8851  void Vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8852    Vtst(al, dt, rd, rn, rm);
8853  }
8854
8855  void Vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8856    VIXL_ASSERT(allow_macro_instructions_);
8857    VIXL_ASSERT(OutsideITBlock());
8858    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8859    ITScope it_scope(this, &cond);
8860    vuzp(cond, dt, rd, rm);
8861  }
8862  void Vuzp(DataType dt, DRegister rd, DRegister rm) { Vuzp(al, dt, rd, rm); }
8863
8864  void Vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8865    VIXL_ASSERT(allow_macro_instructions_);
8866    VIXL_ASSERT(OutsideITBlock());
8867    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8868    ITScope it_scope(this, &cond);
8869    vuzp(cond, dt, rd, rm);
8870  }
8871  void Vuzp(DataType dt, QRegister rd, QRegister rm) { Vuzp(al, dt, rd, rm); }
8872
8873  void Vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8874    VIXL_ASSERT(allow_macro_instructions_);
8875    VIXL_ASSERT(OutsideITBlock());
8876    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8877    ITScope it_scope(this, &cond);
8878    vzip(cond, dt, rd, rm);
8879  }
8880  void Vzip(DataType dt, DRegister rd, DRegister rm) { Vzip(al, dt, rd, rm); }
8881
8882  void Vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8883    VIXL_ASSERT(allow_macro_instructions_);
8884    VIXL_ASSERT(OutsideITBlock());
8885    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8886    ITScope it_scope(this, &cond);
8887    vzip(cond, dt, rd, rm);
8888  }
8889  void Vzip(DataType dt, QRegister rd, QRegister rm) { Vzip(al, dt, rd, rm); }
8890
8891  void Yield(Condition cond) {
8892    VIXL_ASSERT(allow_macro_instructions_);
8893    VIXL_ASSERT(OutsideITBlock());
8894    AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes);
8895    ITScope it_scope(this, &cond);
8896    yield(cond);
8897  }
8898  void Yield() { Yield(al); }
8899  void Vabs(Condition cond, VRegister rd, VRegister rm) {
8900    VIXL_ASSERT(rd.IsS() || rd.IsD());
8901    VIXL_ASSERT(rd.GetType() == rm.GetType());
8902    if (rd.IsS()) {
8903      Vabs(cond, F32, rd.S(), rm.S());
8904    } else {
8905      Vabs(cond, F64, rd.D(), rm.D());
8906    }
8907  }
8908  void Vabs(VRegister rd, VRegister rm) { Vabs(al, rd, rm); }
8909  void Vadd(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
8910    VIXL_ASSERT(rd.IsS() || rd.IsD());
8911    VIXL_ASSERT(rd.GetType() == rn.GetType());
8912    VIXL_ASSERT(rd.GetType() == rm.GetType());
8913    if (rd.IsS()) {
8914      Vadd(cond, F32, rd.S(), rn.S(), rm.S());
8915    } else {
8916      Vadd(cond, F64, rd.D(), rn.D(), rm.D());
8917    }
8918  }
8919  void Vadd(VRegister rd, VRegister rn, VRegister rm) { Vadd(al, rd, rn, rm); }
8920  void Vcmp(Condition cond, VRegister rd, VRegister rm) {
8921    VIXL_ASSERT(rd.IsS() || rd.IsD());
8922    VIXL_ASSERT(rd.GetType() == rm.GetType());
8923    if (rd.IsS()) {
8924      Vcmp(cond, F32, rd.S(), rm.S());
8925    } else {
8926      Vcmp(cond, F64, rd.D(), rm.D());
8927    }
8928  }
8929  void Vcmp(VRegister rd, VRegister rm) { Vcmp(al, rd, rm); }
8930  void Vcmpe(Condition cond, VRegister rd, VRegister rm) {
8931    VIXL_ASSERT(rd.IsS() || rd.IsD());
8932    VIXL_ASSERT(rd.GetType() == rm.GetType());
8933    if (rd.IsS()) {
8934      Vcmpe(cond, F32, rd.S(), rm.S());
8935    } else {
8936      Vcmpe(cond, F64, rd.D(), rm.D());
8937    }
8938  }
8939  void Vcmpe(VRegister rd, VRegister rm) { Vcmpe(al, rd, rm); }
8940  void Vdiv(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
8941    VIXL_ASSERT(rd.IsS() || rd.IsD());
8942    VIXL_ASSERT(rd.GetType() == rn.GetType());
8943    VIXL_ASSERT(rd.GetType() == rm.GetType());
8944    if (rd.IsS()) {
8945      Vdiv(cond, F32, rd.S(), rn.S(), rm.S());
8946    } else {
8947      Vdiv(cond, F64, rd.D(), rn.D(), rm.D());
8948    }
8949  }
8950  void Vdiv(VRegister rd, VRegister rn, VRegister rm) { Vdiv(al, rd, rn, rm); }
8951  void Vfma(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
8952    VIXL_ASSERT(rd.IsS() || rd.IsD());
8953    VIXL_ASSERT(rd.GetType() == rn.GetType());
8954    VIXL_ASSERT(rd.GetType() == rm.GetType());
8955    if (rd.IsS()) {
8956      Vfma(cond, F32, rd.S(), rn.S(), rm.S());
8957    } else {
8958      Vfma(cond, F64, rd.D(), rn.D(), rm.D());
8959    }
8960  }
8961  void Vfma(VRegister rd, VRegister rn, VRegister rm) { Vfma(al, rd, rn, rm); }
8962  void Vfms(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
8963    VIXL_ASSERT(rd.IsS() || rd.IsD());
8964    VIXL_ASSERT(rd.GetType() == rn.GetType());
8965    VIXL_ASSERT(rd.GetType() == rm.GetType());
8966    if (rd.IsS()) {
8967      Vfms(cond, F32, rd.S(), rn.S(), rm.S());
8968    } else {
8969      Vfms(cond, F64, rd.D(), rn.D(), rm.D());
8970    }
8971  }
8972  void Vfms(VRegister rd, VRegister rn, VRegister rm) { Vfms(al, rd, rn, rm); }
8973  void Vfnma(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
8974    VIXL_ASSERT(rd.IsS() || rd.IsD());
8975    VIXL_ASSERT(rd.GetType() == rn.GetType());
8976    VIXL_ASSERT(rd.GetType() == rm.GetType());
8977    if (rd.IsS()) {
8978      Vfnma(cond, F32, rd.S(), rn.S(), rm.S());
8979    } else {
8980      Vfnma(cond, F64, rd.D(), rn.D(), rm.D());
8981    }
8982  }
8983  void Vfnma(VRegister rd, VRegister rn, VRegister rm) {
8984    Vfnma(al, rd, rn, rm);
8985  }
8986  void Vfnms(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
8987    VIXL_ASSERT(rd.IsS() || rd.IsD());
8988    VIXL_ASSERT(rd.GetType() == rn.GetType());
8989    VIXL_ASSERT(rd.GetType() == rm.GetType());
8990    if (rd.IsS()) {
8991      Vfnms(cond, F32, rd.S(), rn.S(), rm.S());
8992    } else {
8993      Vfnms(cond, F64, rd.D(), rn.D(), rm.D());
8994    }
8995  }
8996  void Vfnms(VRegister rd, VRegister rn, VRegister rm) {
8997    Vfnms(al, rd, rn, rm);
8998  }
8999  void Vmaxnm(VRegister rd, VRegister rn, VRegister rm) {
9000    VIXL_ASSERT(rd.IsS() || rd.IsD());
9001    VIXL_ASSERT(rd.GetType() == rn.GetType());
9002    VIXL_ASSERT(rd.GetType() == rm.GetType());
9003    if (rd.IsS()) {
9004      Vmaxnm(F32, rd.S(), rn.S(), rm.S());
9005    } else {
9006      Vmaxnm(F64, rd.D(), rn.D(), rm.D());
9007    }
9008  }
9009  void Vminnm(VRegister rd, VRegister rn, VRegister rm) {
9010    VIXL_ASSERT(rd.IsS() || rd.IsD());
9011    VIXL_ASSERT(rd.GetType() == rn.GetType());
9012    VIXL_ASSERT(rd.GetType() == rm.GetType());
9013    if (rd.IsS()) {
9014      Vminnm(F32, rd.S(), rn.S(), rm.S());
9015    } else {
9016      Vminnm(F64, rd.D(), rn.D(), rm.D());
9017    }
9018  }
9019  void Vmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9020    VIXL_ASSERT(rd.IsS() || rd.IsD());
9021    VIXL_ASSERT(rd.GetType() == rn.GetType());
9022    VIXL_ASSERT(rd.GetType() == rm.GetType());
9023    if (rd.IsS()) {
9024      Vmla(cond, F32, rd.S(), rn.S(), rm.S());
9025    } else {
9026      Vmla(cond, F64, rd.D(), rn.D(), rm.D());
9027    }
9028  }
9029  void Vmla(VRegister rd, VRegister rn, VRegister rm) { Vmla(al, rd, rn, rm); }
9030  void Vmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9031    VIXL_ASSERT(rd.IsS() || rd.IsD());
9032    VIXL_ASSERT(rd.GetType() == rn.GetType());
9033    VIXL_ASSERT(rd.GetType() == rm.GetType());
9034    if (rd.IsS()) {
9035      Vmls(cond, F32, rd.S(), rn.S(), rm.S());
9036    } else {
9037      Vmls(cond, F64, rd.D(), rn.D(), rm.D());
9038    }
9039  }
9040  void Vmls(VRegister rd, VRegister rn, VRegister rm) { Vmls(al, rd, rn, rm); }
9041  void Vmov(Condition cond, VRegister rd, VRegister rm) {
9042    VIXL_ASSERT(rd.IsS() || rd.IsD());
9043    VIXL_ASSERT(rd.GetType() == rm.GetType());
9044    if (rd.IsS()) {
9045      Vmov(cond, F32, rd.S(), rm.S());
9046    } else {
9047      Vmov(cond, F64, rd.D(), rm.D());
9048    }
9049  }
9050  void Vmov(VRegister rd, VRegister rm) { Vmov(al, rd, rm); }
9051  void Vmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9052    VIXL_ASSERT(rd.IsS() || rd.IsD());
9053    VIXL_ASSERT(rd.GetType() == rn.GetType());
9054    VIXL_ASSERT(rd.GetType() == rm.GetType());
9055    if (rd.IsS()) {
9056      Vmul(cond, F32, rd.S(), rn.S(), rm.S());
9057    } else {
9058      Vmul(cond, F64, rd.D(), rn.D(), rm.D());
9059    }
9060  }
9061  void Vmul(VRegister rd, VRegister rn, VRegister rm) { Vmul(al, rd, rn, rm); }
9062  void Vneg(Condition cond, VRegister rd, VRegister rm) {
9063    VIXL_ASSERT(rd.IsS() || rd.IsD());
9064    VIXL_ASSERT(rd.GetType() == rm.GetType());
9065    if (rd.IsS()) {
9066      Vneg(cond, F32, rd.S(), rm.S());
9067    } else {
9068      Vneg(cond, F64, rd.D(), rm.D());
9069    }
9070  }
9071  void Vneg(VRegister rd, VRegister rm) { Vneg(al, rd, rm); }
9072  void Vnmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9073    VIXL_ASSERT(rd.IsS() || rd.IsD());
9074    VIXL_ASSERT(rd.GetType() == rn.GetType());
9075    VIXL_ASSERT(rd.GetType() == rm.GetType());
9076    if (rd.IsS()) {
9077      Vnmla(cond, F32, rd.S(), rn.S(), rm.S());
9078    } else {
9079      Vnmla(cond, F64, rd.D(), rn.D(), rm.D());
9080    }
9081  }
9082  void Vnmla(VRegister rd, VRegister rn, VRegister rm) {
9083    Vnmla(al, rd, rn, rm);
9084  }
9085  void Vnmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9086    VIXL_ASSERT(rd.IsS() || rd.IsD());
9087    VIXL_ASSERT(rd.GetType() == rn.GetType());
9088    VIXL_ASSERT(rd.GetType() == rm.GetType());
9089    if (rd.IsS()) {
9090      Vnmls(cond, F32, rd.S(), rn.S(), rm.S());
9091    } else {
9092      Vnmls(cond, F64, rd.D(), rn.D(), rm.D());
9093    }
9094  }
9095  void Vnmls(VRegister rd, VRegister rn, VRegister rm) {
9096    Vnmls(al, rd, rn, rm);
9097  }
9098  void Vnmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9099    VIXL_ASSERT(rd.IsS() || rd.IsD());
9100    VIXL_ASSERT(rd.GetType() == rn.GetType());
9101    VIXL_ASSERT(rd.GetType() == rm.GetType());
9102    if (rd.IsS()) {
9103      Vnmul(cond, F32, rd.S(), rn.S(), rm.S());
9104    } else {
9105      Vnmul(cond, F64, rd.D(), rn.D(), rm.D());
9106    }
9107  }
9108  void Vnmul(VRegister rd, VRegister rn, VRegister rm) {
9109    Vnmul(al, rd, rn, rm);
9110  }
9111  void Vseleq(VRegister rd, VRegister rn, VRegister rm) {
9112    VIXL_ASSERT(rd.IsS() || rd.IsD());
9113    VIXL_ASSERT(rd.GetType() == rn.GetType());
9114    VIXL_ASSERT(rd.GetType() == rm.GetType());
9115    if (rd.IsS()) {
9116      Vseleq(F32, rd.S(), rn.S(), rm.S());
9117    } else {
9118      Vseleq(F64, rd.D(), rn.D(), rm.D());
9119    }
9120  }
9121  void Vselge(VRegister rd, VRegister rn, VRegister rm) {
9122    VIXL_ASSERT(rd.IsS() || rd.IsD());
9123    VIXL_ASSERT(rd.GetType() == rn.GetType());
9124    VIXL_ASSERT(rd.GetType() == rm.GetType());
9125    if (rd.IsS()) {
9126      Vselge(F32, rd.S(), rn.S(), rm.S());
9127    } else {
9128      Vselge(F64, rd.D(), rn.D(), rm.D());
9129    }
9130  }
9131  void Vselgt(VRegister rd, VRegister rn, VRegister rm) {
9132    VIXL_ASSERT(rd.IsS() || rd.IsD());
9133    VIXL_ASSERT(rd.GetType() == rn.GetType());
9134    VIXL_ASSERT(rd.GetType() == rm.GetType());
9135    if (rd.IsS()) {
9136      Vselgt(F32, rd.S(), rn.S(), rm.S());
9137    } else {
9138      Vselgt(F64, rd.D(), rn.D(), rm.D());
9139    }
9140  }
9141  void Vselvs(VRegister rd, VRegister rn, VRegister rm) {
9142    VIXL_ASSERT(rd.IsS() || rd.IsD());
9143    VIXL_ASSERT(rd.GetType() == rn.GetType());
9144    VIXL_ASSERT(rd.GetType() == rm.GetType());
9145    if (rd.IsS()) {
9146      Vselvs(F32, rd.S(), rn.S(), rm.S());
9147    } else {
9148      Vselvs(F64, rd.D(), rn.D(), rm.D());
9149    }
9150  }
9151  void Vsqrt(Condition cond, VRegister rd, VRegister rm) {
9152    VIXL_ASSERT(rd.IsS() || rd.IsD());
9153    VIXL_ASSERT(rd.GetType() == rm.GetType());
9154    if (rd.IsS()) {
9155      Vsqrt(cond, F32, rd.S(), rm.S());
9156    } else {
9157      Vsqrt(cond, F64, rd.D(), rm.D());
9158    }
9159  }
9160  void Vsqrt(VRegister rd, VRegister rm) { Vsqrt(al, rd, rm); }
9161  void Vsub(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
9162    VIXL_ASSERT(rd.IsS() || rd.IsD());
9163    VIXL_ASSERT(rd.GetType() == rn.GetType());
9164    VIXL_ASSERT(rd.GetType() == rm.GetType());
9165    if (rd.IsS()) {
9166      Vsub(cond, F32, rd.S(), rn.S(), rm.S());
9167    } else {
9168      Vsub(cond, F64, rd.D(), rn.D(), rm.D());
9169    }
9170  }
9171  void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); }
9172  // End of generated code.
9173 private:
9174  RegisterList available_;
9175  VRegisterList available_vfp_;
9176  MacroAssemblerContext context_;
9177  Label::Offset checkpoint_;
9178  LiteralPoolManager literal_pool_manager_;
9179  VeneerPoolManager veneer_pool_manager_;
9180  bool generate_simulator_code_;
9181  bool allow_macro_instructions_;
9182};
9183
9184// This scope is used to ensure that the specified size of instructions will be
9185// emitted contiguously. The assert policy kExtactSize should only be used
9186// when you use directly the assembler as it's difficult to know exactly how
9187// many instructions will be emitted by the macro-assembler. Using the assembler
9188// means that you directly use the assembler instructions (in lower case) from a
9189// MacroAssembler object.
9190class CodeBufferCheckScope {
9191 public:
9192  // Tell whether or not the scope should assert the amount of code emitted
9193  // within the scope is consistent with the requested amount.
9194  enum AssertPolicy {
9195    kNoAssert,    // No assert required.
9196    kExactSize,   // The code emitted must be exactly size bytes.
9197    kMaximumSize  // The code emitted must be at most size bytes.
9198  };
9199
9200  CodeBufferCheckScope(MacroAssembler* masm,
9201                       uint32_t size,
9202                       AssertPolicy assert_policy = kMaximumSize)
9203      : masm_(masm) {
9204    masm->EnsureEmitFor(size);
9205#ifdef VIXL_DEBUG
9206    initial_cursor_offset_ = masm->GetCursorOffset();
9207    size_ = size;
9208    assert_policy_ = assert_policy;
9209#else
9210    USE(assert_policy);
9211#endif
9212  }
9213
9214  ~CodeBufferCheckScope() {
9215#ifdef VIXL_DEBUG
9216    switch (assert_policy_) {
9217      case kNoAssert:
9218        break;
9219      case kExactSize:
9220        VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ == size_);
9221        break;
9222      case kMaximumSize:
9223        VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <= size_);
9224        break;
9225      default:
9226        VIXL_UNREACHABLE();
9227    }
9228#endif
9229  }
9230
9231 protected:
9232  MacroAssembler* masm_;
9233  uint32_t initial_cursor_offset_;
9234  uint32_t size_;
9235  AssertPolicy assert_policy_;
9236};
9237
9238// Use this scope when you need a one-to-one mapping between methods and
9239// instructions. This scope prevents the MacroAssembler functions from being
9240// called and the literal pools and veneers from being emitted (they can only be
9241// emitted when you create the scope). It also asserts the size of the emitted
9242// instructions is the specified size (or not greater than the specified size).
9243// This scope must be used when you want to directly use the assembler. It will
9244// ensure that the buffer is big enough and that you don't break the pool and
9245// veneer mechanisms.
9246class AssemblerAccurateScope : public CodeBufferCheckScope {
9247 public:
9248  AssemblerAccurateScope(MacroAssembler* masm,
9249                         uint32_t size,
9250                         AssertPolicy policy = kExactSize)
9251      : CodeBufferCheckScope(masm, size, policy) {
9252    VIXL_ASSERT(policy != kNoAssert);
9253#ifdef VIXL_DEBUG
9254    old_allow_macro_instructions_ = masm->AllowMacroInstructions();
9255    old_allow_assembler_ = masm->AllowAssembler();
9256    masm->SetAllowMacroInstructions(false);
9257    masm->SetAllowAssembler(true);
9258#else
9259    USE(old_allow_macro_instructions_);
9260    USE(old_allow_assembler_);
9261#endif
9262  }
9263
9264  ~AssemblerAccurateScope() {
9265#ifdef VIXL_DEBUG
9266    masm_->SetAllowMacroInstructions(old_allow_macro_instructions_);
9267    masm_->SetAllowAssembler(old_allow_assembler_);
9268#endif
9269  }
9270
9271 private:
9272  bool old_allow_macro_instructions_;
9273  bool old_allow_assembler_;
9274};
9275
9276// This scope utility allows scratch registers to be managed safely. The
9277// MacroAssembler's GetScratchRegisterList() is used as a pool of scratch
9278// registers. These registers can be allocated on demand, and will be returned
9279// at the end of the scope.
9280//
9281// When the scope ends, the MacroAssembler's lists will be restored to their
9282// original state, even if the lists were modified by some other means.
9283class UseScratchRegisterScope {
9284 public:
9285  // This constructor implicitly calls the `Open` function to initialise the
9286  // scope, so it is ready to use immediately after it has been constructed.
9287  explicit UseScratchRegisterScope(MacroAssembler* masm)
9288      : available_(NULL),
9289        available_vfp_(NULL),
9290        old_available_(0),
9291        old_available_vfp_(0) {
9292    Open(masm);
9293  }
9294  // This constructor allows deferred and optional initialisation of the scope.
9295  // The user is required to explicitly call the `Open` function before using
9296  // the scope.
9297  UseScratchRegisterScope()
9298      : available_(NULL),
9299        available_vfp_(NULL),
9300        old_available_(0),
9301        old_available_vfp_(0) {}
9302
9303  // This function performs the actual initialisation work.
9304  void Open(MacroAssembler* masm);
9305
9306  // The destructor always implicitly calls the `Close` function.
9307  ~UseScratchRegisterScope() { Close(); }
9308
9309  // This function performs the cleaning-up work. It must succeed even if the
9310  // scope has not been opened. It is safe to call multiple times.
9311  void Close();
9312
9313  bool IsAvailable(const Register& reg) const;
9314  bool IsAvailable(const VRegister& reg) const;
9315
9316  // Take a register from the temp list. It will be returned automatically when
9317  // the scope ends.
9318  Register Acquire();
9319  VRegister AcquireV(unsigned size_in_bits);
9320  QRegister AcquireQ();
9321  DRegister AcquireD();
9322  SRegister AcquireS();
9323
9324  // Explicitly release an acquired (or excluded) register, putting it back in
9325  // the temp list.
9326  void Release(const Register& reg);
9327  void Release(const VRegister& reg);
9328
9329  // Make the specified registers available as scratch registers for the
9330  // duration of this scope.
9331  void Include(const RegisterList& list);
9332  void Include(const Register& reg1,
9333               const Register& reg2 = NoReg,
9334               const Register& reg3 = NoReg,
9335               const Register& reg4 = NoReg) {
9336    Include(RegisterList(reg1, reg2, reg3, reg4));
9337  }
9338  void Include(const VRegisterList& list);
9339  void Include(const VRegister& reg1,
9340               const VRegister& reg2 = NoVReg,
9341               const VRegister& reg3 = NoVReg,
9342               const VRegister& reg4 = NoVReg) {
9343    Include(VRegisterList(reg1, reg2, reg3, reg4));
9344  }
9345
9346  // Make sure that the specified registers are not available in this scope.
9347  // This can be used to prevent helper functions from using sensitive
9348  // registers, for example.
9349  void Exclude(const RegisterList& list);
9350  void Exclude(const Register& reg1,
9351               const Register& reg2 = NoReg,
9352               const Register& reg3 = NoReg,
9353               const Register& reg4 = NoReg) {
9354    Exclude(RegisterList(reg1, reg2, reg3, reg4));
9355  }
9356  void Exclude(const VRegisterList& list);
9357  void Exclude(const VRegister& reg1,
9358               const VRegister& reg2 = NoVReg,
9359               const VRegister& reg3 = NoVReg,
9360               const VRegister& reg4 = NoVReg) {
9361    Exclude(VRegisterList(reg1, reg2, reg3, reg4));
9362  }
9363
9364  // Prevent any scratch registers from being used in this scope.
9365  void ExcludeAll();
9366
9367 private:
9368  // Available scratch registers.
9369  RegisterList* available_;       // kRRegister
9370  VRegisterList* available_vfp_;  // kVRegister
9371
9372  // The state of the available lists at the start of this scope.
9373  uint32_t old_available_;      // kRRegister
9374  uint64_t old_available_vfp_;  // kVRegister
9375
9376  VIXL_DEBUG_NO_RETURN UseScratchRegisterScope(const UseScratchRegisterScope&) {
9377    VIXL_UNREACHABLE();
9378  }
9379  VIXL_DEBUG_NO_RETURN void operator=(const UseScratchRegisterScope&) {
9380    VIXL_UNREACHABLE();
9381  }
9382};
9383
9384class JumpTableBase {
9385 protected:
9386  JumpTableBase(int len, int offset_size)
9387      : table_location_(Label::kMaxOffset),
9388        branch_location_(Label::kMaxOffset),
9389        length_(len),
9390        offset_shift_(WhichPowerOf2(offset_size)),
9391        presence_(length_) {
9392    VIXL_ASSERT((length_ >= 0) && (offset_size <= 4));
9393  }
9394  virtual ~JumpTableBase() {}
9395
9396 public:
9397  int GetTableSizeInBytes() const { return length_ * (1 << offset_shift_); }
9398  int GetOffsetShift() const { return offset_shift_; }
9399  int GetLength() const { return length_; }
9400  Label* GetDefaultLabel() { return &default_; }
9401  Label* GetEndLabel() { return &end_; }
9402  void SetBranchLocation(uint32_t branch_location) {
9403    branch_location_ = branch_location;
9404  }
9405  uint32_t GetBranchLocation() const { return branch_location_; }
9406  void BindTable(uint32_t location) { table_location_ = location; }
9407  virtual void Link(MacroAssembler* masm,
9408                    int case_index,
9409                    uint32_t location) = 0;
9410
9411  uint32_t GetLocationForCase(int i) {
9412    VIXL_ASSERT((i >= 0) && (i < length_));
9413    return table_location_ + (i * (1 << offset_shift_));
9414  }
9415  void SetPresenceBitForCase(int i) {
9416    VIXL_ASSERT((i >= 0) && (i < length_));
9417    presence_.Set(i);
9418  }
9419
9420  void Finalize(MacroAssembler* masm) {
9421    if (!default_.IsBound()) {
9422      masm->Bind(&default_);
9423    }
9424    masm->Bind(&end_);
9425
9426    presence_.ForEachBitNotSet(LinkIt(this, masm, default_.GetLocation()));
9427  }
9428
9429 private:
9430  uint32_t table_location_;
9431  uint32_t branch_location_;
9432  const int length_;
9433  const int offset_shift_;
9434  BitField presence_;
9435  Label default_;
9436  Label end_;
9437  struct LinkIt {
9438    JumpTableBase* table_;
9439    MacroAssembler* const masm_;
9440    const uint32_t location_;
9441    LinkIt(JumpTableBase* table, MacroAssembler* const masm, uint32_t location)
9442        : table_(table), masm_(masm), location_(location) {}
9443    bool execute(int id) const {
9444      VIXL_ASSERT(id < table_->GetLength());
9445      table_->Link(masm_, static_cast<int>(id), location_);
9446      return true;
9447    }
9448  };
9449};
9450
9451// JumpTable<T>(len): Helper to describe a jump table
9452// len here describes the number of possible case. Values in [0, n[ can have a
9453// jump offset. Any other value will assert.
9454template <typename T>
9455class JumpTable : public JumpTableBase {
9456 protected:
9457  explicit JumpTable(int length) : JumpTableBase(length, sizeof(T)) {}
9458
9459 public:
9460  virtual void Link(MacroAssembler* masm,
9461                    int case_index,
9462                    uint32_t location) VIXL_OVERRIDE {
9463    uint32_t position_in_table = GetLocationForCase(case_index);
9464    uint32_t from = GetBranchLocation();
9465    int offset = location - from;
9466    T* case_offset = masm->GetBuffer()->GetOffsetAddress<T*>(position_in_table);
9467    if (masm->IsUsingT32()) {
9468      *case_offset = offset >> 1;
9469    } else {
9470      *case_offset = offset >> 2;
9471    }
9472  }
9473};
9474
9475class JumpTable8bitOffset : public JumpTable<uint8_t> {
9476 public:
9477  explicit JumpTable8bitOffset(int length) : JumpTable<uint8_t>(length) {}
9478};
9479
9480class JumpTable16bitOffset : public JumpTable<uint16_t> {
9481 public:
9482  explicit JumpTable16bitOffset(int length) : JumpTable<uint16_t>(length) {}
9483};
9484
9485class JumpTable32bitOffset : public JumpTable<uint32_t> {
9486 public:
9487  explicit JumpTable32bitOffset(int length) : JumpTable<uint32_t>(length) {}
9488};
9489
9490}  // namespace aarch32
9491}  // namespace vixl
9492
9493#endif  // VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_
9494