macro-assembler-aarch32.h revision f678618ae35a43dab65455f446c3de324994c204
1// Copyright 2015, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright 10// notice, this list of conditions and the following disclaimer in the 11// documentation and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may 13// be used to endorse or promote products derived from this software 14// without specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26// POSSIBILITY OF SUCH DAMAGE. 27 28#ifndef VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 29#define VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 30 31#include "utils-vixl.h" 32#include "aarch32/instructions-aarch32.h" 33#include "aarch32/assembler-aarch32.h" 34#include "aarch32/operand-aarch32.h" 35 36namespace vixl { 37namespace aarch32 { 38 39class JumpTableBase; 40 41enum FlagsUpdate { LeaveFlags = 0, SetFlags = 1, DontCare = 2 }; 42 43// LiteralPool class, defined as a container for literals 44class LiteralPool { 45 public: 46 typedef std::list<RawLiteral*>::iterator RawLiteralListIterator; 47 48 public: 49 LiteralPool() : size_(0) {} 50 ~LiteralPool() { 51 VIXL_ASSERT(literals_.empty() && (size_ == 0)); 52 for (RawLiteralListIterator literal_it = keep_until_delete_.begin(); 53 literal_it != keep_until_delete_.end(); 54 literal_it++) { 55 delete *literal_it; 56 } 57 keep_until_delete_.clear(); 58 } 59 60 unsigned GetSize() const { return size_; } 61 62 // Add a literal to the literal container. 63 uint32_t AddLiteral(RawLiteral* literal) { 64 uint32_t position = GetSize(); 65 literal->SetPositionInPool(position); 66 literals_.push_back(literal); 67 size_ += literal->GetAlignedSize(); 68 return position; 69 } 70 71 // First literal to be emitted. 72 RawLiteralListIterator GetFirst() { return literals_.begin(); } 73 74 // Mark the end of the literal container. 75 RawLiteralListIterator GetEnd() { return literals_.end(); } 76 77 // Remove all the literals from the container. 78 // If the literal's memory management has been delegated to the container 79 // it will be delete'd. 80 void Clear() { 81 for (RawLiteralListIterator literal_it = GetFirst(); literal_it != GetEnd(); 82 literal_it++) { 83 RawLiteral* literal = *literal_it; 84 switch (literal->GetDeletionPolicy()) { 85 case RawLiteral::kDeletedOnPlacementByPool: 86 delete literal; 87 break; 88 case RawLiteral::kDeletedOnPoolDestruction: 89 keep_until_delete_.push_back(literal); 90 break; 91 case RawLiteral::kManuallyDeleted: 92 break; 93 } 94 } 95 literals_.clear(); 96 size_ = 0; 97 } 98 99 private: 100 // Size (in bytes and including alignments) of the literal pool. 101 unsigned size_; 102 103 // Literal container. 104 std::list<RawLiteral*> literals_; 105 // Already bound Literal container the app requested this pool to keep. 106 std::list<RawLiteral*> keep_until_delete_; 107}; 108 109// Macro assembler for aarch32 instruction set. 110class MacroAssembler : public Assembler { 111 public: 112 enum EmitOption { kBranchRequired, kNoBranchRequired }; 113 114 private: 115 class AllowAssemblerEmissionScope { 116 MacroAssembler* masm_; 117 118 public: 119 AllowAssemblerEmissionScope(MacroAssembler* masm, uint32_t size) 120 : masm_(masm) { 121 VIXL_ASSERT(!masm->AllowAssembler()); 122 masm->EnsureEmitFor(size); 123#ifdef VIXL_DEBUG 124 masm->SetAllowAssembler(true); 125#else 126 USE(masm_); 127#endif 128 } 129 ~AllowAssemblerEmissionScope() { 130#ifdef VIXL_DEBUG 131 VIXL_ASSERT(masm_->AllowAssembler()); 132 masm_->SetAllowAssembler(false); 133#endif 134 } 135 }; 136 137 class MacroAssemblerContext { 138 public: 139 MacroAssemblerContext() : count_(0) {} 140 ~MacroAssemblerContext() {} 141 unsigned GetRecursiveCount() const { return count_; } 142 void Up() { 143 count_++; 144 VIXL_CHECK(count_ < kMaxRecursion); 145 } 146 void Down() { 147 VIXL_ASSERT((count_ > 0) && (count_ < kMaxRecursion)); 148 count_--; 149 } 150 151 private: 152 unsigned count_; 153 static const uint32_t kMaxRecursion = 5; 154 }; 155 156 class ContextScope { 157 public: 158 explicit ContextScope(MacroAssembler* const masm) : masm_(masm) { 159 VIXL_ASSERT(masm_->AllowMacroInstructions()); 160 masm_->GetContext()->Up(); 161 } 162 ~ContextScope() { masm_->GetContext()->Down(); } 163 164 private: 165 MacroAssembler* const masm_; 166 }; 167 168 MacroAssemblerContext* GetContext() { return &context_; } 169 170 class ITScope { 171 public: 172 ITScope(MacroAssembler* masm, Condition* cond, bool can_use_it = false) 173 : masm_(masm), cond_(*cond), can_use_it_(can_use_it) { 174 if (!cond_.Is(al) && masm->IsUsingT32()) { 175 if (can_use_it_) { 176 // IT is not deprecated (that implies a 16 bit T32 instruction). 177 // We generate an IT instruction and a conditional instruction. 178 masm->it(cond_); 179 } else { 180 // The usage of IT is deprecated for the instruction. 181 // We generate a conditional branch and an unconditional instruction. 182 masm_->EnsureEmitFor(k16BitT32InstructionSizeInBytes + 183 kMaxT32MacroInstructionSizeInBytes); 184 // Generate the branch. 185 masm_->b(cond_.Negate(), Narrow, &label_); 186 // Tell the macro-assembler to generate unconditional instructions. 187 *cond = al; 188 } 189 } 190#ifdef VIXL_DEBUG 191 initial_cursor_offset_ = masm->GetCursorOffset(); 192#else 193 USE(initial_cursor_offset_); 194#endif 195 } 196 ~ITScope() { 197 if (!cond_.Is(al) && masm_->IsUsingT32() && !can_use_it_) { 198 VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <= 199 kMaxT32MacroInstructionSizeInBytes); 200 masm_->bind(&label_); 201 } 202 } 203 204 private: 205 MacroAssembler* masm_; 206 Condition cond_; 207 Label label_; 208 bool can_use_it_; 209 uint32_t initial_cursor_offset_; 210 }; 211 212 template <Assembler::InstructionCondDtDL asmfn> 213 class EmitLiteralCondDtDL { 214 public: 215 EmitLiteralCondDtDL(Condition cond, DataType dt, DRegister rt) 216 : cond_(cond), dt_(dt), rt_(rt) {} 217 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 218 (masm->*asmfn)(cond_, dt_, rt_, literal); 219 } 220 221 private: 222 Condition cond_; 223 DataType dt_; 224 DRegister rt_; 225 }; 226 227 template <Assembler::InstructionCondDtSL asmfn> 228 class EmitLiteralCondDtSL { 229 public: 230 EmitLiteralCondDtSL(Condition cond, DataType dt, SRegister rt) 231 : cond_(cond), dt_(dt), rt_(rt) {} 232 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 233 (masm->*asmfn)(cond_, dt_, rt_, literal); 234 } 235 236 private: 237 Condition cond_; 238 DataType dt_; 239 SRegister rt_; 240 }; 241 242 template <Assembler::InstructionCondRL asmfn> 243 class EmitLiteralCondRL { 244 public: 245 EmitLiteralCondRL(Condition cond, Register rt) : cond_(cond), rt_(rt) {} 246 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 247 (masm->*asmfn)(cond_, rt_, literal); 248 } 249 250 private: 251 Condition cond_; 252 Register rt_; 253 }; 254 255 template <Assembler::InstructionCondRRL asmfn> 256 class EmitLiteralCondRRL { 257 public: 258 EmitLiteralCondRRL(Condition cond, Register rt, Register rt2) 259 : cond_(cond), rt_(rt), rt2_(rt2) {} 260 void emit(MacroAssembler* const masm, RawLiteral* const literal) { 261 (masm->*asmfn)(cond_, rt_, rt2_, literal); 262 } 263 264 private: 265 Condition cond_; 266 Register rt_, rt2_; 267 }; 268 269 class LiteralPoolManager { 270 public: 271 explicit LiteralPoolManager(MacroAssembler* const masm) : masm_(masm) { 272 ResetCheckpoint(); 273 } 274 275 void ResetCheckpoint() { checkpoint_ = Label::kMaxOffset; } 276 277 LiteralPool* GetLiteralPool() { return &literal_pool_; } 278 Label::Offset GetCheckpoint() const { 279 // Make room for a branch over the pools. 280 return checkpoint_ - kMaxInstructionSizeInBytes; 281 } 282 size_t GetLiteralPoolSize() const { return literal_pool_.GetSize(); } 283 284 // Checks if the insertion of the literal will put the forward reference 285 // too far in the literal pool. 286 bool IsInsertTooFar(RawLiteral* literal, uint32_t from) const { 287 uint32_t checkpoint = from + literal->GetLastInsertForwardDistance(); 288 checkpoint = 289 std::min(checkpoint, static_cast<uint32_t>(literal->GetCheckpoint())); 290 bool too_far = AlignDown(checkpoint, 4) < from + literal_pool_.GetSize() + 291 kMaxInstructionSizeInBytes; 292 return too_far; 293 } 294 295 // Set the different checkpoints where the literal pool has to be emited. 296 void UpdateCheckpoint(RawLiteral* literal) { 297 // The literal should have been placed somewhere in the literal pool 298 VIXL_ASSERT(literal->GetPositionInPool() != Label::kMaxOffset); 299 // TODO(all): Consider AddForwardRef as a virtual so the checkpoint is 300 // updated when inserted. Or move checkpoint_ into Label, 301 literal->UpdateCheckpoint(); 302 Label::Offset tmp = 303 literal->GetAlignedCheckpoint(4) - literal->GetPositionInPool(); 304 if (checkpoint_ > tmp) { 305 checkpoint_ = tmp; 306 masm_->ComputeCheckpoint(); 307 } 308 } 309 310 // Inserts the literal in the pool, and update the different checkpoints. 311 void AddLiteral(RawLiteral* literal) { literal_pool_.AddLiteral(literal); } 312 313 private: 314 MacroAssembler* const masm_; 315 LiteralPool literal_pool_; 316 317 // Max offset in the code buffer where the literal needs to be 318 // emitted. A default value of Label::kMaxOffset means that the checkpoint 319 // is invalid. 320 Label::Offset checkpoint_; 321 }; 322 323 class VeneerPoolManager { 324 public: 325 explicit VeneerPoolManager(MacroAssembler* masm) 326 : masm_(masm), checkpoint_(Label::kMaxOffset) {} 327 Label::Offset GetCheckpoint() const { 328 // Make room for a branch over the pools. 329 return checkpoint_ - kMaxInstructionSizeInBytes; 330 } 331 size_t GetMaxSize() const { 332 return labels_.size() * kMaxInstructionSizeInBytes; 333 } 334 void AddLabel(Label* label) { 335 if (!label->IsInVeneerPool()) { 336 label->SetInVeneerPool(); 337 labels_.push_back(label); 338 } 339 Label::ForwardReference& back = label->GetBackForwardRef(); 340 back.SetIsBranch(); 341 label->UpdateCheckpoint(); 342 Label::Offset tmp = label->GetCheckpoint(); 343 if (checkpoint_ > tmp) { 344 checkpoint_ = tmp; 345 masm_->ComputeCheckpoint(); 346 } 347 } 348 void RemoveLabel(Label* label); 349 void Emit(Label::Offset target); 350 351 private: 352 MacroAssembler* masm_; 353 // List of all unbound labels which are used by a branch instruction. 354 std::list<Label*> labels_; 355 // Max offset in the code buffer where the veneer needs to be emitted. 356 // A default value of Label::kMaxOffset means that the checkpoint is 357 // invalid. 358 Label::Offset checkpoint_; 359 }; 360 361 void PerformEnsureEmit(Label::Offset target, uint32_t extra_size); 362 363 protected: 364 void HandleOutOfBoundsImmediate(Condition cond, Register tmp, uint32_t imm); 365 366 // Generate the instruction and if it's not possible revert the whole thing. 367 // emit the literal pool and regenerate the instruction. 368 // Note: The instruction is generated via 369 // void T::emit(MacroAssembler* const, RawLiteral* const) 370 template <typename T> 371 void GenerateInstruction(T instr_callback, RawLiteral* const literal) { 372 ptrdiff_t cursor = GetBuffer().GetCursorOffset(); 373 uint32_t where = cursor + GetArchitectureStatePCOffset(); 374 // Emit the instruction, via the assembler 375 { 376 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 377 instr_callback.emit(this, literal); 378 } 379 if (IsInsertTooFar(literal, where)) { 380 // The instruction's data is too far: revert the emission 381 GetBuffer().Rewind(cursor); 382 literal->InvalidateLastForwardReference(RawLiteral::kNoUpdateNecessary); 383 EmitLiteralPool(kBranchRequired); 384 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 385 instr_callback.emit(this, literal); 386 } 387 if (literal->GetPositionInPool() == Label::kMaxOffset) { 388 literal_pool_manager_.AddLiteral(literal); 389 } 390 literal_pool_manager_.UpdateCheckpoint(literal); 391 } 392 393 public: 394 explicit MacroAssembler(InstructionSet isa = A32) 395 : Assembler(isa), 396 available_(r12), 397 checkpoint_(Label::kMaxOffset), 398 literal_pool_manager_(this), 399 veneer_pool_manager_(this), 400 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) { 401 SetAllowAssembler(false); 402#ifdef VIXL_DEBUG 403 SetAllowMacroInstructions(true); 404#else 405 USE(literal_pool_manager_); 406 USE(allow_macro_instructions_); 407#endif 408 ComputeCheckpoint(); 409 } 410 explicit MacroAssembler(size_t size, InstructionSet isa = A32) 411 : Assembler(size, isa), 412 available_(r12), 413 checkpoint_(Label::kMaxOffset), 414 literal_pool_manager_(this), 415 veneer_pool_manager_(this), 416 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) { 417 SetAllowAssembler(false); 418#ifdef VIXL_DEBUG 419 SetAllowMacroInstructions(true); 420#endif 421 ComputeCheckpoint(); 422 } 423 MacroAssembler(void* buffer, size_t size, InstructionSet isa = A32) 424 : Assembler(buffer, size, isa), 425 available_(r12), 426 checkpoint_(Label::kMaxOffset), 427 literal_pool_manager_(this), 428 veneer_pool_manager_(this), 429 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) { 430 SetAllowAssembler(false); 431#ifdef VIXL_DEBUG 432 SetAllowMacroInstructions(true); 433#endif 434 ComputeCheckpoint(); 435 } 436 437 bool GenerateSimulatorCode() const { return generate_simulator_code_; } 438 439#ifdef VIXL_DEBUG 440 // Tell whether any of the macro instruction can be used. When false the 441 // MacroAssembler will assert if a method which can emit a variable number 442 // of instructions is called. 443 void SetAllowMacroInstructions(bool value) { 444 allow_macro_instructions_ = value; 445 } 446 bool AllowMacroInstructions() const { return allow_macro_instructions_; } 447#endif 448 449 void FinalizeCode() { 450 EmitLiteralPool(kNoBranchRequired); 451 Assembler::FinalizeCode(); 452 } 453 454 RegisterList* GetScratchRegisterList() { return &available_; } 455 VRegisterList* GetScratchVRegisterList() { return &available_vfp_; } 456 457 // State and type helpers. 458 bool IsModifiedImmediate(uint32_t imm) { 459 return (IsUsingT32() && ImmediateT32(imm).IsValid()) || 460 ImmediateA32(imm).IsValid(); 461 } 462 463 void Bind(Label* label) { 464 VIXL_ASSERT(allow_macro_instructions_); 465 bind(label); 466 if (label->IsInVeneerPool()) veneer_pool_manager_.RemoveLabel(label); 467 } 468 469 void AddBranchLabel(Label* label) { 470 if (label->IsBound()) return; 471 veneer_pool_manager_.AddLabel(label); 472 } 473 474 void Place(RawLiteral* literal) { 475 VIXL_ASSERT(allow_macro_instructions_); 476 EnsureEmitFor(literal->GetSize()); 477 place(literal); 478 } 479 480 void ComputeCheckpoint(); 481 482 void EnsureEmitFor(uint32_t size) { 483 Label::Offset target = AlignUp(GetCursorOffset() + size, 4); 484 if (target < checkpoint_) return; 485 PerformEnsureEmit(target, size); 486 } 487 488 bool IsInsertTooFar(RawLiteral* literal, uint32_t where) { 489 return literal_pool_manager_.IsInsertTooFar(literal, where); 490 } 491 492 // Emit the literal pool in the code buffer. 493 // Every literal is placed on a 32bit boundary 494 // All the literals in the pool will be removed from the pool and potentially 495 // delete'd. 496 void EmitLiteralPool(LiteralPool* const literal_pool, EmitOption option) { 497 if (literal_pool->GetSize() > 0) { 498#ifdef VIXL_DEBUG 499 for (LiteralPool::RawLiteralListIterator literal_it = 500 literal_pool->GetFirst(); 501 literal_it != literal_pool->GetEnd(); 502 literal_it++) { 503 RawLiteral* literal = *literal_it; 504 VIXL_ASSERT(GetCursorOffset() < 505 static_cast<uint32_t>(literal->GetCheckpoint())); 506 } 507#endif 508 Label after_literal; 509 if (option == kBranchRequired) { 510 GetBuffer().EnsureSpaceFor(kMaxInstructionSizeInBytes); 511 VIXL_ASSERT(!AllowAssembler()); 512#ifdef VIXL_DEBUG 513 SetAllowAssembler(true); 514#endif 515 b(&after_literal); 516 VIXL_ASSERT(AllowAssembler()); 517#ifdef VIXL_DEBUG 518 SetAllowAssembler(false); 519#endif 520 } 521 GetBuffer().Align(); 522 GetBuffer().EnsureSpaceFor(literal_pool->GetSize()); 523 for (LiteralPool::RawLiteralListIterator it = literal_pool->GetFirst(); 524 it != literal_pool->GetEnd(); 525 it++) { 526 place(*it); 527 } 528 if (option == kBranchRequired) bind(&after_literal); 529 literal_pool->Clear(); 530 } 531 } 532 void EmitLiteralPool(EmitOption option = kBranchRequired) { 533 EmitLiteralPool(literal_pool_manager_.GetLiteralPool(), option); 534 literal_pool_manager_.ResetCheckpoint(); 535 ComputeCheckpoint(); 536 } 537 538 unsigned GetLiteralPoolSize() const { 539 return literal_pool_manager_.GetLiteralPoolSize(); 540 } 541 542 // Add a Literal to the internal literal pool 543 void AddLiteral(RawLiteral* literal) { 544 return literal_pool_manager_.AddLiteral(literal); 545 } 546 547 // Generic Ldr(register, data) 548 void Ldr(Condition cond, Register rt, uint32_t v) { 549 RawLiteral* literal = 550 new Literal<uint32_t>(v, RawLiteral::kDeletedOnPlacementByPool); 551 EmitLiteralCondRL<&Assembler::ldr> emit_helper(cond, rt); 552 GenerateInstruction(emit_helper, literal); 553 } 554 // Ldr string pointer. The string is added to the literal pool and the 555 // string's address in the literal pool is loaded in rt (adr instruction). 556 void Ldr(Condition cond, Register rt, const char* str) { 557 RawLiteral* literal = 558 new Literal<const char*>(str, RawLiteral::kDeletedOnPlacementByPool); 559 EmitLiteralCondRL<&Assembler::adr> emit_helper(cond, rt); 560 GenerateInstruction(emit_helper, literal); 561 } 562 template <typename T> 563 void Ldr(Register rt, T v) { 564 Ldr(al, rt, v); 565 } 566 567 // Generic Ldrd(rt, rt2, data) 568 void Ldrd(Condition cond, Register rt, Register rt2, uint64_t v) { 569 RawLiteral* literal = 570 new Literal<uint64_t>(v, RawLiteral::kDeletedOnPlacementByPool); 571 EmitLiteralCondRRL<&Assembler::ldrd> emit_helper(cond, rt, rt2); 572 GenerateInstruction(emit_helper, literal); 573 } 574 template <typename T> 575 void Ldrd(Register rt, Register rt2, T v) { 576 Ldrd(al, rt, rt2, v); 577 } 578 579 void Vldr(Condition cond, SRegister rt, float v) { 580 RawLiteral* literal = 581 new Literal<float>(v, RawLiteral::kDeletedOnPlacementByPool); 582 EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(cond, Untyped32, rt); 583 GenerateInstruction(emit_helper, literal); 584 } 585 void Vldr(SRegister rt, float v) { Vldr(al, rt, v); } 586 587 void Vldr(Condition cond, DRegister rt, double v) { 588 RawLiteral* literal = 589 new Literal<double>(v, RawLiteral::kDeletedOnPlacementByPool); 590 EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(cond, Untyped64, rt); 591 GenerateInstruction(emit_helper, literal); 592 } 593 void Vldr(DRegister rt, double v) { Vldr(al, rt, v); } 594 595 void Vmov(Condition cond, DRegister rt, double v) { Vmov(cond, F64, rt, v); } 596 void Vmov(DRegister rt, double v) { Vmov(al, F64, rt, v); } 597 void Vmov(Condition cond, SRegister rt, float v) { Vmov(cond, F32, rt, v); } 598 void Vmov(SRegister rt, float v) { Vmov(al, F32, rt, v); } 599 600 void Switch(Register reg, JumpTableBase* table); 601 void GenerateSwitchTable(JumpTableBase* table, int table_size); 602 void Case(JumpTableBase* table, int case_index); 603 void Break(JumpTableBase* table); 604 void Default(JumpTableBase* table); 605 void EndSwitch(JumpTableBase* table); 606 607 // Claim memory on the stack. 608 // Note that the Claim, Drop, and Peek helpers below ensure that offsets used 609 // are multiples of 32 bits to help maintain 32-bit SP alignment. 610 // We could `Align{Up,Down}(size, 4)`, but that's potentially problematic: 611 // Claim(3) 612 // Claim(1) 613 // Drop(4) 614 // would seem correct, when in fact: 615 // Claim(3) -> sp = sp - 4 616 // Claim(1) -> sp = sp - 4 617 // Drop(4) -> sp = sp + 4 618 // 619 void Claim(int32_t size) { 620 if (size == 0) return; 621 // The stack must be kept 32bit aligned. 622 VIXL_ASSERT((size > 0) && ((size % 4) == 0)); 623 Sub(sp, sp, size); 624 } 625 // Release memory on the stack 626 void Drop(int32_t size) { 627 if (size == 0) return; 628 // The stack must be kept 32bit aligned. 629 VIXL_ASSERT((size > 0) && ((size % 4) == 0)); 630 Add(sp, sp, size); 631 } 632 void Peek(Register dst, int32_t offset) { 633 VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0)); 634 Ldr(dst, MemOperand(sp, offset)); 635 } 636 void Poke(Register src, int32_t offset) { 637 VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0)); 638 Str(src, MemOperand(sp, offset)); 639 } 640 void Printf(const char* format, 641 CPURegister reg1 = NoReg, 642 CPURegister reg2 = NoReg, 643 CPURegister reg3 = NoReg, 644 CPURegister reg4 = NoReg); 645 // Functions used by Printf for generation. 646 void PushRegister(CPURegister reg); 647 void PreparePrintfArgument(CPURegister reg, 648 int* core_count, 649 int* vfp_count, 650 uint32_t* printf_type); 651 // Handlers for cases not handled by the assembler. 652 virtual void Delegate(InstructionType type, 653 InstructionCondROp instruction, 654 Condition cond, 655 Register rn, 656 const Operand& operand); 657 virtual void Delegate(InstructionType type, 658 InstructionCondSizeROp instruction, 659 Condition cond, 660 EncodingSize size, 661 Register rn, 662 const Operand& operand); 663 virtual void Delegate(InstructionType type, 664 InstructionCondRROp instruction, 665 Condition cond, 666 Register rd, 667 Register rn, 668 const Operand& operand); 669 virtual void Delegate(InstructionType type, 670 InstructionCondSizeRROp instruction, 671 Condition cond, 672 EncodingSize size, 673 Register rd, 674 Register rn, 675 const Operand& operand); 676 virtual void Delegate(InstructionType type, 677 InstructionRL instruction, 678 Register rn, 679 Label* label); 680 virtual void Delegate(InstructionType type, 681 InstructionCondDtSSop instruction, 682 Condition cond, 683 DataType dt, 684 SRegister rd, 685 const SOperand& operand); 686 virtual void Delegate(InstructionType type, 687 InstructionCondDtDDop instruction, 688 Condition cond, 689 DataType dt, 690 DRegister rd, 691 const DOperand& operand); 692 virtual void Delegate(InstructionType type, 693 InstructionCondDtQQop instruction, 694 Condition cond, 695 DataType dt, 696 QRegister rd, 697 const QOperand& operand); 698 virtual void Delegate(InstructionType type, 699 InstructionCondMop instruction, 700 Condition cond, 701 const MemOperand& operand); 702 virtual void Delegate(InstructionType type, 703 InstructionCondRMop instruction, 704 Condition cond, 705 Register rd, 706 const MemOperand& operand); 707 virtual void Delegate(InstructionType type, 708 InstructionCondSizeRMop instruction, 709 Condition cond, 710 EncodingSize size, 711 Register rd, 712 const MemOperand& operand); 713 virtual void Delegate(InstructionType type, 714 InstructionCondRRMop instruction, 715 Condition cond, 716 Register rt, 717 Register rt2, 718 const MemOperand& operand); 719 virtual void Delegate(InstructionType type, 720 InstructionCondRRRMop instruction, 721 Condition cond, 722 Register rd, 723 Register rt, 724 Register rt2, 725 const MemOperand& operand); 726 virtual void Delegate(InstructionType type, 727 InstructionCondDtSMop instruction, 728 Condition cond, 729 DataType dt, 730 SRegister rd, 731 const MemOperand& operand); 732 virtual void Delegate(InstructionType type, 733 InstructionCondDtDMop instruction, 734 Condition cond, 735 DataType dt, 736 DRegister rd, 737 const MemOperand& operand); 738 virtual void Delegate(InstructionType type, 739 InstructionCondDtNrlMop instruction, 740 Condition cond, 741 DataType dt, 742 const NeonRegisterList& reglist, 743 const MemOperand& operand); 744 virtual void Delegate(InstructionType type, 745 InstructionCondMsrOp instruction, 746 Condition cond, 747 MaskedSpecialRegister spec_reg, 748 const Operand& operand); 749 750 // Start of generated code. 751 752 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { 753 VIXL_ASSERT(allow_macro_instructions_); 754 VIXL_ASSERT(OutsideITBlock()); 755 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 756 bool can_use_it = 757 // ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 758 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && 759 operand.GetBaseRegister().IsLow(); 760 ITScope it_scope(this, &cond, can_use_it); 761 adc(cond, rd, rn, operand); 762 } 763 void Adc(Register rd, Register rn, const Operand& operand) { 764 Adc(al, rd, rn, operand); 765 } 766 void Adc(FlagsUpdate flags, 767 Condition cond, 768 Register rd, 769 Register rn, 770 const Operand& operand) { 771 switch (flags) { 772 case LeaveFlags: 773 Adc(cond, rd, rn, operand); 774 break; 775 case SetFlags: 776 Adcs(cond, rd, rn, operand); 777 break; 778 case DontCare: 779 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 780 rn.Is(rd) && operand.IsPlainRegister() && 781 operand.GetBaseRegister().IsLow(); 782 if (can_be_16bit_encoded) { 783 Adcs(cond, rd, rn, operand); 784 } else { 785 Adc(cond, rd, rn, operand); 786 } 787 break; 788 } 789 } 790 void Adc(FlagsUpdate flags, 791 Register rd, 792 Register rn, 793 const Operand& operand) { 794 Adc(flags, al, rd, rn, operand); 795 } 796 797 void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 798 VIXL_ASSERT(allow_macro_instructions_); 799 VIXL_ASSERT(OutsideITBlock()); 800 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 801 ITScope it_scope(this, &cond); 802 adcs(cond, rd, rn, operand); 803 } 804 void Adcs(Register rd, Register rn, const Operand& operand) { 805 Adcs(al, rd, rn, operand); 806 } 807 808 void Add(Condition cond, Register rd, Register rn, const Operand& operand) { 809 VIXL_ASSERT(allow_macro_instructions_); 810 VIXL_ASSERT(OutsideITBlock()); 811 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 812 bool can_use_it = 813 // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 814 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() && 815 rd.IsLow()) || 816 // ADD<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2 817 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 818 rd.IsLow() && rn.Is(rd)) || 819 // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1 820 (operand.IsImmediate() && (operand.GetImmediate() <= 508) && 821 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) || 822 // ADD<c>{<q>} <Rd>, <Rn>, <Rm> 823 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 824 operand.GetBaseRegister().IsLow()) || 825 // ADD<c>{<q>} <Rdn>, <Rm> ; T2 826 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) && 827 !operand.GetBaseRegister().IsSP() && 828 !operand.GetBaseRegister().IsPC()) || 829 // ADD{<c>}{<q>} {<Rdm>,} SP, <Rdm> ; T1 830 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && 831 operand.GetBaseRegister().Is(rd)); 832 ITScope it_scope(this, &cond, can_use_it); 833 add(cond, rd, rn, operand); 834 } 835 void Add(Register rd, Register rn, const Operand& operand) { 836 Add(al, rd, rn, operand); 837 } 838 void Add(FlagsUpdate flags, 839 Condition cond, 840 Register rd, 841 Register rn, 842 const Operand& operand) { 843 switch (flags) { 844 case LeaveFlags: 845 Add(cond, rd, rn, operand); 846 break; 847 case SetFlags: 848 Adds(cond, rd, rn, operand); 849 break; 850 case DontCare: 851 bool can_be_16bit_encoded = 852 IsUsingT32() && cond.Is(al) && 853 ((operand.IsPlainRegister() && 854 ((rd.IsLow() && rn.IsLow() && 855 operand.GetBaseRegister().IsLow()) || 856 rd.Is(rn))) || 857 (operand.IsImmediate() && 858 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) || 859 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256))))); 860 if (can_be_16bit_encoded) { 861 Adds(cond, rd, rn, operand); 862 } else { 863 Add(cond, rd, rn, operand); 864 } 865 break; 866 } 867 } 868 void Add(FlagsUpdate flags, 869 Register rd, 870 Register rn, 871 const Operand& operand) { 872 Add(flags, al, rd, rn, operand); 873 } 874 875 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) { 876 VIXL_ASSERT(allow_macro_instructions_); 877 VIXL_ASSERT(OutsideITBlock()); 878 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 879 ITScope it_scope(this, &cond); 880 adds(cond, rd, rn, operand); 881 } 882 void Adds(Register rd, Register rn, const Operand& operand) { 883 Adds(al, rd, rn, operand); 884 } 885 886 void Addw(Condition cond, Register rd, Register rn, const Operand& operand) { 887 VIXL_ASSERT(allow_macro_instructions_); 888 VIXL_ASSERT(OutsideITBlock()); 889 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 890 ITScope it_scope(this, &cond); 891 addw(cond, rd, rn, operand); 892 } 893 void Addw(Register rd, Register rn, const Operand& operand) { 894 Addw(al, rd, rn, operand); 895 } 896 897 void Adr(Condition cond, Register rd, Label* label) { 898 VIXL_ASSERT(allow_macro_instructions_); 899 VIXL_ASSERT(OutsideITBlock()); 900 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 901 ITScope it_scope(this, &cond); 902 adr(cond, rd, label); 903 } 904 void Adr(Register rd, Label* label) { Adr(al, rd, label); } 905 906 void And(Condition cond, Register rd, Register rn, const Operand& operand) { 907 VIXL_ASSERT(allow_macro_instructions_); 908 VIXL_ASSERT(OutsideITBlock()); 909 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 910 bool can_use_it = 911 // AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 912 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 913 operand.GetBaseRegister().IsLow(); 914 ITScope it_scope(this, &cond, can_use_it); 915 and_(cond, rd, rn, operand); 916 } 917 void And(Register rd, Register rn, const Operand& operand) { 918 And(al, rd, rn, operand); 919 } 920 void And(FlagsUpdate flags, 921 Condition cond, 922 Register rd, 923 Register rn, 924 const Operand& operand) { 925 switch (flags) { 926 case LeaveFlags: 927 And(cond, rd, rn, operand); 928 break; 929 case SetFlags: 930 Ands(cond, rd, rn, operand); 931 break; 932 case DontCare: 933 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 934 rn.Is(rd) && operand.IsPlainRegister() && 935 operand.GetBaseRegister().IsLow(); 936 if (can_be_16bit_encoded) { 937 Ands(cond, rd, rn, operand); 938 } else { 939 And(cond, rd, rn, operand); 940 } 941 break; 942 } 943 } 944 void And(FlagsUpdate flags, 945 Register rd, 946 Register rn, 947 const Operand& operand) { 948 And(flags, al, rd, rn, operand); 949 } 950 951 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) { 952 VIXL_ASSERT(allow_macro_instructions_); 953 VIXL_ASSERT(OutsideITBlock()); 954 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 955 ITScope it_scope(this, &cond); 956 ands(cond, rd, rn, operand); 957 } 958 void Ands(Register rd, Register rn, const Operand& operand) { 959 Ands(al, rd, rn, operand); 960 } 961 962 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { 963 VIXL_ASSERT(allow_macro_instructions_); 964 VIXL_ASSERT(OutsideITBlock()); 965 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 966 bool can_use_it = 967 // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 968 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 969 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || 970 // ASR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 971 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 972 operand.GetBaseRegister().IsLow()); 973 ITScope it_scope(this, &cond, can_use_it); 974 asr(cond, rd, rm, operand); 975 } 976 void Asr(Register rd, Register rm, const Operand& operand) { 977 Asr(al, rd, rm, operand); 978 } 979 void Asr(FlagsUpdate flags, 980 Condition cond, 981 Register rd, 982 Register rm, 983 const Operand& operand) { 984 switch (flags) { 985 case LeaveFlags: 986 Asr(cond, rd, rm, operand); 987 break; 988 case SetFlags: 989 Asrs(cond, rd, rm, operand); 990 break; 991 case DontCare: 992 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 993 rm.IsLow() && operand.IsImmediate() && 994 (operand.GetImmediate() < 32); 995 if (can_be_16bit_encoded) { 996 Asrs(cond, rd, rm, operand); 997 } else { 998 Asr(cond, rd, rm, operand); 999 } 1000 break; 1001 } 1002 } 1003 void Asr(FlagsUpdate flags, 1004 Register rd, 1005 Register rm, 1006 const Operand& operand) { 1007 Asr(flags, al, rd, rm, operand); 1008 } 1009 1010 void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 1011 VIXL_ASSERT(allow_macro_instructions_); 1012 VIXL_ASSERT(OutsideITBlock()); 1013 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1014 ITScope it_scope(this, &cond); 1015 asrs(cond, rd, rm, operand); 1016 } 1017 void Asrs(Register rd, Register rm, const Operand& operand) { 1018 Asrs(al, rd, rm, operand); 1019 } 1020 1021 void B(Condition cond, Label* label) { 1022 VIXL_ASSERT(allow_macro_instructions_); 1023 VIXL_ASSERT(OutsideITBlock()); 1024 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1025 b(cond, label); 1026 AddBranchLabel(label); 1027 } 1028 void B(Label* label) { B(al, label); } 1029 1030 void Bfc(Condition cond, Register rd, uint32_t lsb, const Operand& operand) { 1031 VIXL_ASSERT(allow_macro_instructions_); 1032 VIXL_ASSERT(OutsideITBlock()); 1033 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1034 ITScope it_scope(this, &cond); 1035 bfc(cond, rd, lsb, operand); 1036 } 1037 void Bfc(Register rd, uint32_t lsb, const Operand& operand) { 1038 Bfc(al, rd, lsb, operand); 1039 } 1040 1041 void Bfi(Condition cond, 1042 Register rd, 1043 Register rn, 1044 uint32_t lsb, 1045 const Operand& operand) { 1046 VIXL_ASSERT(allow_macro_instructions_); 1047 VIXL_ASSERT(OutsideITBlock()); 1048 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1049 ITScope it_scope(this, &cond); 1050 bfi(cond, rd, rn, lsb, operand); 1051 } 1052 void Bfi(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 1053 Bfi(al, rd, rn, lsb, operand); 1054 } 1055 1056 void Bic(Condition cond, Register rd, Register rn, const Operand& operand) { 1057 VIXL_ASSERT(allow_macro_instructions_); 1058 VIXL_ASSERT(OutsideITBlock()); 1059 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1060 bool can_use_it = 1061 // BIC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1062 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1063 operand.GetBaseRegister().IsLow(); 1064 ITScope it_scope(this, &cond, can_use_it); 1065 bic(cond, rd, rn, operand); 1066 } 1067 void Bic(Register rd, Register rn, const Operand& operand) { 1068 Bic(al, rd, rn, operand); 1069 } 1070 void Bic(FlagsUpdate flags, 1071 Condition cond, 1072 Register rd, 1073 Register rn, 1074 const Operand& operand) { 1075 switch (flags) { 1076 case LeaveFlags: 1077 Bic(cond, rd, rn, operand); 1078 break; 1079 case SetFlags: 1080 Bics(cond, rd, rn, operand); 1081 break; 1082 case DontCare: 1083 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1084 rn.Is(rd) && operand.IsPlainRegister() && 1085 operand.GetBaseRegister().IsLow(); 1086 if (can_be_16bit_encoded) { 1087 Bics(cond, rd, rn, operand); 1088 } else { 1089 Bic(cond, rd, rn, operand); 1090 } 1091 break; 1092 } 1093 } 1094 void Bic(FlagsUpdate flags, 1095 Register rd, 1096 Register rn, 1097 const Operand& operand) { 1098 Bic(flags, al, rd, rn, operand); 1099 } 1100 1101 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) { 1102 VIXL_ASSERT(allow_macro_instructions_); 1103 VIXL_ASSERT(OutsideITBlock()); 1104 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1105 ITScope it_scope(this, &cond); 1106 bics(cond, rd, rn, operand); 1107 } 1108 void Bics(Register rd, Register rn, const Operand& operand) { 1109 Bics(al, rd, rn, operand); 1110 } 1111 1112 void Bkpt(Condition cond, uint32_t imm) { 1113 VIXL_ASSERT(allow_macro_instructions_); 1114 VIXL_ASSERT(OutsideITBlock()); 1115 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1116 ITScope it_scope(this, &cond); 1117 bkpt(cond, imm); 1118 } 1119 void Bkpt(uint32_t imm) { Bkpt(al, imm); } 1120 1121 void Bl(Condition cond, Label* label) { 1122 VIXL_ASSERT(allow_macro_instructions_); 1123 VIXL_ASSERT(OutsideITBlock()); 1124 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1125 ITScope it_scope(this, &cond); 1126 bl(cond, label); 1127 AddBranchLabel(label); 1128 } 1129 void Bl(Label* label) { Bl(al, label); } 1130 1131 void Blx(Condition cond, Label* label) { 1132 VIXL_ASSERT(allow_macro_instructions_); 1133 VIXL_ASSERT(OutsideITBlock()); 1134 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1135 ITScope it_scope(this, &cond); 1136 blx(cond, label); 1137 AddBranchLabel(label); 1138 } 1139 void Blx(Label* label) { Blx(al, label); } 1140 1141 void Blx(Condition cond, Register rm) { 1142 VIXL_ASSERT(allow_macro_instructions_); 1143 VIXL_ASSERT(OutsideITBlock()); 1144 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1145 bool can_use_it = 1146 // BLX{<c>}{<q>} <Rm> ; T1 1147 !rm.IsPC(); 1148 ITScope it_scope(this, &cond, can_use_it); 1149 blx(cond, rm); 1150 } 1151 void Blx(Register rm) { Blx(al, rm); } 1152 1153 void Bx(Condition cond, Register rm) { 1154 VIXL_ASSERT(allow_macro_instructions_); 1155 VIXL_ASSERT(OutsideITBlock()); 1156 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1157 bool can_use_it = 1158 // BX{<c>}{<q>} <Rm> ; T1 1159 !rm.IsPC(); 1160 ITScope it_scope(this, &cond, can_use_it); 1161 bx(cond, rm); 1162 } 1163 void Bx(Register rm) { Bx(al, rm); } 1164 1165 void Bxj(Condition cond, Register rm) { 1166 VIXL_ASSERT(allow_macro_instructions_); 1167 VIXL_ASSERT(OutsideITBlock()); 1168 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1169 ITScope it_scope(this, &cond); 1170 bxj(cond, rm); 1171 } 1172 void Bxj(Register rm) { Bxj(al, rm); } 1173 1174 void Cbnz(Register rn, Label* label) { 1175 VIXL_ASSERT(allow_macro_instructions_); 1176 VIXL_ASSERT(OutsideITBlock()); 1177 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1178 cbnz(rn, label); 1179 AddBranchLabel(label); 1180 } 1181 1182 void Cbz(Register rn, Label* label) { 1183 VIXL_ASSERT(allow_macro_instructions_); 1184 VIXL_ASSERT(OutsideITBlock()); 1185 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1186 cbz(rn, label); 1187 AddBranchLabel(label); 1188 } 1189 1190 void Clrex(Condition cond) { 1191 VIXL_ASSERT(allow_macro_instructions_); 1192 VIXL_ASSERT(OutsideITBlock()); 1193 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1194 ITScope it_scope(this, &cond); 1195 clrex(cond); 1196 } 1197 void Clrex() { Clrex(al); } 1198 1199 void Clz(Condition cond, Register rd, Register rm) { 1200 VIXL_ASSERT(allow_macro_instructions_); 1201 VIXL_ASSERT(OutsideITBlock()); 1202 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1203 ITScope it_scope(this, &cond); 1204 clz(cond, rd, rm); 1205 } 1206 void Clz(Register rd, Register rm) { Clz(al, rd, rm); } 1207 1208 void Cmn(Condition cond, Register rn, const Operand& operand) { 1209 VIXL_ASSERT(allow_macro_instructions_); 1210 VIXL_ASSERT(OutsideITBlock()); 1211 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1212 bool can_use_it = 1213 // CMN{<c>}{<q>} <Rn>, <Rm> ; T1 1214 operand.IsPlainRegister() && rn.IsLow() && 1215 operand.GetBaseRegister().IsLow(); 1216 ITScope it_scope(this, &cond, can_use_it); 1217 cmn(cond, rn, operand); 1218 } 1219 void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); } 1220 1221 void Cmp(Condition cond, Register rn, const Operand& operand) { 1222 VIXL_ASSERT(allow_macro_instructions_); 1223 VIXL_ASSERT(OutsideITBlock()); 1224 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1225 bool can_use_it = 1226 // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1 1227 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 1228 rn.IsLow()) || 1229 // CMP{<c>}{<q>} <Rn>, <Rm> ; T1 T2 1230 (operand.IsPlainRegister() && !rn.IsPC() && 1231 !operand.GetBaseRegister().IsPC()); 1232 ITScope it_scope(this, &cond, can_use_it); 1233 cmp(cond, rn, operand); 1234 } 1235 void Cmp(Register rn, const Operand& operand) { Cmp(al, rn, operand); } 1236 1237 void Crc32b(Condition cond, Register rd, Register rn, Register rm) { 1238 VIXL_ASSERT(allow_macro_instructions_); 1239 VIXL_ASSERT(OutsideITBlock()); 1240 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1241 ITScope it_scope(this, &cond); 1242 crc32b(cond, rd, rn, rm); 1243 } 1244 void Crc32b(Register rd, Register rn, Register rm) { Crc32b(al, rd, rn, rm); } 1245 1246 void Crc32cb(Condition cond, Register rd, Register rn, Register rm) { 1247 VIXL_ASSERT(allow_macro_instructions_); 1248 VIXL_ASSERT(OutsideITBlock()); 1249 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1250 ITScope it_scope(this, &cond); 1251 crc32cb(cond, rd, rn, rm); 1252 } 1253 void Crc32cb(Register rd, Register rn, Register rm) { 1254 Crc32cb(al, rd, rn, rm); 1255 } 1256 1257 void Crc32ch(Condition cond, Register rd, Register rn, Register rm) { 1258 VIXL_ASSERT(allow_macro_instructions_); 1259 VIXL_ASSERT(OutsideITBlock()); 1260 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1261 ITScope it_scope(this, &cond); 1262 crc32ch(cond, rd, rn, rm); 1263 } 1264 void Crc32ch(Register rd, Register rn, Register rm) { 1265 Crc32ch(al, rd, rn, rm); 1266 } 1267 1268 void Crc32cw(Condition cond, Register rd, Register rn, Register rm) { 1269 VIXL_ASSERT(allow_macro_instructions_); 1270 VIXL_ASSERT(OutsideITBlock()); 1271 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1272 ITScope it_scope(this, &cond); 1273 crc32cw(cond, rd, rn, rm); 1274 } 1275 void Crc32cw(Register rd, Register rn, Register rm) { 1276 Crc32cw(al, rd, rn, rm); 1277 } 1278 1279 void Crc32h(Condition cond, Register rd, Register rn, Register rm) { 1280 VIXL_ASSERT(allow_macro_instructions_); 1281 VIXL_ASSERT(OutsideITBlock()); 1282 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1283 ITScope it_scope(this, &cond); 1284 crc32h(cond, rd, rn, rm); 1285 } 1286 void Crc32h(Register rd, Register rn, Register rm) { Crc32h(al, rd, rn, rm); } 1287 1288 void Crc32w(Condition cond, Register rd, Register rn, Register rm) { 1289 VIXL_ASSERT(allow_macro_instructions_); 1290 VIXL_ASSERT(OutsideITBlock()); 1291 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1292 ITScope it_scope(this, &cond); 1293 crc32w(cond, rd, rn, rm); 1294 } 1295 void Crc32w(Register rd, Register rn, Register rm) { Crc32w(al, rd, rn, rm); } 1296 1297 void Dmb(Condition cond, MemoryBarrier option) { 1298 VIXL_ASSERT(allow_macro_instructions_); 1299 VIXL_ASSERT(OutsideITBlock()); 1300 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1301 ITScope it_scope(this, &cond); 1302 dmb(cond, option); 1303 } 1304 void Dmb(MemoryBarrier option) { Dmb(al, option); } 1305 1306 void Dsb(Condition cond, MemoryBarrier option) { 1307 VIXL_ASSERT(allow_macro_instructions_); 1308 VIXL_ASSERT(OutsideITBlock()); 1309 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1310 ITScope it_scope(this, &cond); 1311 dsb(cond, option); 1312 } 1313 void Dsb(MemoryBarrier option) { Dsb(al, option); } 1314 1315 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { 1316 VIXL_ASSERT(allow_macro_instructions_); 1317 VIXL_ASSERT(OutsideITBlock()); 1318 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1319 bool can_use_it = 1320 // EOR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1321 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1322 operand.GetBaseRegister().IsLow(); 1323 ITScope it_scope(this, &cond, can_use_it); 1324 eor(cond, rd, rn, operand); 1325 } 1326 void Eor(Register rd, Register rn, const Operand& operand) { 1327 Eor(al, rd, rn, operand); 1328 } 1329 void Eor(FlagsUpdate flags, 1330 Condition cond, 1331 Register rd, 1332 Register rn, 1333 const Operand& operand) { 1334 switch (flags) { 1335 case LeaveFlags: 1336 Eor(cond, rd, rn, operand); 1337 break; 1338 case SetFlags: 1339 Eors(cond, rd, rn, operand); 1340 break; 1341 case DontCare: 1342 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1343 rn.Is(rd) && operand.IsPlainRegister() && 1344 operand.GetBaseRegister().IsLow(); 1345 if (can_be_16bit_encoded) { 1346 Eors(cond, rd, rn, operand); 1347 } else { 1348 Eor(cond, rd, rn, operand); 1349 } 1350 break; 1351 } 1352 } 1353 void Eor(FlagsUpdate flags, 1354 Register rd, 1355 Register rn, 1356 const Operand& operand) { 1357 Eor(flags, al, rd, rn, operand); 1358 } 1359 1360 void Eors(Condition cond, Register rd, Register rn, const Operand& operand) { 1361 VIXL_ASSERT(allow_macro_instructions_); 1362 VIXL_ASSERT(OutsideITBlock()); 1363 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1364 ITScope it_scope(this, &cond); 1365 eors(cond, rd, rn, operand); 1366 } 1367 void Eors(Register rd, Register rn, const Operand& operand) { 1368 Eors(al, rd, rn, operand); 1369 } 1370 1371 void Fldmdbx(Condition cond, 1372 Register rn, 1373 WriteBack write_back, 1374 DRegisterList dreglist) { 1375 VIXL_ASSERT(allow_macro_instructions_); 1376 VIXL_ASSERT(OutsideITBlock()); 1377 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1378 ITScope it_scope(this, &cond); 1379 fldmdbx(cond, rn, write_back, dreglist); 1380 } 1381 void Fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1382 Fldmdbx(al, rn, write_back, dreglist); 1383 } 1384 1385 void Fldmiax(Condition cond, 1386 Register rn, 1387 WriteBack write_back, 1388 DRegisterList dreglist) { 1389 VIXL_ASSERT(allow_macro_instructions_); 1390 VIXL_ASSERT(OutsideITBlock()); 1391 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1392 ITScope it_scope(this, &cond); 1393 fldmiax(cond, rn, write_back, dreglist); 1394 } 1395 void Fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1396 Fldmiax(al, rn, write_back, dreglist); 1397 } 1398 1399 void Fstmdbx(Condition cond, 1400 Register rn, 1401 WriteBack write_back, 1402 DRegisterList dreglist) { 1403 VIXL_ASSERT(allow_macro_instructions_); 1404 VIXL_ASSERT(OutsideITBlock()); 1405 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1406 ITScope it_scope(this, &cond); 1407 fstmdbx(cond, rn, write_back, dreglist); 1408 } 1409 void Fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1410 Fstmdbx(al, rn, write_back, dreglist); 1411 } 1412 1413 void Fstmiax(Condition cond, 1414 Register rn, 1415 WriteBack write_back, 1416 DRegisterList dreglist) { 1417 VIXL_ASSERT(allow_macro_instructions_); 1418 VIXL_ASSERT(OutsideITBlock()); 1419 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1420 ITScope it_scope(this, &cond); 1421 fstmiax(cond, rn, write_back, dreglist); 1422 } 1423 void Fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1424 Fstmiax(al, rn, write_back, dreglist); 1425 } 1426 1427 void Hlt(Condition cond, uint32_t imm) { 1428 VIXL_ASSERT(allow_macro_instructions_); 1429 VIXL_ASSERT(OutsideITBlock()); 1430 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1431 ITScope it_scope(this, &cond); 1432 hlt(cond, imm); 1433 } 1434 void Hlt(uint32_t imm) { Hlt(al, imm); } 1435 1436 void Hvc(Condition cond, uint32_t imm) { 1437 VIXL_ASSERT(allow_macro_instructions_); 1438 VIXL_ASSERT(OutsideITBlock()); 1439 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1440 ITScope it_scope(this, &cond); 1441 hvc(cond, imm); 1442 } 1443 void Hvc(uint32_t imm) { Hvc(al, imm); } 1444 1445 void Isb(Condition cond, MemoryBarrier option) { 1446 VIXL_ASSERT(allow_macro_instructions_); 1447 VIXL_ASSERT(OutsideITBlock()); 1448 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1449 ITScope it_scope(this, &cond); 1450 isb(cond, option); 1451 } 1452 void Isb(MemoryBarrier option) { Isb(al, option); } 1453 1454 void Lda(Condition cond, Register rt, const MemOperand& operand) { 1455 VIXL_ASSERT(allow_macro_instructions_); 1456 VIXL_ASSERT(OutsideITBlock()); 1457 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1458 ITScope it_scope(this, &cond); 1459 lda(cond, rt, operand); 1460 } 1461 void Lda(Register rt, const MemOperand& operand) { Lda(al, rt, operand); } 1462 1463 void Ldab(Condition cond, Register rt, const MemOperand& operand) { 1464 VIXL_ASSERT(allow_macro_instructions_); 1465 VIXL_ASSERT(OutsideITBlock()); 1466 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1467 ITScope it_scope(this, &cond); 1468 ldab(cond, rt, operand); 1469 } 1470 void Ldab(Register rt, const MemOperand& operand) { Ldab(al, rt, operand); } 1471 1472 void Ldaex(Condition cond, Register rt, const MemOperand& operand) { 1473 VIXL_ASSERT(allow_macro_instructions_); 1474 VIXL_ASSERT(OutsideITBlock()); 1475 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1476 ITScope it_scope(this, &cond); 1477 ldaex(cond, rt, operand); 1478 } 1479 void Ldaex(Register rt, const MemOperand& operand) { Ldaex(al, rt, operand); } 1480 1481 void Ldaexb(Condition cond, Register rt, const MemOperand& operand) { 1482 VIXL_ASSERT(allow_macro_instructions_); 1483 VIXL_ASSERT(OutsideITBlock()); 1484 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1485 ITScope it_scope(this, &cond); 1486 ldaexb(cond, rt, operand); 1487 } 1488 void Ldaexb(Register rt, const MemOperand& operand) { 1489 Ldaexb(al, rt, operand); 1490 } 1491 1492 void Ldaexd(Condition cond, 1493 Register rt, 1494 Register rt2, 1495 const MemOperand& operand) { 1496 VIXL_ASSERT(allow_macro_instructions_); 1497 VIXL_ASSERT(OutsideITBlock()); 1498 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1499 ITScope it_scope(this, &cond); 1500 ldaexd(cond, rt, rt2, operand); 1501 } 1502 void Ldaexd(Register rt, Register rt2, const MemOperand& operand) { 1503 Ldaexd(al, rt, rt2, operand); 1504 } 1505 1506 void Ldaexh(Condition cond, Register rt, const MemOperand& operand) { 1507 VIXL_ASSERT(allow_macro_instructions_); 1508 VIXL_ASSERT(OutsideITBlock()); 1509 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1510 ITScope it_scope(this, &cond); 1511 ldaexh(cond, rt, operand); 1512 } 1513 void Ldaexh(Register rt, const MemOperand& operand) { 1514 Ldaexh(al, rt, operand); 1515 } 1516 1517 void Ldah(Condition cond, Register rt, const MemOperand& operand) { 1518 VIXL_ASSERT(allow_macro_instructions_); 1519 VIXL_ASSERT(OutsideITBlock()); 1520 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1521 ITScope it_scope(this, &cond); 1522 ldah(cond, rt, operand); 1523 } 1524 void Ldah(Register rt, const MemOperand& operand) { Ldah(al, rt, operand); } 1525 1526 void Ldm(Condition cond, 1527 Register rn, 1528 WriteBack write_back, 1529 RegisterList registers) { 1530 VIXL_ASSERT(allow_macro_instructions_); 1531 VIXL_ASSERT(OutsideITBlock()); 1532 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1533 ITScope it_scope(this, &cond); 1534 ldm(cond, rn, write_back, registers); 1535 } 1536 void Ldm(Register rn, WriteBack write_back, RegisterList registers) { 1537 Ldm(al, rn, write_back, registers); 1538 } 1539 1540 void Ldmda(Condition cond, 1541 Register rn, 1542 WriteBack write_back, 1543 RegisterList registers) { 1544 VIXL_ASSERT(allow_macro_instructions_); 1545 VIXL_ASSERT(OutsideITBlock()); 1546 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1547 ITScope it_scope(this, &cond); 1548 ldmda(cond, rn, write_back, registers); 1549 } 1550 void Ldmda(Register rn, WriteBack write_back, RegisterList registers) { 1551 Ldmda(al, rn, write_back, registers); 1552 } 1553 1554 void Ldmdb(Condition cond, 1555 Register rn, 1556 WriteBack write_back, 1557 RegisterList registers) { 1558 VIXL_ASSERT(allow_macro_instructions_); 1559 VIXL_ASSERT(OutsideITBlock()); 1560 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1561 ITScope it_scope(this, &cond); 1562 ldmdb(cond, rn, write_back, registers); 1563 } 1564 void Ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 1565 Ldmdb(al, rn, write_back, registers); 1566 } 1567 1568 void Ldmea(Condition cond, 1569 Register rn, 1570 WriteBack write_back, 1571 RegisterList registers) { 1572 VIXL_ASSERT(allow_macro_instructions_); 1573 VIXL_ASSERT(OutsideITBlock()); 1574 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1575 ITScope it_scope(this, &cond); 1576 ldmea(cond, rn, write_back, registers); 1577 } 1578 void Ldmea(Register rn, WriteBack write_back, RegisterList registers) { 1579 Ldmea(al, rn, write_back, registers); 1580 } 1581 1582 void Ldmed(Condition cond, 1583 Register rn, 1584 WriteBack write_back, 1585 RegisterList registers) { 1586 VIXL_ASSERT(allow_macro_instructions_); 1587 VIXL_ASSERT(OutsideITBlock()); 1588 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1589 ITScope it_scope(this, &cond); 1590 ldmed(cond, rn, write_back, registers); 1591 } 1592 void Ldmed(Register rn, WriteBack write_back, RegisterList registers) { 1593 Ldmed(al, rn, write_back, registers); 1594 } 1595 1596 void Ldmfa(Condition cond, 1597 Register rn, 1598 WriteBack write_back, 1599 RegisterList registers) { 1600 VIXL_ASSERT(allow_macro_instructions_); 1601 VIXL_ASSERT(OutsideITBlock()); 1602 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1603 ITScope it_scope(this, &cond); 1604 ldmfa(cond, rn, write_back, registers); 1605 } 1606 void Ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 1607 Ldmfa(al, rn, write_back, registers); 1608 } 1609 1610 void Ldmfd(Condition cond, 1611 Register rn, 1612 WriteBack write_back, 1613 RegisterList registers) { 1614 VIXL_ASSERT(allow_macro_instructions_); 1615 VIXL_ASSERT(OutsideITBlock()); 1616 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1617 ITScope it_scope(this, &cond); 1618 ldmfd(cond, rn, write_back, registers); 1619 } 1620 void Ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 1621 Ldmfd(al, rn, write_back, registers); 1622 } 1623 1624 void Ldmib(Condition cond, 1625 Register rn, 1626 WriteBack write_back, 1627 RegisterList registers) { 1628 VIXL_ASSERT(allow_macro_instructions_); 1629 VIXL_ASSERT(OutsideITBlock()); 1630 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1631 ITScope it_scope(this, &cond); 1632 ldmib(cond, rn, write_back, registers); 1633 } 1634 void Ldmib(Register rn, WriteBack write_back, RegisterList registers) { 1635 Ldmib(al, rn, write_back, registers); 1636 } 1637 1638 void Ldr(Condition cond, Register rt, const MemOperand& operand) { 1639 VIXL_ASSERT(allow_macro_instructions_); 1640 VIXL_ASSERT(OutsideITBlock()); 1641 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1642 bool can_use_it = 1643 // LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 1644 (operand.IsImmediate() && rt.IsLow() && 1645 operand.GetBaseRegister().IsLow() && 1646 operand.IsOffsetImmediateWithinRange(0, 124, 4) && 1647 (operand.GetAddrMode() == Offset)) || 1648 // LDR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2 1649 (operand.IsImmediate() && rt.IsLow() && 1650 operand.GetBaseRegister().IsSP() && 1651 operand.IsOffsetImmediateWithinRange(0, 1020, 4) && 1652 (operand.GetAddrMode() == Offset)) || 1653 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1654 (operand.IsPlainRegister() && rt.IsLow() && 1655 operand.GetBaseRegister().IsLow() && 1656 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1657 (operand.GetAddrMode() == Offset)); 1658 ITScope it_scope(this, &cond, can_use_it); 1659 ldr(cond, rt, operand); 1660 } 1661 void Ldr(Register rt, const MemOperand& operand) { Ldr(al, rt, operand); } 1662 1663 void Ldr(Condition cond, Register rt, Label* label) { 1664 VIXL_ASSERT(allow_macro_instructions_); 1665 VIXL_ASSERT(OutsideITBlock()); 1666 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1667 ITScope it_scope(this, &cond); 1668 ldr(cond, rt, label); 1669 } 1670 void Ldr(Register rt, Label* label) { Ldr(al, rt, label); } 1671 1672 void Ldrb(Condition cond, Register rt, const MemOperand& operand) { 1673 VIXL_ASSERT(allow_macro_instructions_); 1674 VIXL_ASSERT(OutsideITBlock()); 1675 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1676 bool can_use_it = 1677 // LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 1678 (operand.IsImmediate() && rt.IsLow() && 1679 operand.GetBaseRegister().IsLow() && 1680 operand.IsOffsetImmediateWithinRange(0, 31) && 1681 (operand.GetAddrMode() == Offset)) || 1682 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1683 (operand.IsPlainRegister() && rt.IsLow() && 1684 operand.GetBaseRegister().IsLow() && 1685 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1686 (operand.GetAddrMode() == Offset)); 1687 ITScope it_scope(this, &cond, can_use_it); 1688 ldrb(cond, rt, operand); 1689 } 1690 void Ldrb(Register rt, const MemOperand& operand) { Ldrb(al, rt, operand); } 1691 1692 void Ldrb(Condition cond, Register rt, Label* label) { 1693 VIXL_ASSERT(allow_macro_instructions_); 1694 VIXL_ASSERT(OutsideITBlock()); 1695 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1696 ITScope it_scope(this, &cond); 1697 ldrb(cond, rt, label); 1698 } 1699 void Ldrb(Register rt, Label* label) { Ldrb(al, rt, label); } 1700 1701 void Ldrd(Condition cond, 1702 Register rt, 1703 Register rt2, 1704 const MemOperand& operand) { 1705 VIXL_ASSERT(allow_macro_instructions_); 1706 VIXL_ASSERT(OutsideITBlock()); 1707 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1708 ITScope it_scope(this, &cond); 1709 ldrd(cond, rt, rt2, operand); 1710 } 1711 void Ldrd(Register rt, Register rt2, const MemOperand& operand) { 1712 Ldrd(al, rt, rt2, operand); 1713 } 1714 1715 void Ldrd(Condition cond, Register rt, Register rt2, Label* label) { 1716 VIXL_ASSERT(allow_macro_instructions_); 1717 VIXL_ASSERT(OutsideITBlock()); 1718 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1719 ITScope it_scope(this, &cond); 1720 ldrd(cond, rt, rt2, label); 1721 } 1722 void Ldrd(Register rt, Register rt2, Label* label) { 1723 Ldrd(al, rt, rt2, label); 1724 } 1725 1726 void Ldrex(Condition cond, Register rt, const MemOperand& operand) { 1727 VIXL_ASSERT(allow_macro_instructions_); 1728 VIXL_ASSERT(OutsideITBlock()); 1729 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1730 ITScope it_scope(this, &cond); 1731 ldrex(cond, rt, operand); 1732 } 1733 void Ldrex(Register rt, const MemOperand& operand) { Ldrex(al, rt, operand); } 1734 1735 void Ldrexb(Condition cond, Register rt, const MemOperand& operand) { 1736 VIXL_ASSERT(allow_macro_instructions_); 1737 VIXL_ASSERT(OutsideITBlock()); 1738 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1739 ITScope it_scope(this, &cond); 1740 ldrexb(cond, rt, operand); 1741 } 1742 void Ldrexb(Register rt, const MemOperand& operand) { 1743 Ldrexb(al, rt, operand); 1744 } 1745 1746 void Ldrexd(Condition cond, 1747 Register rt, 1748 Register rt2, 1749 const MemOperand& operand) { 1750 VIXL_ASSERT(allow_macro_instructions_); 1751 VIXL_ASSERT(OutsideITBlock()); 1752 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1753 ITScope it_scope(this, &cond); 1754 ldrexd(cond, rt, rt2, operand); 1755 } 1756 void Ldrexd(Register rt, Register rt2, const MemOperand& operand) { 1757 Ldrexd(al, rt, rt2, operand); 1758 } 1759 1760 void Ldrexh(Condition cond, Register rt, const MemOperand& operand) { 1761 VIXL_ASSERT(allow_macro_instructions_); 1762 VIXL_ASSERT(OutsideITBlock()); 1763 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1764 ITScope it_scope(this, &cond); 1765 ldrexh(cond, rt, operand); 1766 } 1767 void Ldrexh(Register rt, const MemOperand& operand) { 1768 Ldrexh(al, rt, operand); 1769 } 1770 1771 void Ldrh(Condition cond, Register rt, const MemOperand& operand) { 1772 VIXL_ASSERT(allow_macro_instructions_); 1773 VIXL_ASSERT(OutsideITBlock()); 1774 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1775 bool can_use_it = 1776 // LDRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 1777 (operand.IsImmediate() && rt.IsLow() && 1778 operand.GetBaseRegister().IsLow() && 1779 operand.IsOffsetImmediateWithinRange(0, 62, 2) && 1780 (operand.GetAddrMode() == Offset)) || 1781 // LDRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1782 (operand.IsPlainRegister() && rt.IsLow() && 1783 operand.GetBaseRegister().IsLow() && 1784 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1785 (operand.GetAddrMode() == Offset)); 1786 ITScope it_scope(this, &cond, can_use_it); 1787 ldrh(cond, rt, operand); 1788 } 1789 void Ldrh(Register rt, const MemOperand& operand) { Ldrh(al, rt, operand); } 1790 1791 void Ldrh(Condition cond, Register rt, Label* label) { 1792 VIXL_ASSERT(allow_macro_instructions_); 1793 VIXL_ASSERT(OutsideITBlock()); 1794 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1795 ITScope it_scope(this, &cond); 1796 ldrh(cond, rt, label); 1797 } 1798 void Ldrh(Register rt, Label* label) { Ldrh(al, rt, label); } 1799 1800 void Ldrsb(Condition cond, Register rt, const MemOperand& operand) { 1801 VIXL_ASSERT(allow_macro_instructions_); 1802 VIXL_ASSERT(OutsideITBlock()); 1803 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1804 bool can_use_it = 1805 // LDRSB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1806 operand.IsPlainRegister() && rt.IsLow() && 1807 operand.GetBaseRegister().IsLow() && 1808 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1809 (operand.GetAddrMode() == Offset); 1810 ITScope it_scope(this, &cond, can_use_it); 1811 ldrsb(cond, rt, operand); 1812 } 1813 void Ldrsb(Register rt, const MemOperand& operand) { Ldrsb(al, rt, operand); } 1814 1815 void Ldrsb(Condition cond, Register rt, Label* label) { 1816 VIXL_ASSERT(allow_macro_instructions_); 1817 VIXL_ASSERT(OutsideITBlock()); 1818 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1819 ITScope it_scope(this, &cond); 1820 ldrsb(cond, rt, label); 1821 } 1822 void Ldrsb(Register rt, Label* label) { Ldrsb(al, rt, label); } 1823 1824 void Ldrsh(Condition cond, Register rt, const MemOperand& operand) { 1825 VIXL_ASSERT(allow_macro_instructions_); 1826 VIXL_ASSERT(OutsideITBlock()); 1827 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1828 bool can_use_it = 1829 // LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 1830 operand.IsPlainRegister() && rt.IsLow() && 1831 operand.GetBaseRegister().IsLow() && 1832 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 1833 (operand.GetAddrMode() == Offset); 1834 ITScope it_scope(this, &cond, can_use_it); 1835 ldrsh(cond, rt, operand); 1836 } 1837 void Ldrsh(Register rt, const MemOperand& operand) { Ldrsh(al, rt, operand); } 1838 1839 void Ldrsh(Condition cond, Register rt, Label* label) { 1840 VIXL_ASSERT(allow_macro_instructions_); 1841 VIXL_ASSERT(OutsideITBlock()); 1842 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1843 ITScope it_scope(this, &cond); 1844 ldrsh(cond, rt, label); 1845 } 1846 void Ldrsh(Register rt, Label* label) { Ldrsh(al, rt, label); } 1847 1848 void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 1849 VIXL_ASSERT(allow_macro_instructions_); 1850 VIXL_ASSERT(OutsideITBlock()); 1851 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1852 bool can_use_it = 1853 // LSL<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 1854 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 1855 (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) || 1856 // LSL<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 1857 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 1858 operand.GetBaseRegister().IsLow()); 1859 ITScope it_scope(this, &cond, can_use_it); 1860 lsl(cond, rd, rm, operand); 1861 } 1862 void Lsl(Register rd, Register rm, const Operand& operand) { 1863 Lsl(al, rd, rm, operand); 1864 } 1865 void Lsl(FlagsUpdate flags, 1866 Condition cond, 1867 Register rd, 1868 Register rm, 1869 const Operand& operand) { 1870 switch (flags) { 1871 case LeaveFlags: 1872 Lsl(cond, rd, rm, operand); 1873 break; 1874 case SetFlags: 1875 Lsls(cond, rd, rm, operand); 1876 break; 1877 case DontCare: 1878 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1879 rm.IsLow() && operand.IsImmediate() && 1880 (operand.GetImmediate() < 32) && 1881 (operand.GetImmediate() != 0); 1882 if (can_be_16bit_encoded) { 1883 Lsls(cond, rd, rm, operand); 1884 } else { 1885 Lsl(cond, rd, rm, operand); 1886 } 1887 break; 1888 } 1889 } 1890 void Lsl(FlagsUpdate flags, 1891 Register rd, 1892 Register rm, 1893 const Operand& operand) { 1894 Lsl(flags, al, rd, rm, operand); 1895 } 1896 1897 void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 1898 VIXL_ASSERT(allow_macro_instructions_); 1899 VIXL_ASSERT(OutsideITBlock()); 1900 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1901 ITScope it_scope(this, &cond); 1902 lsls(cond, rd, rm, operand); 1903 } 1904 void Lsls(Register rd, Register rm, const Operand& operand) { 1905 Lsls(al, rd, rm, operand); 1906 } 1907 1908 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 1909 VIXL_ASSERT(allow_macro_instructions_); 1910 VIXL_ASSERT(OutsideITBlock()); 1911 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1912 bool can_use_it = 1913 // LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 1914 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 1915 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || 1916 // LSR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 1917 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 1918 operand.GetBaseRegister().IsLow()); 1919 ITScope it_scope(this, &cond, can_use_it); 1920 lsr(cond, rd, rm, operand); 1921 } 1922 void Lsr(Register rd, Register rm, const Operand& operand) { 1923 Lsr(al, rd, rm, operand); 1924 } 1925 void Lsr(FlagsUpdate flags, 1926 Condition cond, 1927 Register rd, 1928 Register rm, 1929 const Operand& operand) { 1930 switch (flags) { 1931 case LeaveFlags: 1932 Lsr(cond, rd, rm, operand); 1933 break; 1934 case SetFlags: 1935 Lsrs(cond, rd, rm, operand); 1936 break; 1937 case DontCare: 1938 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1939 rm.IsLow() && operand.IsImmediate() && 1940 (operand.GetImmediate() < 32); 1941 if (can_be_16bit_encoded) { 1942 Lsrs(cond, rd, rm, operand); 1943 } else { 1944 Lsr(cond, rd, rm, operand); 1945 } 1946 break; 1947 } 1948 } 1949 void Lsr(FlagsUpdate flags, 1950 Register rd, 1951 Register rm, 1952 const Operand& operand) { 1953 Lsr(flags, al, rd, rm, operand); 1954 } 1955 1956 void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 1957 VIXL_ASSERT(allow_macro_instructions_); 1958 VIXL_ASSERT(OutsideITBlock()); 1959 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1960 ITScope it_scope(this, &cond); 1961 lsrs(cond, rd, rm, operand); 1962 } 1963 void Lsrs(Register rd, Register rm, const Operand& operand) { 1964 Lsrs(al, rd, rm, operand); 1965 } 1966 1967 void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) { 1968 VIXL_ASSERT(allow_macro_instructions_); 1969 VIXL_ASSERT(OutsideITBlock()); 1970 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 1971 ITScope it_scope(this, &cond); 1972 mla(cond, rd, rn, rm, ra); 1973 } 1974 void Mla(Register rd, Register rn, Register rm, Register ra) { 1975 Mla(al, rd, rn, rm, ra); 1976 } 1977 void Mla(FlagsUpdate flags, 1978 Condition cond, 1979 Register rd, 1980 Register rn, 1981 Register rm, 1982 Register ra) { 1983 switch (flags) { 1984 case LeaveFlags: 1985 Mla(cond, rd, rn, rm, ra); 1986 break; 1987 case SetFlags: 1988 Mlas(cond, rd, rn, rm, ra); 1989 break; 1990 case DontCare: 1991 Mla(cond, rd, rn, rm, ra); 1992 break; 1993 } 1994 } 1995 void Mla( 1996 FlagsUpdate flags, Register rd, Register rn, Register rm, Register ra) { 1997 Mla(flags, al, rd, rn, rm, ra); 1998 } 1999 2000 void Mlas( 2001 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2002 VIXL_ASSERT(allow_macro_instructions_); 2003 VIXL_ASSERT(OutsideITBlock()); 2004 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2005 ITScope it_scope(this, &cond); 2006 mlas(cond, rd, rn, rm, ra); 2007 } 2008 void Mlas(Register rd, Register rn, Register rm, Register ra) { 2009 Mlas(al, rd, rn, rm, ra); 2010 } 2011 2012 void Mls(Condition cond, Register rd, Register rn, Register rm, Register ra) { 2013 VIXL_ASSERT(allow_macro_instructions_); 2014 VIXL_ASSERT(OutsideITBlock()); 2015 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2016 ITScope it_scope(this, &cond); 2017 mls(cond, rd, rn, rm, ra); 2018 } 2019 void Mls(Register rd, Register rn, Register rm, Register ra) { 2020 Mls(al, rd, rn, rm, ra); 2021 } 2022 2023 void Mov(Condition cond, Register rd, const Operand& operand) { 2024 VIXL_ASSERT(allow_macro_instructions_); 2025 VIXL_ASSERT(OutsideITBlock()); 2026 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2027 bool can_use_it = 2028 // MOV<c>{<q>} <Rd>, #<imm8> ; T1 2029 (operand.IsImmediate() && rd.IsLow() && 2030 (operand.GetImmediate() <= 255)) || 2031 // MOV{<c>}{<q>} <Rd>, <Rm> ; T1 2032 (operand.IsPlainRegister() && !rd.IsPC() && 2033 !operand.GetBaseRegister().IsPC()) || 2034 // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} ; T2 2035 (operand.IsImmediateShiftedRegister() && rd.IsLow() && 2036 operand.GetBaseRegister().IsLow() && 2037 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) || 2038 operand.GetShift().Is(ASR))) || 2039 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 2040 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 2041 // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 2042 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 2043 (operand.IsRegisterShiftedRegister() && 2044 rd.Is(operand.GetBaseRegister()) && rd.IsLow() && 2045 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) || 2046 operand.GetShift().Is(ASR) || operand.GetShift().Is(ROR)) && 2047 operand.GetShiftRegister().IsLow()); 2048 ITScope it_scope(this, &cond, can_use_it); 2049 mov(cond, rd, operand); 2050 } 2051 void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); } 2052 void Mov(FlagsUpdate flags, 2053 Condition cond, 2054 Register rd, 2055 const Operand& operand) { 2056 switch (flags) { 2057 case LeaveFlags: 2058 Mov(cond, rd, operand); 2059 break; 2060 case SetFlags: 2061 Movs(cond, rd, operand); 2062 break; 2063 case DontCare: 2064 bool can_be_16bit_encoded = 2065 IsUsingT32() && cond.Is(al) && 2066 ((operand.IsImmediateShiftedRegister() && rd.IsLow() && 2067 operand.GetBaseRegister().IsLow() && 2068 (operand.GetShiftAmount() < 32) && 2069 (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() || 2070 operand.GetShift().IsASR())) || 2071 (operand.IsRegisterShiftedRegister() && rd.IsLow() && 2072 operand.GetBaseRegister().Is(rd) && 2073 operand.GetShiftRegister().IsLow() && 2074 (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() || 2075 operand.GetShift().IsASR() || operand.GetShift().IsROR())) || 2076 (operand.IsImmediate() && rd.IsLow() && 2077 (operand.GetImmediate() < 256))); 2078 if (can_be_16bit_encoded) { 2079 Movs(cond, rd, operand); 2080 } else { 2081 Mov(cond, rd, operand); 2082 } 2083 break; 2084 } 2085 } 2086 void Mov(FlagsUpdate flags, Register rd, const Operand& operand) { 2087 Mov(flags, al, rd, operand); 2088 } 2089 2090 void Movs(Condition cond, Register rd, const Operand& operand) { 2091 VIXL_ASSERT(allow_macro_instructions_); 2092 VIXL_ASSERT(OutsideITBlock()); 2093 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2094 ITScope it_scope(this, &cond); 2095 movs(cond, rd, operand); 2096 } 2097 void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); } 2098 2099 void Movt(Condition cond, Register rd, const Operand& operand) { 2100 VIXL_ASSERT(allow_macro_instructions_); 2101 VIXL_ASSERT(OutsideITBlock()); 2102 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2103 ITScope it_scope(this, &cond); 2104 movt(cond, rd, operand); 2105 } 2106 void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); } 2107 2108 void Movw(Condition cond, Register rd, const Operand& operand) { 2109 VIXL_ASSERT(allow_macro_instructions_); 2110 VIXL_ASSERT(OutsideITBlock()); 2111 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2112 ITScope it_scope(this, &cond); 2113 movw(cond, rd, operand); 2114 } 2115 void Movw(Register rd, const Operand& operand) { Movw(al, rd, operand); } 2116 2117 void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) { 2118 VIXL_ASSERT(allow_macro_instructions_); 2119 VIXL_ASSERT(OutsideITBlock()); 2120 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2121 ITScope it_scope(this, &cond); 2122 mrs(cond, rd, spec_reg); 2123 } 2124 void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); } 2125 2126 void Msr(Condition cond, 2127 MaskedSpecialRegister spec_reg, 2128 const Operand& operand) { 2129 VIXL_ASSERT(allow_macro_instructions_); 2130 VIXL_ASSERT(OutsideITBlock()); 2131 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2132 ITScope it_scope(this, &cond); 2133 msr(cond, spec_reg, operand); 2134 } 2135 void Msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2136 Msr(al, spec_reg, operand); 2137 } 2138 2139 void Mul(Condition cond, Register rd, Register rn, Register rm) { 2140 VIXL_ASSERT(allow_macro_instructions_); 2141 VIXL_ASSERT(OutsideITBlock()); 2142 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2143 bool can_use_it = 2144 // MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>} ; T1 2145 rd.Is(rm) && rn.IsLow() && rm.IsLow(); 2146 ITScope it_scope(this, &cond, can_use_it); 2147 mul(cond, rd, rn, rm); 2148 } 2149 void Mul(Register rd, Register rn, Register rm) { Mul(al, rd, rn, rm); } 2150 void Mul(FlagsUpdate flags, 2151 Condition cond, 2152 Register rd, 2153 Register rn, 2154 Register rm) { 2155 switch (flags) { 2156 case LeaveFlags: 2157 Mul(cond, rd, rn, rm); 2158 break; 2159 case SetFlags: 2160 Muls(cond, rd, rn, rm); 2161 break; 2162 case DontCare: 2163 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2164 rn.IsLow() && rm.Is(rd); 2165 if (can_be_16bit_encoded) { 2166 Muls(cond, rd, rn, rm); 2167 } else { 2168 Mul(cond, rd, rn, rm); 2169 } 2170 break; 2171 } 2172 } 2173 void Mul(FlagsUpdate flags, Register rd, Register rn, Register rm) { 2174 Mul(flags, al, rd, rn, rm); 2175 } 2176 2177 void Muls(Condition cond, Register rd, Register rn, Register rm) { 2178 VIXL_ASSERT(allow_macro_instructions_); 2179 VIXL_ASSERT(OutsideITBlock()); 2180 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2181 ITScope it_scope(this, &cond); 2182 muls(cond, rd, rn, rm); 2183 } 2184 void Muls(Register rd, Register rn, Register rm) { Muls(al, rd, rn, rm); } 2185 2186 void Mvn(Condition cond, Register rd, const Operand& operand) { 2187 VIXL_ASSERT(allow_macro_instructions_); 2188 VIXL_ASSERT(OutsideITBlock()); 2189 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2190 bool can_use_it = 2191 // MVN<c>{<q>} <Rd>, <Rm> ; T1 2192 operand.IsPlainRegister() && rd.IsLow() && 2193 operand.GetBaseRegister().IsLow(); 2194 ITScope it_scope(this, &cond, can_use_it); 2195 mvn(cond, rd, operand); 2196 } 2197 void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); } 2198 void Mvn(FlagsUpdate flags, 2199 Condition cond, 2200 Register rd, 2201 const Operand& operand) { 2202 switch (flags) { 2203 case LeaveFlags: 2204 Mvn(cond, rd, operand); 2205 break; 2206 case SetFlags: 2207 Mvns(cond, rd, operand); 2208 break; 2209 case DontCare: 2210 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2211 operand.IsPlainRegister() && 2212 operand.GetBaseRegister().IsLow(); 2213 if (can_be_16bit_encoded) { 2214 Mvns(cond, rd, operand); 2215 } else { 2216 Mvn(cond, rd, operand); 2217 } 2218 break; 2219 } 2220 } 2221 void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) { 2222 Mvn(flags, al, rd, operand); 2223 } 2224 2225 void Mvns(Condition cond, Register rd, const Operand& operand) { 2226 VIXL_ASSERT(allow_macro_instructions_); 2227 VIXL_ASSERT(OutsideITBlock()); 2228 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2229 ITScope it_scope(this, &cond); 2230 mvns(cond, rd, operand); 2231 } 2232 void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); } 2233 2234 void Nop(Condition cond) { 2235 VIXL_ASSERT(allow_macro_instructions_); 2236 VIXL_ASSERT(OutsideITBlock()); 2237 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2238 ITScope it_scope(this, &cond); 2239 nop(cond); 2240 } 2241 void Nop() { Nop(al); } 2242 2243 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { 2244 VIXL_ASSERT(allow_macro_instructions_); 2245 VIXL_ASSERT(OutsideITBlock()); 2246 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2247 ITScope it_scope(this, &cond); 2248 orn(cond, rd, rn, operand); 2249 } 2250 void Orn(Register rd, Register rn, const Operand& operand) { 2251 Orn(al, rd, rn, operand); 2252 } 2253 void Orn(FlagsUpdate flags, 2254 Condition cond, 2255 Register rd, 2256 Register rn, 2257 const Operand& operand) { 2258 switch (flags) { 2259 case LeaveFlags: 2260 Orn(cond, rd, rn, operand); 2261 break; 2262 case SetFlags: 2263 Orns(cond, rd, rn, operand); 2264 break; 2265 case DontCare: 2266 Orn(cond, rd, rn, operand); 2267 break; 2268 } 2269 } 2270 void Orn(FlagsUpdate flags, 2271 Register rd, 2272 Register rn, 2273 const Operand& operand) { 2274 Orn(flags, al, rd, rn, operand); 2275 } 2276 2277 void Orns(Condition cond, Register rd, Register rn, const Operand& operand) { 2278 VIXL_ASSERT(allow_macro_instructions_); 2279 VIXL_ASSERT(OutsideITBlock()); 2280 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2281 ITScope it_scope(this, &cond); 2282 orns(cond, rd, rn, operand); 2283 } 2284 void Orns(Register rd, Register rn, const Operand& operand) { 2285 Orns(al, rd, rn, operand); 2286 } 2287 2288 void Orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2289 VIXL_ASSERT(allow_macro_instructions_); 2290 VIXL_ASSERT(OutsideITBlock()); 2291 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2292 bool can_use_it = 2293 // ORR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 2294 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 2295 operand.GetBaseRegister().IsLow(); 2296 ITScope it_scope(this, &cond, can_use_it); 2297 orr(cond, rd, rn, operand); 2298 } 2299 void Orr(Register rd, Register rn, const Operand& operand) { 2300 Orr(al, rd, rn, operand); 2301 } 2302 void Orr(FlagsUpdate flags, 2303 Condition cond, 2304 Register rd, 2305 Register rn, 2306 const Operand& operand) { 2307 switch (flags) { 2308 case LeaveFlags: 2309 Orr(cond, rd, rn, operand); 2310 break; 2311 case SetFlags: 2312 Orrs(cond, rd, rn, operand); 2313 break; 2314 case DontCare: 2315 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2316 rn.Is(rd) && operand.IsPlainRegister() && 2317 operand.GetBaseRegister().IsLow(); 2318 if (can_be_16bit_encoded) { 2319 Orrs(cond, rd, rn, operand); 2320 } else { 2321 Orr(cond, rd, rn, operand); 2322 } 2323 break; 2324 } 2325 } 2326 void Orr(FlagsUpdate flags, 2327 Register rd, 2328 Register rn, 2329 const Operand& operand) { 2330 Orr(flags, al, rd, rn, operand); 2331 } 2332 2333 void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2334 VIXL_ASSERT(allow_macro_instructions_); 2335 VIXL_ASSERT(OutsideITBlock()); 2336 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2337 ITScope it_scope(this, &cond); 2338 orrs(cond, rd, rn, operand); 2339 } 2340 void Orrs(Register rd, Register rn, const Operand& operand) { 2341 Orrs(al, rd, rn, operand); 2342 } 2343 2344 void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) { 2345 VIXL_ASSERT(allow_macro_instructions_); 2346 VIXL_ASSERT(OutsideITBlock()); 2347 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2348 ITScope it_scope(this, &cond); 2349 pkhbt(cond, rd, rn, operand); 2350 } 2351 void Pkhbt(Register rd, Register rn, const Operand& operand) { 2352 Pkhbt(al, rd, rn, operand); 2353 } 2354 2355 void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) { 2356 VIXL_ASSERT(allow_macro_instructions_); 2357 VIXL_ASSERT(OutsideITBlock()); 2358 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2359 ITScope it_scope(this, &cond); 2360 pkhtb(cond, rd, rn, operand); 2361 } 2362 void Pkhtb(Register rd, Register rn, const Operand& operand) { 2363 Pkhtb(al, rd, rn, operand); 2364 } 2365 2366 void Pld(Condition cond, Label* label) { 2367 VIXL_ASSERT(allow_macro_instructions_); 2368 VIXL_ASSERT(OutsideITBlock()); 2369 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2370 ITScope it_scope(this, &cond); 2371 pld(cond, label); 2372 } 2373 void Pld(Label* label) { Pld(al, label); } 2374 2375 void Pld(Condition cond, const MemOperand& operand) { 2376 VIXL_ASSERT(allow_macro_instructions_); 2377 VIXL_ASSERT(OutsideITBlock()); 2378 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2379 ITScope it_scope(this, &cond); 2380 pld(cond, operand); 2381 } 2382 void Pld(const MemOperand& operand) { Pld(al, operand); } 2383 2384 void Pldw(Condition cond, const MemOperand& operand) { 2385 VIXL_ASSERT(allow_macro_instructions_); 2386 VIXL_ASSERT(OutsideITBlock()); 2387 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2388 ITScope it_scope(this, &cond); 2389 pldw(cond, operand); 2390 } 2391 void Pldw(const MemOperand& operand) { Pldw(al, operand); } 2392 2393 void Pli(Condition cond, const MemOperand& operand) { 2394 VIXL_ASSERT(allow_macro_instructions_); 2395 VIXL_ASSERT(OutsideITBlock()); 2396 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2397 ITScope it_scope(this, &cond); 2398 pli(cond, operand); 2399 } 2400 void Pli(const MemOperand& operand) { Pli(al, operand); } 2401 2402 void Pli(Condition cond, Label* label) { 2403 VIXL_ASSERT(allow_macro_instructions_); 2404 VIXL_ASSERT(OutsideITBlock()); 2405 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2406 ITScope it_scope(this, &cond); 2407 pli(cond, label); 2408 } 2409 void Pli(Label* label) { Pli(al, label); } 2410 2411 void Pop(Condition cond, RegisterList registers) { 2412 VIXL_ASSERT(allow_macro_instructions_); 2413 VIXL_ASSERT(OutsideITBlock()); 2414 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2415 ITScope it_scope(this, &cond); 2416 pop(cond, registers); 2417 } 2418 void Pop(RegisterList registers) { Pop(al, registers); } 2419 2420 void Pop(Condition cond, Register rt) { 2421 VIXL_ASSERT(allow_macro_instructions_); 2422 VIXL_ASSERT(OutsideITBlock()); 2423 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2424 ITScope it_scope(this, &cond); 2425 pop(cond, rt); 2426 } 2427 void Pop(Register rt) { Pop(al, rt); } 2428 2429 void Push(Condition cond, RegisterList registers) { 2430 VIXL_ASSERT(allow_macro_instructions_); 2431 VIXL_ASSERT(OutsideITBlock()); 2432 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2433 ITScope it_scope(this, &cond); 2434 push(cond, registers); 2435 } 2436 void Push(RegisterList registers) { Push(al, registers); } 2437 2438 void Push(Condition cond, Register rt) { 2439 VIXL_ASSERT(allow_macro_instructions_); 2440 VIXL_ASSERT(OutsideITBlock()); 2441 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2442 ITScope it_scope(this, &cond); 2443 push(cond, rt); 2444 } 2445 void Push(Register rt) { Push(al, rt); } 2446 2447 void Qadd(Condition cond, Register rd, Register rm, Register rn) { 2448 VIXL_ASSERT(allow_macro_instructions_); 2449 VIXL_ASSERT(OutsideITBlock()); 2450 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2451 ITScope it_scope(this, &cond); 2452 qadd(cond, rd, rm, rn); 2453 } 2454 void Qadd(Register rd, Register rm, Register rn) { Qadd(al, rd, rm, rn); } 2455 2456 void Qadd16(Condition cond, Register rd, Register rn, Register rm) { 2457 VIXL_ASSERT(allow_macro_instructions_); 2458 VIXL_ASSERT(OutsideITBlock()); 2459 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2460 ITScope it_scope(this, &cond); 2461 qadd16(cond, rd, rn, rm); 2462 } 2463 void Qadd16(Register rd, Register rn, Register rm) { Qadd16(al, rd, rn, rm); } 2464 2465 void Qadd8(Condition cond, Register rd, Register rn, Register rm) { 2466 VIXL_ASSERT(allow_macro_instructions_); 2467 VIXL_ASSERT(OutsideITBlock()); 2468 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2469 ITScope it_scope(this, &cond); 2470 qadd8(cond, rd, rn, rm); 2471 } 2472 void Qadd8(Register rd, Register rn, Register rm) { Qadd8(al, rd, rn, rm); } 2473 2474 void Qasx(Condition cond, Register rd, Register rn, Register rm) { 2475 VIXL_ASSERT(allow_macro_instructions_); 2476 VIXL_ASSERT(OutsideITBlock()); 2477 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2478 ITScope it_scope(this, &cond); 2479 qasx(cond, rd, rn, rm); 2480 } 2481 void Qasx(Register rd, Register rn, Register rm) { Qasx(al, rd, rn, rm); } 2482 2483 void Qdadd(Condition cond, Register rd, Register rm, Register rn) { 2484 VIXL_ASSERT(allow_macro_instructions_); 2485 VIXL_ASSERT(OutsideITBlock()); 2486 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2487 ITScope it_scope(this, &cond); 2488 qdadd(cond, rd, rm, rn); 2489 } 2490 void Qdadd(Register rd, Register rm, Register rn) { Qdadd(al, rd, rm, rn); } 2491 2492 void Qdsub(Condition cond, Register rd, Register rm, Register rn) { 2493 VIXL_ASSERT(allow_macro_instructions_); 2494 VIXL_ASSERT(OutsideITBlock()); 2495 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2496 ITScope it_scope(this, &cond); 2497 qdsub(cond, rd, rm, rn); 2498 } 2499 void Qdsub(Register rd, Register rm, Register rn) { Qdsub(al, rd, rm, rn); } 2500 2501 void Qsax(Condition cond, Register rd, Register rn, Register rm) { 2502 VIXL_ASSERT(allow_macro_instructions_); 2503 VIXL_ASSERT(OutsideITBlock()); 2504 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2505 ITScope it_scope(this, &cond); 2506 qsax(cond, rd, rn, rm); 2507 } 2508 void Qsax(Register rd, Register rn, Register rm) { Qsax(al, rd, rn, rm); } 2509 2510 void Qsub(Condition cond, Register rd, Register rm, Register rn) { 2511 VIXL_ASSERT(allow_macro_instructions_); 2512 VIXL_ASSERT(OutsideITBlock()); 2513 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2514 ITScope it_scope(this, &cond); 2515 qsub(cond, rd, rm, rn); 2516 } 2517 void Qsub(Register rd, Register rm, Register rn) { Qsub(al, rd, rm, rn); } 2518 2519 void Qsub16(Condition cond, Register rd, Register rn, Register rm) { 2520 VIXL_ASSERT(allow_macro_instructions_); 2521 VIXL_ASSERT(OutsideITBlock()); 2522 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2523 ITScope it_scope(this, &cond); 2524 qsub16(cond, rd, rn, rm); 2525 } 2526 void Qsub16(Register rd, Register rn, Register rm) { Qsub16(al, rd, rn, rm); } 2527 2528 void Qsub8(Condition cond, Register rd, Register rn, Register rm) { 2529 VIXL_ASSERT(allow_macro_instructions_); 2530 VIXL_ASSERT(OutsideITBlock()); 2531 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2532 ITScope it_scope(this, &cond); 2533 qsub8(cond, rd, rn, rm); 2534 } 2535 void Qsub8(Register rd, Register rn, Register rm) { Qsub8(al, rd, rn, rm); } 2536 2537 void Rbit(Condition cond, Register rd, Register rm) { 2538 VIXL_ASSERT(allow_macro_instructions_); 2539 VIXL_ASSERT(OutsideITBlock()); 2540 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2541 ITScope it_scope(this, &cond); 2542 rbit(cond, rd, rm); 2543 } 2544 void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); } 2545 2546 void Rev(Condition cond, Register rd, Register rm) { 2547 VIXL_ASSERT(allow_macro_instructions_); 2548 VIXL_ASSERT(OutsideITBlock()); 2549 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2550 ITScope it_scope(this, &cond); 2551 rev(cond, rd, rm); 2552 } 2553 void Rev(Register rd, Register rm) { Rev(al, rd, rm); } 2554 2555 void Rev16(Condition cond, Register rd, Register rm) { 2556 VIXL_ASSERT(allow_macro_instructions_); 2557 VIXL_ASSERT(OutsideITBlock()); 2558 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2559 ITScope it_scope(this, &cond); 2560 rev16(cond, rd, rm); 2561 } 2562 void Rev16(Register rd, Register rm) { Rev16(al, rd, rm); } 2563 2564 void Revsh(Condition cond, Register rd, Register rm) { 2565 VIXL_ASSERT(allow_macro_instructions_); 2566 VIXL_ASSERT(OutsideITBlock()); 2567 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2568 ITScope it_scope(this, &cond); 2569 revsh(cond, rd, rm); 2570 } 2571 void Revsh(Register rd, Register rm) { Revsh(al, rd, rm); } 2572 2573 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) { 2574 VIXL_ASSERT(allow_macro_instructions_); 2575 VIXL_ASSERT(OutsideITBlock()); 2576 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2577 bool can_use_it = 2578 // ROR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 2579 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2580 (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) || 2581 // ROR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 2582 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 2583 operand.GetBaseRegister().IsLow()); 2584 ITScope it_scope(this, &cond, can_use_it); 2585 ror(cond, rd, rm, operand); 2586 } 2587 void Ror(Register rd, Register rm, const Operand& operand) { 2588 Ror(al, rd, rm, operand); 2589 } 2590 void Ror(FlagsUpdate flags, 2591 Condition cond, 2592 Register rd, 2593 Register rm, 2594 const Operand& operand) { 2595 switch (flags) { 2596 case LeaveFlags: 2597 Ror(cond, rd, rm, operand); 2598 break; 2599 case SetFlags: 2600 Rors(cond, rd, rm, operand); 2601 break; 2602 case DontCare: 2603 Ror(cond, rd, rm, operand); 2604 break; 2605 } 2606 } 2607 void Ror(FlagsUpdate flags, 2608 Register rd, 2609 Register rm, 2610 const Operand& operand) { 2611 Ror(flags, al, rd, rm, operand); 2612 } 2613 2614 void Rors(Condition cond, Register rd, Register rm, const Operand& operand) { 2615 VIXL_ASSERT(allow_macro_instructions_); 2616 VIXL_ASSERT(OutsideITBlock()); 2617 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2618 ITScope it_scope(this, &cond); 2619 rors(cond, rd, rm, operand); 2620 } 2621 void Rors(Register rd, Register rm, const Operand& operand) { 2622 Rors(al, rd, rm, operand); 2623 } 2624 2625 void Rrx(Condition cond, Register rd, Register rm) { 2626 VIXL_ASSERT(allow_macro_instructions_); 2627 VIXL_ASSERT(OutsideITBlock()); 2628 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2629 ITScope it_scope(this, &cond); 2630 rrx(cond, rd, rm); 2631 } 2632 void Rrx(Register rd, Register rm) { Rrx(al, rd, rm); } 2633 void Rrx(FlagsUpdate flags, Condition cond, Register rd, Register rm) { 2634 switch (flags) { 2635 case LeaveFlags: 2636 Rrx(cond, rd, rm); 2637 break; 2638 case SetFlags: 2639 Rrxs(cond, rd, rm); 2640 break; 2641 case DontCare: 2642 Rrx(cond, rd, rm); 2643 break; 2644 } 2645 } 2646 void Rrx(FlagsUpdate flags, Register rd, Register rm) { 2647 Rrx(flags, al, rd, rm); 2648 } 2649 2650 void Rrxs(Condition cond, Register rd, Register rm) { 2651 VIXL_ASSERT(allow_macro_instructions_); 2652 VIXL_ASSERT(OutsideITBlock()); 2653 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2654 ITScope it_scope(this, &cond); 2655 rrxs(cond, rd, rm); 2656 } 2657 void Rrxs(Register rd, Register rm) { Rrxs(al, rd, rm); } 2658 2659 void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 2660 VIXL_ASSERT(allow_macro_instructions_); 2661 VIXL_ASSERT(OutsideITBlock()); 2662 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2663 bool can_use_it = 2664 // RSB<c>{<q>} {<Rd>, }<Rn>, #0 ; T1 2665 operand.IsImmediate() && rd.IsLow() && rn.IsLow() && 2666 (operand.GetImmediate() == 0); 2667 ITScope it_scope(this, &cond, can_use_it); 2668 rsb(cond, rd, rn, operand); 2669 } 2670 void Rsb(Register rd, Register rn, const Operand& operand) { 2671 Rsb(al, rd, rn, operand); 2672 } 2673 void Rsb(FlagsUpdate flags, 2674 Condition cond, 2675 Register rd, 2676 Register rn, 2677 const Operand& operand) { 2678 switch (flags) { 2679 case LeaveFlags: 2680 Rsb(cond, rd, rn, operand); 2681 break; 2682 case SetFlags: 2683 Rsbs(cond, rd, rn, operand); 2684 break; 2685 case DontCare: 2686 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2687 rn.IsLow() && operand.IsImmediate() && 2688 (operand.GetImmediate() == 0); 2689 if (can_be_16bit_encoded) { 2690 Rsbs(cond, rd, rn, operand); 2691 } else { 2692 Rsb(cond, rd, rn, operand); 2693 } 2694 break; 2695 } 2696 } 2697 void Rsb(FlagsUpdate flags, 2698 Register rd, 2699 Register rn, 2700 const Operand& operand) { 2701 Rsb(flags, al, rd, rn, operand); 2702 } 2703 2704 void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 2705 VIXL_ASSERT(allow_macro_instructions_); 2706 VIXL_ASSERT(OutsideITBlock()); 2707 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2708 ITScope it_scope(this, &cond); 2709 rsbs(cond, rd, rn, operand); 2710 } 2711 void Rsbs(Register rd, Register rn, const Operand& operand) { 2712 Rsbs(al, rd, rn, operand); 2713 } 2714 2715 void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) { 2716 VIXL_ASSERT(allow_macro_instructions_); 2717 VIXL_ASSERT(OutsideITBlock()); 2718 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2719 ITScope it_scope(this, &cond); 2720 rsc(cond, rd, rn, operand); 2721 } 2722 void Rsc(Register rd, Register rn, const Operand& operand) { 2723 Rsc(al, rd, rn, operand); 2724 } 2725 void Rsc(FlagsUpdate flags, 2726 Condition cond, 2727 Register rd, 2728 Register rn, 2729 const Operand& operand) { 2730 switch (flags) { 2731 case LeaveFlags: 2732 Rsc(cond, rd, rn, operand); 2733 break; 2734 case SetFlags: 2735 Rscs(cond, rd, rn, operand); 2736 break; 2737 case DontCare: 2738 Rsc(cond, rd, rn, operand); 2739 break; 2740 } 2741 } 2742 void Rsc(FlagsUpdate flags, 2743 Register rd, 2744 Register rn, 2745 const Operand& operand) { 2746 Rsc(flags, al, rd, rn, operand); 2747 } 2748 2749 void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) { 2750 VIXL_ASSERT(allow_macro_instructions_); 2751 VIXL_ASSERT(OutsideITBlock()); 2752 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2753 ITScope it_scope(this, &cond); 2754 rscs(cond, rd, rn, operand); 2755 } 2756 void Rscs(Register rd, Register rn, const Operand& operand) { 2757 Rscs(al, rd, rn, operand); 2758 } 2759 2760 void Sadd16(Condition cond, Register rd, Register rn, Register rm) { 2761 VIXL_ASSERT(allow_macro_instructions_); 2762 VIXL_ASSERT(OutsideITBlock()); 2763 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2764 ITScope it_scope(this, &cond); 2765 sadd16(cond, rd, rn, rm); 2766 } 2767 void Sadd16(Register rd, Register rn, Register rm) { Sadd16(al, rd, rn, rm); } 2768 2769 void Sadd8(Condition cond, Register rd, Register rn, Register rm) { 2770 VIXL_ASSERT(allow_macro_instructions_); 2771 VIXL_ASSERT(OutsideITBlock()); 2772 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2773 ITScope it_scope(this, &cond); 2774 sadd8(cond, rd, rn, rm); 2775 } 2776 void Sadd8(Register rd, Register rn, Register rm) { Sadd8(al, rd, rn, rm); } 2777 2778 void Sasx(Condition cond, Register rd, Register rn, Register rm) { 2779 VIXL_ASSERT(allow_macro_instructions_); 2780 VIXL_ASSERT(OutsideITBlock()); 2781 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2782 ITScope it_scope(this, &cond); 2783 sasx(cond, rd, rn, rm); 2784 } 2785 void Sasx(Register rd, Register rn, Register rm) { Sasx(al, rd, rn, rm); } 2786 2787 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 2788 VIXL_ASSERT(allow_macro_instructions_); 2789 VIXL_ASSERT(OutsideITBlock()); 2790 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2791 bool can_use_it = 2792 // SBC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 2793 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && 2794 operand.GetBaseRegister().IsLow(); 2795 ITScope it_scope(this, &cond, can_use_it); 2796 sbc(cond, rd, rn, operand); 2797 } 2798 void Sbc(Register rd, Register rn, const Operand& operand) { 2799 Sbc(al, rd, rn, operand); 2800 } 2801 void Sbc(FlagsUpdate flags, 2802 Condition cond, 2803 Register rd, 2804 Register rn, 2805 const Operand& operand) { 2806 switch (flags) { 2807 case LeaveFlags: 2808 Sbc(cond, rd, rn, operand); 2809 break; 2810 case SetFlags: 2811 Sbcs(cond, rd, rn, operand); 2812 break; 2813 case DontCare: 2814 bool can_be_16bit_encoded = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2815 rn.Is(rd) && operand.IsPlainRegister() && 2816 operand.GetBaseRegister().IsLow(); 2817 if (can_be_16bit_encoded) { 2818 Sbcs(cond, rd, rn, operand); 2819 } else { 2820 Sbc(cond, rd, rn, operand); 2821 } 2822 break; 2823 } 2824 } 2825 void Sbc(FlagsUpdate flags, 2826 Register rd, 2827 Register rn, 2828 const Operand& operand) { 2829 Sbc(flags, al, rd, rn, operand); 2830 } 2831 2832 void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 2833 VIXL_ASSERT(allow_macro_instructions_); 2834 VIXL_ASSERT(OutsideITBlock()); 2835 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2836 ITScope it_scope(this, &cond); 2837 sbcs(cond, rd, rn, operand); 2838 } 2839 void Sbcs(Register rd, Register rn, const Operand& operand) { 2840 Sbcs(al, rd, rn, operand); 2841 } 2842 2843 void Sbfx(Condition cond, 2844 Register rd, 2845 Register rn, 2846 uint32_t lsb, 2847 const Operand& operand) { 2848 VIXL_ASSERT(allow_macro_instructions_); 2849 VIXL_ASSERT(OutsideITBlock()); 2850 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2851 ITScope it_scope(this, &cond); 2852 sbfx(cond, rd, rn, lsb, operand); 2853 } 2854 void Sbfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 2855 Sbfx(al, rd, rn, lsb, operand); 2856 } 2857 2858 void Sdiv(Condition cond, Register rd, Register rn, Register rm) { 2859 VIXL_ASSERT(allow_macro_instructions_); 2860 VIXL_ASSERT(OutsideITBlock()); 2861 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2862 ITScope it_scope(this, &cond); 2863 sdiv(cond, rd, rn, rm); 2864 } 2865 void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); } 2866 2867 void Sel(Condition cond, Register rd, Register rn, Register rm) { 2868 VIXL_ASSERT(allow_macro_instructions_); 2869 VIXL_ASSERT(OutsideITBlock()); 2870 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2871 ITScope it_scope(this, &cond); 2872 sel(cond, rd, rn, rm); 2873 } 2874 void Sel(Register rd, Register rn, Register rm) { Sel(al, rd, rn, rm); } 2875 2876 void Shadd16(Condition cond, Register rd, Register rn, Register rm) { 2877 VIXL_ASSERT(allow_macro_instructions_); 2878 VIXL_ASSERT(OutsideITBlock()); 2879 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2880 ITScope it_scope(this, &cond); 2881 shadd16(cond, rd, rn, rm); 2882 } 2883 void Shadd16(Register rd, Register rn, Register rm) { 2884 Shadd16(al, rd, rn, rm); 2885 } 2886 2887 void Shadd8(Condition cond, Register rd, Register rn, Register rm) { 2888 VIXL_ASSERT(allow_macro_instructions_); 2889 VIXL_ASSERT(OutsideITBlock()); 2890 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2891 ITScope it_scope(this, &cond); 2892 shadd8(cond, rd, rn, rm); 2893 } 2894 void Shadd8(Register rd, Register rn, Register rm) { Shadd8(al, rd, rn, rm); } 2895 2896 void Shasx(Condition cond, Register rd, Register rn, Register rm) { 2897 VIXL_ASSERT(allow_macro_instructions_); 2898 VIXL_ASSERT(OutsideITBlock()); 2899 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2900 ITScope it_scope(this, &cond); 2901 shasx(cond, rd, rn, rm); 2902 } 2903 void Shasx(Register rd, Register rn, Register rm) { Shasx(al, rd, rn, rm); } 2904 2905 void Shsax(Condition cond, Register rd, Register rn, Register rm) { 2906 VIXL_ASSERT(allow_macro_instructions_); 2907 VIXL_ASSERT(OutsideITBlock()); 2908 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2909 ITScope it_scope(this, &cond); 2910 shsax(cond, rd, rn, rm); 2911 } 2912 void Shsax(Register rd, Register rn, Register rm) { Shsax(al, rd, rn, rm); } 2913 2914 void Shsub16(Condition cond, Register rd, Register rn, Register rm) { 2915 VIXL_ASSERT(allow_macro_instructions_); 2916 VIXL_ASSERT(OutsideITBlock()); 2917 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2918 ITScope it_scope(this, &cond); 2919 shsub16(cond, rd, rn, rm); 2920 } 2921 void Shsub16(Register rd, Register rn, Register rm) { 2922 Shsub16(al, rd, rn, rm); 2923 } 2924 2925 void Shsub8(Condition cond, Register rd, Register rn, Register rm) { 2926 VIXL_ASSERT(allow_macro_instructions_); 2927 VIXL_ASSERT(OutsideITBlock()); 2928 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2929 ITScope it_scope(this, &cond); 2930 shsub8(cond, rd, rn, rm); 2931 } 2932 void Shsub8(Register rd, Register rn, Register rm) { Shsub8(al, rd, rn, rm); } 2933 2934 void Smlabb( 2935 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2936 VIXL_ASSERT(allow_macro_instructions_); 2937 VIXL_ASSERT(OutsideITBlock()); 2938 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2939 ITScope it_scope(this, &cond); 2940 smlabb(cond, rd, rn, rm, ra); 2941 } 2942 void Smlabb(Register rd, Register rn, Register rm, Register ra) { 2943 Smlabb(al, rd, rn, rm, ra); 2944 } 2945 2946 void Smlabt( 2947 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2948 VIXL_ASSERT(allow_macro_instructions_); 2949 VIXL_ASSERT(OutsideITBlock()); 2950 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2951 ITScope it_scope(this, &cond); 2952 smlabt(cond, rd, rn, rm, ra); 2953 } 2954 void Smlabt(Register rd, Register rn, Register rm, Register ra) { 2955 Smlabt(al, rd, rn, rm, ra); 2956 } 2957 2958 void Smlad( 2959 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2960 VIXL_ASSERT(allow_macro_instructions_); 2961 VIXL_ASSERT(OutsideITBlock()); 2962 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2963 ITScope it_scope(this, &cond); 2964 smlad(cond, rd, rn, rm, ra); 2965 } 2966 void Smlad(Register rd, Register rn, Register rm, Register ra) { 2967 Smlad(al, rd, rn, rm, ra); 2968 } 2969 2970 void Smladx( 2971 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2972 VIXL_ASSERT(allow_macro_instructions_); 2973 VIXL_ASSERT(OutsideITBlock()); 2974 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2975 ITScope it_scope(this, &cond); 2976 smladx(cond, rd, rn, rm, ra); 2977 } 2978 void Smladx(Register rd, Register rn, Register rm, Register ra) { 2979 Smladx(al, rd, rn, rm, ra); 2980 } 2981 2982 void Smlal( 2983 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 2984 VIXL_ASSERT(allow_macro_instructions_); 2985 VIXL_ASSERT(OutsideITBlock()); 2986 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2987 ITScope it_scope(this, &cond); 2988 smlal(cond, rdlo, rdhi, rn, rm); 2989 } 2990 void Smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 2991 Smlal(al, rdlo, rdhi, rn, rm); 2992 } 2993 2994 void Smlalbb( 2995 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 2996 VIXL_ASSERT(allow_macro_instructions_); 2997 VIXL_ASSERT(OutsideITBlock()); 2998 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 2999 ITScope it_scope(this, &cond); 3000 smlalbb(cond, rdlo, rdhi, rn, rm); 3001 } 3002 void Smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 3003 Smlalbb(al, rdlo, rdhi, rn, rm); 3004 } 3005 3006 void Smlalbt( 3007 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3008 VIXL_ASSERT(allow_macro_instructions_); 3009 VIXL_ASSERT(OutsideITBlock()); 3010 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3011 ITScope it_scope(this, &cond); 3012 smlalbt(cond, rdlo, rdhi, rn, rm); 3013 } 3014 void Smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 3015 Smlalbt(al, rdlo, rdhi, rn, rm); 3016 } 3017 3018 void Smlald( 3019 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3020 VIXL_ASSERT(allow_macro_instructions_); 3021 VIXL_ASSERT(OutsideITBlock()); 3022 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3023 ITScope it_scope(this, &cond); 3024 smlald(cond, rdlo, rdhi, rn, rm); 3025 } 3026 void Smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 3027 Smlald(al, rdlo, rdhi, rn, rm); 3028 } 3029 3030 void Smlaldx( 3031 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3032 VIXL_ASSERT(allow_macro_instructions_); 3033 VIXL_ASSERT(OutsideITBlock()); 3034 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3035 ITScope it_scope(this, &cond); 3036 smlaldx(cond, rdlo, rdhi, rn, rm); 3037 } 3038 void Smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3039 Smlaldx(al, rdlo, rdhi, rn, rm); 3040 } 3041 3042 void Smlals( 3043 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3044 VIXL_ASSERT(allow_macro_instructions_); 3045 VIXL_ASSERT(OutsideITBlock()); 3046 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3047 ITScope it_scope(this, &cond); 3048 smlals(cond, rdlo, rdhi, rn, rm); 3049 } 3050 void Smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3051 Smlals(al, rdlo, rdhi, rn, rm); 3052 } 3053 3054 void Smlaltb( 3055 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3056 VIXL_ASSERT(allow_macro_instructions_); 3057 VIXL_ASSERT(OutsideITBlock()); 3058 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3059 ITScope it_scope(this, &cond); 3060 smlaltb(cond, rdlo, rdhi, rn, rm); 3061 } 3062 void Smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 3063 Smlaltb(al, rdlo, rdhi, rn, rm); 3064 } 3065 3066 void Smlaltt( 3067 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3068 VIXL_ASSERT(allow_macro_instructions_); 3069 VIXL_ASSERT(OutsideITBlock()); 3070 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3071 ITScope it_scope(this, &cond); 3072 smlaltt(cond, rdlo, rdhi, rn, rm); 3073 } 3074 void Smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 3075 Smlaltt(al, rdlo, rdhi, rn, rm); 3076 } 3077 3078 void Smlatb( 3079 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3080 VIXL_ASSERT(allow_macro_instructions_); 3081 VIXL_ASSERT(OutsideITBlock()); 3082 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3083 ITScope it_scope(this, &cond); 3084 smlatb(cond, rd, rn, rm, ra); 3085 } 3086 void Smlatb(Register rd, Register rn, Register rm, Register ra) { 3087 Smlatb(al, rd, rn, rm, ra); 3088 } 3089 3090 void Smlatt( 3091 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3092 VIXL_ASSERT(allow_macro_instructions_); 3093 VIXL_ASSERT(OutsideITBlock()); 3094 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3095 ITScope it_scope(this, &cond); 3096 smlatt(cond, rd, rn, rm, ra); 3097 } 3098 void Smlatt(Register rd, Register rn, Register rm, Register ra) { 3099 Smlatt(al, rd, rn, rm, ra); 3100 } 3101 3102 void Smlawb( 3103 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3104 VIXL_ASSERT(allow_macro_instructions_); 3105 VIXL_ASSERT(OutsideITBlock()); 3106 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3107 ITScope it_scope(this, &cond); 3108 smlawb(cond, rd, rn, rm, ra); 3109 } 3110 void Smlawb(Register rd, Register rn, Register rm, Register ra) { 3111 Smlawb(al, rd, rn, rm, ra); 3112 } 3113 3114 void Smlawt( 3115 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3116 VIXL_ASSERT(allow_macro_instructions_); 3117 VIXL_ASSERT(OutsideITBlock()); 3118 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3119 ITScope it_scope(this, &cond); 3120 smlawt(cond, rd, rn, rm, ra); 3121 } 3122 void Smlawt(Register rd, Register rn, Register rm, Register ra) { 3123 Smlawt(al, rd, rn, rm, ra); 3124 } 3125 3126 void Smlsd( 3127 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3128 VIXL_ASSERT(allow_macro_instructions_); 3129 VIXL_ASSERT(OutsideITBlock()); 3130 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3131 ITScope it_scope(this, &cond); 3132 smlsd(cond, rd, rn, rm, ra); 3133 } 3134 void Smlsd(Register rd, Register rn, Register rm, Register ra) { 3135 Smlsd(al, rd, rn, rm, ra); 3136 } 3137 3138 void Smlsdx( 3139 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3140 VIXL_ASSERT(allow_macro_instructions_); 3141 VIXL_ASSERT(OutsideITBlock()); 3142 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3143 ITScope it_scope(this, &cond); 3144 smlsdx(cond, rd, rn, rm, ra); 3145 } 3146 void Smlsdx(Register rd, Register rn, Register rm, Register ra) { 3147 Smlsdx(al, rd, rn, rm, ra); 3148 } 3149 3150 void Smlsld( 3151 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3152 VIXL_ASSERT(allow_macro_instructions_); 3153 VIXL_ASSERT(OutsideITBlock()); 3154 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3155 ITScope it_scope(this, &cond); 3156 smlsld(cond, rdlo, rdhi, rn, rm); 3157 } 3158 void Smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 3159 Smlsld(al, rdlo, rdhi, rn, rm); 3160 } 3161 3162 void Smlsldx( 3163 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3164 VIXL_ASSERT(allow_macro_instructions_); 3165 VIXL_ASSERT(OutsideITBlock()); 3166 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3167 ITScope it_scope(this, &cond); 3168 smlsldx(cond, rdlo, rdhi, rn, rm); 3169 } 3170 void Smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3171 Smlsldx(al, rdlo, rdhi, rn, rm); 3172 } 3173 3174 void Smmla( 3175 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3176 VIXL_ASSERT(allow_macro_instructions_); 3177 VIXL_ASSERT(OutsideITBlock()); 3178 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3179 ITScope it_scope(this, &cond); 3180 smmla(cond, rd, rn, rm, ra); 3181 } 3182 void Smmla(Register rd, Register rn, Register rm, Register ra) { 3183 Smmla(al, rd, rn, rm, ra); 3184 } 3185 3186 void Smmlar( 3187 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3188 VIXL_ASSERT(allow_macro_instructions_); 3189 VIXL_ASSERT(OutsideITBlock()); 3190 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3191 ITScope it_scope(this, &cond); 3192 smmlar(cond, rd, rn, rm, ra); 3193 } 3194 void Smmlar(Register rd, Register rn, Register rm, Register ra) { 3195 Smmlar(al, rd, rn, rm, ra); 3196 } 3197 3198 void Smmls( 3199 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3200 VIXL_ASSERT(allow_macro_instructions_); 3201 VIXL_ASSERT(OutsideITBlock()); 3202 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3203 ITScope it_scope(this, &cond); 3204 smmls(cond, rd, rn, rm, ra); 3205 } 3206 void Smmls(Register rd, Register rn, Register rm, Register ra) { 3207 Smmls(al, rd, rn, rm, ra); 3208 } 3209 3210 void Smmlsr( 3211 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3212 VIXL_ASSERT(allow_macro_instructions_); 3213 VIXL_ASSERT(OutsideITBlock()); 3214 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3215 ITScope it_scope(this, &cond); 3216 smmlsr(cond, rd, rn, rm, ra); 3217 } 3218 void Smmlsr(Register rd, Register rn, Register rm, Register ra) { 3219 Smmlsr(al, rd, rn, rm, ra); 3220 } 3221 3222 void Smmul(Condition cond, Register rd, Register rn, Register rm) { 3223 VIXL_ASSERT(allow_macro_instructions_); 3224 VIXL_ASSERT(OutsideITBlock()); 3225 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3226 ITScope it_scope(this, &cond); 3227 smmul(cond, rd, rn, rm); 3228 } 3229 void Smmul(Register rd, Register rn, Register rm) { Smmul(al, rd, rn, rm); } 3230 3231 void Smmulr(Condition cond, Register rd, Register rn, Register rm) { 3232 VIXL_ASSERT(allow_macro_instructions_); 3233 VIXL_ASSERT(OutsideITBlock()); 3234 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3235 ITScope it_scope(this, &cond); 3236 smmulr(cond, rd, rn, rm); 3237 } 3238 void Smmulr(Register rd, Register rn, Register rm) { Smmulr(al, rd, rn, rm); } 3239 3240 void Smuad(Condition cond, Register rd, Register rn, Register rm) { 3241 VIXL_ASSERT(allow_macro_instructions_); 3242 VIXL_ASSERT(OutsideITBlock()); 3243 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3244 ITScope it_scope(this, &cond); 3245 smuad(cond, rd, rn, rm); 3246 } 3247 void Smuad(Register rd, Register rn, Register rm) { Smuad(al, rd, rn, rm); } 3248 3249 void Smuadx(Condition cond, Register rd, Register rn, Register rm) { 3250 VIXL_ASSERT(allow_macro_instructions_); 3251 VIXL_ASSERT(OutsideITBlock()); 3252 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3253 ITScope it_scope(this, &cond); 3254 smuadx(cond, rd, rn, rm); 3255 } 3256 void Smuadx(Register rd, Register rn, Register rm) { Smuadx(al, rd, rn, rm); } 3257 3258 void Smulbb(Condition cond, Register rd, Register rn, Register rm) { 3259 VIXL_ASSERT(allow_macro_instructions_); 3260 VIXL_ASSERT(OutsideITBlock()); 3261 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3262 ITScope it_scope(this, &cond); 3263 smulbb(cond, rd, rn, rm); 3264 } 3265 void Smulbb(Register rd, Register rn, Register rm) { Smulbb(al, rd, rn, rm); } 3266 3267 void Smulbt(Condition cond, Register rd, Register rn, Register rm) { 3268 VIXL_ASSERT(allow_macro_instructions_); 3269 VIXL_ASSERT(OutsideITBlock()); 3270 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3271 ITScope it_scope(this, &cond); 3272 smulbt(cond, rd, rn, rm); 3273 } 3274 void Smulbt(Register rd, Register rn, Register rm) { Smulbt(al, rd, rn, rm); } 3275 3276 void Smull( 3277 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3278 VIXL_ASSERT(allow_macro_instructions_); 3279 VIXL_ASSERT(OutsideITBlock()); 3280 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3281 ITScope it_scope(this, &cond); 3282 smull(cond, rdlo, rdhi, rn, rm); 3283 } 3284 void Smull(Register rdlo, Register rdhi, Register rn, Register rm) { 3285 Smull(al, rdlo, rdhi, rn, rm); 3286 } 3287 void Smull(FlagsUpdate flags, 3288 Condition cond, 3289 Register rdlo, 3290 Register rdhi, 3291 Register rn, 3292 Register rm) { 3293 switch (flags) { 3294 case LeaveFlags: 3295 Smull(cond, rdlo, rdhi, rn, rm); 3296 break; 3297 case SetFlags: 3298 Smulls(cond, rdlo, rdhi, rn, rm); 3299 break; 3300 case DontCare: 3301 Smull(cond, rdlo, rdhi, rn, rm); 3302 break; 3303 } 3304 } 3305 void Smull(FlagsUpdate flags, 3306 Register rdlo, 3307 Register rdhi, 3308 Register rn, 3309 Register rm) { 3310 Smull(flags, al, rdlo, rdhi, rn, rm); 3311 } 3312 3313 void Smulls( 3314 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3315 VIXL_ASSERT(allow_macro_instructions_); 3316 VIXL_ASSERT(OutsideITBlock()); 3317 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3318 ITScope it_scope(this, &cond); 3319 smulls(cond, rdlo, rdhi, rn, rm); 3320 } 3321 void Smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3322 Smulls(al, rdlo, rdhi, rn, rm); 3323 } 3324 3325 void Smultb(Condition cond, Register rd, Register rn, Register rm) { 3326 VIXL_ASSERT(allow_macro_instructions_); 3327 VIXL_ASSERT(OutsideITBlock()); 3328 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3329 ITScope it_scope(this, &cond); 3330 smultb(cond, rd, rn, rm); 3331 } 3332 void Smultb(Register rd, Register rn, Register rm) { Smultb(al, rd, rn, rm); } 3333 3334 void Smultt(Condition cond, Register rd, Register rn, Register rm) { 3335 VIXL_ASSERT(allow_macro_instructions_); 3336 VIXL_ASSERT(OutsideITBlock()); 3337 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3338 ITScope it_scope(this, &cond); 3339 smultt(cond, rd, rn, rm); 3340 } 3341 void Smultt(Register rd, Register rn, Register rm) { Smultt(al, rd, rn, rm); } 3342 3343 void Smulwb(Condition cond, Register rd, Register rn, Register rm) { 3344 VIXL_ASSERT(allow_macro_instructions_); 3345 VIXL_ASSERT(OutsideITBlock()); 3346 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3347 ITScope it_scope(this, &cond); 3348 smulwb(cond, rd, rn, rm); 3349 } 3350 void Smulwb(Register rd, Register rn, Register rm) { Smulwb(al, rd, rn, rm); } 3351 3352 void Smulwt(Condition cond, Register rd, Register rn, Register rm) { 3353 VIXL_ASSERT(allow_macro_instructions_); 3354 VIXL_ASSERT(OutsideITBlock()); 3355 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3356 ITScope it_scope(this, &cond); 3357 smulwt(cond, rd, rn, rm); 3358 } 3359 void Smulwt(Register rd, Register rn, Register rm) { Smulwt(al, rd, rn, rm); } 3360 3361 void Smusd(Condition cond, Register rd, Register rn, Register rm) { 3362 VIXL_ASSERT(allow_macro_instructions_); 3363 VIXL_ASSERT(OutsideITBlock()); 3364 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3365 ITScope it_scope(this, &cond); 3366 smusd(cond, rd, rn, rm); 3367 } 3368 void Smusd(Register rd, Register rn, Register rm) { Smusd(al, rd, rn, rm); } 3369 3370 void Smusdx(Condition cond, Register rd, Register rn, Register rm) { 3371 VIXL_ASSERT(allow_macro_instructions_); 3372 VIXL_ASSERT(OutsideITBlock()); 3373 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3374 ITScope it_scope(this, &cond); 3375 smusdx(cond, rd, rn, rm); 3376 } 3377 void Smusdx(Register rd, Register rn, Register rm) { Smusdx(al, rd, rn, rm); } 3378 3379 void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) { 3380 VIXL_ASSERT(allow_macro_instructions_); 3381 VIXL_ASSERT(OutsideITBlock()); 3382 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3383 ITScope it_scope(this, &cond); 3384 ssat(cond, rd, imm, operand); 3385 } 3386 void Ssat(Register rd, uint32_t imm, const Operand& operand) { 3387 Ssat(al, rd, imm, operand); 3388 } 3389 3390 void Ssat16(Condition cond, Register rd, uint32_t imm, Register rn) { 3391 VIXL_ASSERT(allow_macro_instructions_); 3392 VIXL_ASSERT(OutsideITBlock()); 3393 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3394 ITScope it_scope(this, &cond); 3395 ssat16(cond, rd, imm, rn); 3396 } 3397 void Ssat16(Register rd, uint32_t imm, Register rn) { 3398 Ssat16(al, rd, imm, rn); 3399 } 3400 3401 void Ssax(Condition cond, Register rd, Register rn, Register rm) { 3402 VIXL_ASSERT(allow_macro_instructions_); 3403 VIXL_ASSERT(OutsideITBlock()); 3404 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3405 ITScope it_scope(this, &cond); 3406 ssax(cond, rd, rn, rm); 3407 } 3408 void Ssax(Register rd, Register rn, Register rm) { Ssax(al, rd, rn, rm); } 3409 3410 void Ssub16(Condition cond, Register rd, Register rn, Register rm) { 3411 VIXL_ASSERT(allow_macro_instructions_); 3412 VIXL_ASSERT(OutsideITBlock()); 3413 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3414 ITScope it_scope(this, &cond); 3415 ssub16(cond, rd, rn, rm); 3416 } 3417 void Ssub16(Register rd, Register rn, Register rm) { Ssub16(al, rd, rn, rm); } 3418 3419 void Ssub8(Condition cond, Register rd, Register rn, Register rm) { 3420 VIXL_ASSERT(allow_macro_instructions_); 3421 VIXL_ASSERT(OutsideITBlock()); 3422 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3423 ITScope it_scope(this, &cond); 3424 ssub8(cond, rd, rn, rm); 3425 } 3426 void Ssub8(Register rd, Register rn, Register rm) { Ssub8(al, rd, rn, rm); } 3427 3428 void Stl(Condition cond, Register rt, const MemOperand& operand) { 3429 VIXL_ASSERT(allow_macro_instructions_); 3430 VIXL_ASSERT(OutsideITBlock()); 3431 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3432 ITScope it_scope(this, &cond); 3433 stl(cond, rt, operand); 3434 } 3435 void Stl(Register rt, const MemOperand& operand) { Stl(al, rt, operand); } 3436 3437 void Stlb(Condition cond, Register rt, const MemOperand& operand) { 3438 VIXL_ASSERT(allow_macro_instructions_); 3439 VIXL_ASSERT(OutsideITBlock()); 3440 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3441 ITScope it_scope(this, &cond); 3442 stlb(cond, rt, operand); 3443 } 3444 void Stlb(Register rt, const MemOperand& operand) { Stlb(al, rt, operand); } 3445 3446 void Stlex(Condition cond, 3447 Register rd, 3448 Register rt, 3449 const MemOperand& operand) { 3450 VIXL_ASSERT(allow_macro_instructions_); 3451 VIXL_ASSERT(OutsideITBlock()); 3452 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3453 ITScope it_scope(this, &cond); 3454 stlex(cond, rd, rt, operand); 3455 } 3456 void Stlex(Register rd, Register rt, const MemOperand& operand) { 3457 Stlex(al, rd, rt, operand); 3458 } 3459 3460 void Stlexb(Condition cond, 3461 Register rd, 3462 Register rt, 3463 const MemOperand& operand) { 3464 VIXL_ASSERT(allow_macro_instructions_); 3465 VIXL_ASSERT(OutsideITBlock()); 3466 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3467 ITScope it_scope(this, &cond); 3468 stlexb(cond, rd, rt, operand); 3469 } 3470 void Stlexb(Register rd, Register rt, const MemOperand& operand) { 3471 Stlexb(al, rd, rt, operand); 3472 } 3473 3474 void Stlexd(Condition cond, 3475 Register rd, 3476 Register rt, 3477 Register rt2, 3478 const MemOperand& operand) { 3479 VIXL_ASSERT(allow_macro_instructions_); 3480 VIXL_ASSERT(OutsideITBlock()); 3481 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3482 ITScope it_scope(this, &cond); 3483 stlexd(cond, rd, rt, rt2, operand); 3484 } 3485 void Stlexd(Register rd, 3486 Register rt, 3487 Register rt2, 3488 const MemOperand& operand) { 3489 Stlexd(al, rd, rt, rt2, operand); 3490 } 3491 3492 void Stlexh(Condition cond, 3493 Register rd, 3494 Register rt, 3495 const MemOperand& operand) { 3496 VIXL_ASSERT(allow_macro_instructions_); 3497 VIXL_ASSERT(OutsideITBlock()); 3498 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3499 ITScope it_scope(this, &cond); 3500 stlexh(cond, rd, rt, operand); 3501 } 3502 void Stlexh(Register rd, Register rt, const MemOperand& operand) { 3503 Stlexh(al, rd, rt, operand); 3504 } 3505 3506 void Stlh(Condition cond, Register rt, const MemOperand& operand) { 3507 VIXL_ASSERT(allow_macro_instructions_); 3508 VIXL_ASSERT(OutsideITBlock()); 3509 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3510 ITScope it_scope(this, &cond); 3511 stlh(cond, rt, operand); 3512 } 3513 void Stlh(Register rt, const MemOperand& operand) { Stlh(al, rt, operand); } 3514 3515 void Stm(Condition cond, 3516 Register rn, 3517 WriteBack write_back, 3518 RegisterList registers) { 3519 VIXL_ASSERT(allow_macro_instructions_); 3520 VIXL_ASSERT(OutsideITBlock()); 3521 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3522 ITScope it_scope(this, &cond); 3523 stm(cond, rn, write_back, registers); 3524 } 3525 void Stm(Register rn, WriteBack write_back, RegisterList registers) { 3526 Stm(al, rn, write_back, registers); 3527 } 3528 3529 void Stmda(Condition cond, 3530 Register rn, 3531 WriteBack write_back, 3532 RegisterList registers) { 3533 VIXL_ASSERT(allow_macro_instructions_); 3534 VIXL_ASSERT(OutsideITBlock()); 3535 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3536 ITScope it_scope(this, &cond); 3537 stmda(cond, rn, write_back, registers); 3538 } 3539 void Stmda(Register rn, WriteBack write_back, RegisterList registers) { 3540 Stmda(al, rn, write_back, registers); 3541 } 3542 3543 void Stmdb(Condition cond, 3544 Register rn, 3545 WriteBack write_back, 3546 RegisterList registers) { 3547 VIXL_ASSERT(allow_macro_instructions_); 3548 VIXL_ASSERT(OutsideITBlock()); 3549 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3550 ITScope it_scope(this, &cond); 3551 stmdb(cond, rn, write_back, registers); 3552 } 3553 void Stmdb(Register rn, WriteBack write_back, RegisterList registers) { 3554 Stmdb(al, rn, write_back, registers); 3555 } 3556 3557 void Stmea(Condition cond, 3558 Register rn, 3559 WriteBack write_back, 3560 RegisterList registers) { 3561 VIXL_ASSERT(allow_macro_instructions_); 3562 VIXL_ASSERT(OutsideITBlock()); 3563 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3564 ITScope it_scope(this, &cond); 3565 stmea(cond, rn, write_back, registers); 3566 } 3567 void Stmea(Register rn, WriteBack write_back, RegisterList registers) { 3568 Stmea(al, rn, write_back, registers); 3569 } 3570 3571 void Stmed(Condition cond, 3572 Register rn, 3573 WriteBack write_back, 3574 RegisterList registers) { 3575 VIXL_ASSERT(allow_macro_instructions_); 3576 VIXL_ASSERT(OutsideITBlock()); 3577 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3578 ITScope it_scope(this, &cond); 3579 stmed(cond, rn, write_back, registers); 3580 } 3581 void Stmed(Register rn, WriteBack write_back, RegisterList registers) { 3582 Stmed(al, rn, write_back, registers); 3583 } 3584 3585 void Stmfa(Condition cond, 3586 Register rn, 3587 WriteBack write_back, 3588 RegisterList registers) { 3589 VIXL_ASSERT(allow_macro_instructions_); 3590 VIXL_ASSERT(OutsideITBlock()); 3591 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3592 ITScope it_scope(this, &cond); 3593 stmfa(cond, rn, write_back, registers); 3594 } 3595 void Stmfa(Register rn, WriteBack write_back, RegisterList registers) { 3596 Stmfa(al, rn, write_back, registers); 3597 } 3598 3599 void Stmfd(Condition cond, 3600 Register rn, 3601 WriteBack write_back, 3602 RegisterList registers) { 3603 VIXL_ASSERT(allow_macro_instructions_); 3604 VIXL_ASSERT(OutsideITBlock()); 3605 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3606 ITScope it_scope(this, &cond); 3607 stmfd(cond, rn, write_back, registers); 3608 } 3609 void Stmfd(Register rn, WriteBack write_back, RegisterList registers) { 3610 Stmfd(al, rn, write_back, registers); 3611 } 3612 3613 void Stmib(Condition cond, 3614 Register rn, 3615 WriteBack write_back, 3616 RegisterList registers) { 3617 VIXL_ASSERT(allow_macro_instructions_); 3618 VIXL_ASSERT(OutsideITBlock()); 3619 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3620 ITScope it_scope(this, &cond); 3621 stmib(cond, rn, write_back, registers); 3622 } 3623 void Stmib(Register rn, WriteBack write_back, RegisterList registers) { 3624 Stmib(al, rn, write_back, registers); 3625 } 3626 3627 void Str(Condition cond, Register rt, const MemOperand& operand) { 3628 VIXL_ASSERT(allow_macro_instructions_); 3629 VIXL_ASSERT(OutsideITBlock()); 3630 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3631 bool can_use_it = 3632 // STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 3633 (operand.IsImmediate() && rt.IsLow() && 3634 operand.GetBaseRegister().IsLow() && 3635 operand.IsOffsetImmediateWithinRange(0, 124, 4) && 3636 (operand.GetAddrMode() == Offset)) || 3637 // STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2 3638 (operand.IsImmediate() && rt.IsLow() && 3639 operand.GetBaseRegister().IsSP() && 3640 operand.IsOffsetImmediateWithinRange(0, 1020, 4) && 3641 (operand.GetAddrMode() == Offset)) || 3642 // STR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 3643 (operand.IsPlainRegister() && rt.IsLow() && 3644 operand.GetBaseRegister().IsLow() && 3645 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 3646 (operand.GetAddrMode() == Offset)); 3647 ITScope it_scope(this, &cond, can_use_it); 3648 str(cond, rt, operand); 3649 } 3650 void Str(Register rt, const MemOperand& operand) { Str(al, rt, operand); } 3651 3652 void Strb(Condition cond, Register rt, const MemOperand& operand) { 3653 VIXL_ASSERT(allow_macro_instructions_); 3654 VIXL_ASSERT(OutsideITBlock()); 3655 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3656 bool can_use_it = 3657 // STRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 3658 (operand.IsImmediate() && rt.IsLow() && 3659 operand.GetBaseRegister().IsLow() && 3660 operand.IsOffsetImmediateWithinRange(0, 31) && 3661 (operand.GetAddrMode() == Offset)) || 3662 // STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 3663 (operand.IsPlainRegister() && rt.IsLow() && 3664 operand.GetBaseRegister().IsLow() && 3665 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 3666 (operand.GetAddrMode() == Offset)); 3667 ITScope it_scope(this, &cond, can_use_it); 3668 strb(cond, rt, operand); 3669 } 3670 void Strb(Register rt, const MemOperand& operand) { Strb(al, rt, operand); } 3671 3672 void Strd(Condition cond, 3673 Register rt, 3674 Register rt2, 3675 const MemOperand& operand) { 3676 VIXL_ASSERT(allow_macro_instructions_); 3677 VIXL_ASSERT(OutsideITBlock()); 3678 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3679 ITScope it_scope(this, &cond); 3680 strd(cond, rt, rt2, operand); 3681 } 3682 void Strd(Register rt, Register rt2, const MemOperand& operand) { 3683 Strd(al, rt, rt2, operand); 3684 } 3685 3686 void Strex(Condition cond, 3687 Register rd, 3688 Register rt, 3689 const MemOperand& operand) { 3690 VIXL_ASSERT(allow_macro_instructions_); 3691 VIXL_ASSERT(OutsideITBlock()); 3692 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3693 ITScope it_scope(this, &cond); 3694 strex(cond, rd, rt, operand); 3695 } 3696 void Strex(Register rd, Register rt, const MemOperand& operand) { 3697 Strex(al, rd, rt, operand); 3698 } 3699 3700 void Strexb(Condition cond, 3701 Register rd, 3702 Register rt, 3703 const MemOperand& operand) { 3704 VIXL_ASSERT(allow_macro_instructions_); 3705 VIXL_ASSERT(OutsideITBlock()); 3706 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3707 ITScope it_scope(this, &cond); 3708 strexb(cond, rd, rt, operand); 3709 } 3710 void Strexb(Register rd, Register rt, const MemOperand& operand) { 3711 Strexb(al, rd, rt, operand); 3712 } 3713 3714 void Strexd(Condition cond, 3715 Register rd, 3716 Register rt, 3717 Register rt2, 3718 const MemOperand& operand) { 3719 VIXL_ASSERT(allow_macro_instructions_); 3720 VIXL_ASSERT(OutsideITBlock()); 3721 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3722 ITScope it_scope(this, &cond); 3723 strexd(cond, rd, rt, rt2, operand); 3724 } 3725 void Strexd(Register rd, 3726 Register rt, 3727 Register rt2, 3728 const MemOperand& operand) { 3729 Strexd(al, rd, rt, rt2, operand); 3730 } 3731 3732 void Strexh(Condition cond, 3733 Register rd, 3734 Register rt, 3735 const MemOperand& operand) { 3736 VIXL_ASSERT(allow_macro_instructions_); 3737 VIXL_ASSERT(OutsideITBlock()); 3738 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3739 ITScope it_scope(this, &cond); 3740 strexh(cond, rd, rt, operand); 3741 } 3742 void Strexh(Register rd, Register rt, const MemOperand& operand) { 3743 Strexh(al, rd, rt, operand); 3744 } 3745 3746 void Strh(Condition cond, Register rt, const MemOperand& operand) { 3747 VIXL_ASSERT(allow_macro_instructions_); 3748 VIXL_ASSERT(OutsideITBlock()); 3749 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3750 bool can_use_it = 3751 // STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 3752 (operand.IsImmediate() && rt.IsLow() && 3753 operand.GetBaseRegister().IsLow() && 3754 operand.IsOffsetImmediateWithinRange(0, 62, 2) && 3755 (operand.GetAddrMode() == Offset)) || 3756 // STRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 3757 (operand.IsPlainRegister() && rt.IsLow() && 3758 operand.GetBaseRegister().IsLow() && 3759 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 3760 (operand.GetAddrMode() == Offset)); 3761 ITScope it_scope(this, &cond, can_use_it); 3762 strh(cond, rt, operand); 3763 } 3764 void Strh(Register rt, const MemOperand& operand) { Strh(al, rt, operand); } 3765 3766 void Sub(Condition cond, Register rd, Register rn, const Operand& operand) { 3767 VIXL_ASSERT(allow_macro_instructions_); 3768 VIXL_ASSERT(OutsideITBlock()); 3769 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3770 bool can_use_it = 3771 // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 3772 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() && 3773 rd.IsLow()) || 3774 // SUB<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2 3775 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 3776 rd.IsLow() && rn.Is(rd)) || 3777 // SUB<c>{<q>} <Rd>, <Rn>, <Rm> 3778 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 3779 operand.GetBaseRegister().IsLow()); 3780 ITScope it_scope(this, &cond, can_use_it); 3781 sub(cond, rd, rn, operand); 3782 } 3783 void Sub(Register rd, Register rn, const Operand& operand) { 3784 Sub(al, rd, rn, operand); 3785 } 3786 void Sub(FlagsUpdate flags, 3787 Condition cond, 3788 Register rd, 3789 Register rn, 3790 const Operand& operand) { 3791 switch (flags) { 3792 case LeaveFlags: 3793 Sub(cond, rd, rn, operand); 3794 break; 3795 case SetFlags: 3796 Subs(cond, rd, rn, operand); 3797 break; 3798 case DontCare: 3799 bool can_be_16bit_encoded = 3800 IsUsingT32() && cond.Is(al) && 3801 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 3802 operand.GetBaseRegister().IsLow()) || 3803 (operand.IsImmediate() && 3804 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) || 3805 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256))))); 3806 if (can_be_16bit_encoded) { 3807 Subs(cond, rd, rn, operand); 3808 } else { 3809 Sub(cond, rd, rn, operand); 3810 } 3811 break; 3812 } 3813 } 3814 void Sub(FlagsUpdate flags, 3815 Register rd, 3816 Register rn, 3817 const Operand& operand) { 3818 Sub(flags, al, rd, rn, operand); 3819 } 3820 3821 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) { 3822 VIXL_ASSERT(allow_macro_instructions_); 3823 VIXL_ASSERT(OutsideITBlock()); 3824 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3825 ITScope it_scope(this, &cond); 3826 subs(cond, rd, rn, operand); 3827 } 3828 void Subs(Register rd, Register rn, const Operand& operand) { 3829 Subs(al, rd, rn, operand); 3830 } 3831 3832 void Subw(Condition cond, Register rd, Register rn, const Operand& operand) { 3833 VIXL_ASSERT(allow_macro_instructions_); 3834 VIXL_ASSERT(OutsideITBlock()); 3835 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3836 ITScope it_scope(this, &cond); 3837 subw(cond, rd, rn, operand); 3838 } 3839 void Subw(Register rd, Register rn, const Operand& operand) { 3840 Subw(al, rd, rn, operand); 3841 } 3842 3843 void Svc(Condition cond, uint32_t imm) { 3844 VIXL_ASSERT(allow_macro_instructions_); 3845 VIXL_ASSERT(OutsideITBlock()); 3846 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3847 ITScope it_scope(this, &cond); 3848 svc(cond, imm); 3849 } 3850 void Svc(uint32_t imm) { Svc(al, imm); } 3851 3852 void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) { 3853 VIXL_ASSERT(allow_macro_instructions_); 3854 VIXL_ASSERT(OutsideITBlock()); 3855 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3856 ITScope it_scope(this, &cond); 3857 sxtab(cond, rd, rn, operand); 3858 } 3859 void Sxtab(Register rd, Register rn, const Operand& operand) { 3860 Sxtab(al, rd, rn, operand); 3861 } 3862 3863 void Sxtab16(Condition cond, 3864 Register rd, 3865 Register rn, 3866 const Operand& operand) { 3867 VIXL_ASSERT(allow_macro_instructions_); 3868 VIXL_ASSERT(OutsideITBlock()); 3869 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3870 ITScope it_scope(this, &cond); 3871 sxtab16(cond, rd, rn, operand); 3872 } 3873 void Sxtab16(Register rd, Register rn, const Operand& operand) { 3874 Sxtab16(al, rd, rn, operand); 3875 } 3876 3877 void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) { 3878 VIXL_ASSERT(allow_macro_instructions_); 3879 VIXL_ASSERT(OutsideITBlock()); 3880 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3881 ITScope it_scope(this, &cond); 3882 sxtah(cond, rd, rn, operand); 3883 } 3884 void Sxtah(Register rd, Register rn, const Operand& operand) { 3885 Sxtah(al, rd, rn, operand); 3886 } 3887 3888 void Sxtb(Condition cond, Register rd, const Operand& operand) { 3889 VIXL_ASSERT(allow_macro_instructions_); 3890 VIXL_ASSERT(OutsideITBlock()); 3891 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3892 ITScope it_scope(this, &cond); 3893 sxtb(cond, rd, operand); 3894 } 3895 void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); } 3896 3897 void Sxtb16(Condition cond, Register rd, const Operand& operand) { 3898 VIXL_ASSERT(allow_macro_instructions_); 3899 VIXL_ASSERT(OutsideITBlock()); 3900 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3901 ITScope it_scope(this, &cond); 3902 sxtb16(cond, rd, operand); 3903 } 3904 void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); } 3905 3906 void Sxth(Condition cond, Register rd, const Operand& operand) { 3907 VIXL_ASSERT(allow_macro_instructions_); 3908 VIXL_ASSERT(OutsideITBlock()); 3909 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3910 ITScope it_scope(this, &cond); 3911 sxth(cond, rd, operand); 3912 } 3913 void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); } 3914 3915 void Tbb(Condition cond, Register rn, Register rm) { 3916 VIXL_ASSERT(allow_macro_instructions_); 3917 VIXL_ASSERT(OutsideITBlock()); 3918 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3919 ITScope it_scope(this, &cond); 3920 tbb(cond, rn, rm); 3921 } 3922 void Tbb(Register rn, Register rm) { Tbb(al, rn, rm); } 3923 3924 void Tbh(Condition cond, Register rn, Register rm) { 3925 VIXL_ASSERT(allow_macro_instructions_); 3926 VIXL_ASSERT(OutsideITBlock()); 3927 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3928 ITScope it_scope(this, &cond); 3929 tbh(cond, rn, rm); 3930 } 3931 void Tbh(Register rn, Register rm) { Tbh(al, rn, rm); } 3932 3933 void Teq(Condition cond, Register rn, const Operand& operand) { 3934 VIXL_ASSERT(allow_macro_instructions_); 3935 VIXL_ASSERT(OutsideITBlock()); 3936 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3937 ITScope it_scope(this, &cond); 3938 teq(cond, rn, operand); 3939 } 3940 void Teq(Register rn, const Operand& operand) { Teq(al, rn, operand); } 3941 3942 void Tst(Condition cond, Register rn, const Operand& operand) { 3943 VIXL_ASSERT(allow_macro_instructions_); 3944 VIXL_ASSERT(OutsideITBlock()); 3945 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3946 bool can_use_it = 3947 // TST{<c>}{<q>} <Rn>, <Rm> ; T1 3948 operand.IsPlainRegister() && rn.IsLow() && 3949 operand.GetBaseRegister().IsLow(); 3950 ITScope it_scope(this, &cond, can_use_it); 3951 tst(cond, rn, operand); 3952 } 3953 void Tst(Register rn, const Operand& operand) { Tst(al, rn, operand); } 3954 3955 void Uadd16(Condition cond, Register rd, Register rn, Register rm) { 3956 VIXL_ASSERT(allow_macro_instructions_); 3957 VIXL_ASSERT(OutsideITBlock()); 3958 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3959 ITScope it_scope(this, &cond); 3960 uadd16(cond, rd, rn, rm); 3961 } 3962 void Uadd16(Register rd, Register rn, Register rm) { Uadd16(al, rd, rn, rm); } 3963 3964 void Uadd8(Condition cond, Register rd, Register rn, Register rm) { 3965 VIXL_ASSERT(allow_macro_instructions_); 3966 VIXL_ASSERT(OutsideITBlock()); 3967 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3968 ITScope it_scope(this, &cond); 3969 uadd8(cond, rd, rn, rm); 3970 } 3971 void Uadd8(Register rd, Register rn, Register rm) { Uadd8(al, rd, rn, rm); } 3972 3973 void Uasx(Condition cond, Register rd, Register rn, Register rm) { 3974 VIXL_ASSERT(allow_macro_instructions_); 3975 VIXL_ASSERT(OutsideITBlock()); 3976 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3977 ITScope it_scope(this, &cond); 3978 uasx(cond, rd, rn, rm); 3979 } 3980 void Uasx(Register rd, Register rn, Register rm) { Uasx(al, rd, rn, rm); } 3981 3982 void Ubfx(Condition cond, 3983 Register rd, 3984 Register rn, 3985 uint32_t lsb, 3986 const Operand& operand) { 3987 VIXL_ASSERT(allow_macro_instructions_); 3988 VIXL_ASSERT(OutsideITBlock()); 3989 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 3990 ITScope it_scope(this, &cond); 3991 ubfx(cond, rd, rn, lsb, operand); 3992 } 3993 void Ubfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 3994 Ubfx(al, rd, rn, lsb, operand); 3995 } 3996 3997 void Udf(Condition cond, uint32_t imm) { 3998 VIXL_ASSERT(allow_macro_instructions_); 3999 VIXL_ASSERT(OutsideITBlock()); 4000 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4001 ITScope it_scope(this, &cond); 4002 udf(cond, imm); 4003 } 4004 void Udf(uint32_t imm) { Udf(al, imm); } 4005 4006 void Udiv(Condition cond, Register rd, Register rn, Register rm) { 4007 VIXL_ASSERT(allow_macro_instructions_); 4008 VIXL_ASSERT(OutsideITBlock()); 4009 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4010 ITScope it_scope(this, &cond); 4011 udiv(cond, rd, rn, rm); 4012 } 4013 void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); } 4014 4015 void Uhadd16(Condition cond, Register rd, Register rn, Register rm) { 4016 VIXL_ASSERT(allow_macro_instructions_); 4017 VIXL_ASSERT(OutsideITBlock()); 4018 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4019 ITScope it_scope(this, &cond); 4020 uhadd16(cond, rd, rn, rm); 4021 } 4022 void Uhadd16(Register rd, Register rn, Register rm) { 4023 Uhadd16(al, rd, rn, rm); 4024 } 4025 4026 void Uhadd8(Condition cond, Register rd, Register rn, Register rm) { 4027 VIXL_ASSERT(allow_macro_instructions_); 4028 VIXL_ASSERT(OutsideITBlock()); 4029 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4030 ITScope it_scope(this, &cond); 4031 uhadd8(cond, rd, rn, rm); 4032 } 4033 void Uhadd8(Register rd, Register rn, Register rm) { Uhadd8(al, rd, rn, rm); } 4034 4035 void Uhasx(Condition cond, Register rd, Register rn, Register rm) { 4036 VIXL_ASSERT(allow_macro_instructions_); 4037 VIXL_ASSERT(OutsideITBlock()); 4038 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4039 ITScope it_scope(this, &cond); 4040 uhasx(cond, rd, rn, rm); 4041 } 4042 void Uhasx(Register rd, Register rn, Register rm) { Uhasx(al, rd, rn, rm); } 4043 4044 void Uhsax(Condition cond, Register rd, Register rn, Register rm) { 4045 VIXL_ASSERT(allow_macro_instructions_); 4046 VIXL_ASSERT(OutsideITBlock()); 4047 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4048 ITScope it_scope(this, &cond); 4049 uhsax(cond, rd, rn, rm); 4050 } 4051 void Uhsax(Register rd, Register rn, Register rm) { Uhsax(al, rd, rn, rm); } 4052 4053 void Uhsub16(Condition cond, Register rd, Register rn, Register rm) { 4054 VIXL_ASSERT(allow_macro_instructions_); 4055 VIXL_ASSERT(OutsideITBlock()); 4056 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4057 ITScope it_scope(this, &cond); 4058 uhsub16(cond, rd, rn, rm); 4059 } 4060 void Uhsub16(Register rd, Register rn, Register rm) { 4061 Uhsub16(al, rd, rn, rm); 4062 } 4063 4064 void Uhsub8(Condition cond, Register rd, Register rn, Register rm) { 4065 VIXL_ASSERT(allow_macro_instructions_); 4066 VIXL_ASSERT(OutsideITBlock()); 4067 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4068 ITScope it_scope(this, &cond); 4069 uhsub8(cond, rd, rn, rm); 4070 } 4071 void Uhsub8(Register rd, Register rn, Register rm) { Uhsub8(al, rd, rn, rm); } 4072 4073 void Umaal( 4074 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4075 VIXL_ASSERT(allow_macro_instructions_); 4076 VIXL_ASSERT(OutsideITBlock()); 4077 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4078 ITScope it_scope(this, &cond); 4079 umaal(cond, rdlo, rdhi, rn, rm); 4080 } 4081 void Umaal(Register rdlo, Register rdhi, Register rn, Register rm) { 4082 Umaal(al, rdlo, rdhi, rn, rm); 4083 } 4084 4085 void Umlal( 4086 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4087 VIXL_ASSERT(allow_macro_instructions_); 4088 VIXL_ASSERT(OutsideITBlock()); 4089 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4090 ITScope it_scope(this, &cond); 4091 umlal(cond, rdlo, rdhi, rn, rm); 4092 } 4093 void Umlal(Register rdlo, Register rdhi, Register rn, Register rm) { 4094 Umlal(al, rdlo, rdhi, rn, rm); 4095 } 4096 void Umlal(FlagsUpdate flags, 4097 Condition cond, 4098 Register rdlo, 4099 Register rdhi, 4100 Register rn, 4101 Register rm) { 4102 switch (flags) { 4103 case LeaveFlags: 4104 Umlal(cond, rdlo, rdhi, rn, rm); 4105 break; 4106 case SetFlags: 4107 Umlals(cond, rdlo, rdhi, rn, rm); 4108 break; 4109 case DontCare: 4110 Umlal(cond, rdlo, rdhi, rn, rm); 4111 break; 4112 } 4113 } 4114 void Umlal(FlagsUpdate flags, 4115 Register rdlo, 4116 Register rdhi, 4117 Register rn, 4118 Register rm) { 4119 Umlal(flags, al, rdlo, rdhi, rn, rm); 4120 } 4121 4122 void Umlals( 4123 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4124 VIXL_ASSERT(allow_macro_instructions_); 4125 VIXL_ASSERT(OutsideITBlock()); 4126 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4127 ITScope it_scope(this, &cond); 4128 umlals(cond, rdlo, rdhi, rn, rm); 4129 } 4130 void Umlals(Register rdlo, Register rdhi, Register rn, Register rm) { 4131 Umlals(al, rdlo, rdhi, rn, rm); 4132 } 4133 4134 void Umull( 4135 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4136 VIXL_ASSERT(allow_macro_instructions_); 4137 VIXL_ASSERT(OutsideITBlock()); 4138 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4139 ITScope it_scope(this, &cond); 4140 umull(cond, rdlo, rdhi, rn, rm); 4141 } 4142 void Umull(Register rdlo, Register rdhi, Register rn, Register rm) { 4143 Umull(al, rdlo, rdhi, rn, rm); 4144 } 4145 void Umull(FlagsUpdate flags, 4146 Condition cond, 4147 Register rdlo, 4148 Register rdhi, 4149 Register rn, 4150 Register rm) { 4151 switch (flags) { 4152 case LeaveFlags: 4153 Umull(cond, rdlo, rdhi, rn, rm); 4154 break; 4155 case SetFlags: 4156 Umulls(cond, rdlo, rdhi, rn, rm); 4157 break; 4158 case DontCare: 4159 Umull(cond, rdlo, rdhi, rn, rm); 4160 break; 4161 } 4162 } 4163 void Umull(FlagsUpdate flags, 4164 Register rdlo, 4165 Register rdhi, 4166 Register rn, 4167 Register rm) { 4168 Umull(flags, al, rdlo, rdhi, rn, rm); 4169 } 4170 4171 void Umulls( 4172 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4173 VIXL_ASSERT(allow_macro_instructions_); 4174 VIXL_ASSERT(OutsideITBlock()); 4175 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4176 ITScope it_scope(this, &cond); 4177 umulls(cond, rdlo, rdhi, rn, rm); 4178 } 4179 void Umulls(Register rdlo, Register rdhi, Register rn, Register rm) { 4180 Umulls(al, rdlo, rdhi, rn, rm); 4181 } 4182 4183 void Uqadd16(Condition cond, Register rd, Register rn, Register rm) { 4184 VIXL_ASSERT(allow_macro_instructions_); 4185 VIXL_ASSERT(OutsideITBlock()); 4186 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4187 ITScope it_scope(this, &cond); 4188 uqadd16(cond, rd, rn, rm); 4189 } 4190 void Uqadd16(Register rd, Register rn, Register rm) { 4191 Uqadd16(al, rd, rn, rm); 4192 } 4193 4194 void Uqadd8(Condition cond, Register rd, Register rn, Register rm) { 4195 VIXL_ASSERT(allow_macro_instructions_); 4196 VIXL_ASSERT(OutsideITBlock()); 4197 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4198 ITScope it_scope(this, &cond); 4199 uqadd8(cond, rd, rn, rm); 4200 } 4201 void Uqadd8(Register rd, Register rn, Register rm) { Uqadd8(al, rd, rn, rm); } 4202 4203 void Uqasx(Condition cond, Register rd, Register rn, Register rm) { 4204 VIXL_ASSERT(allow_macro_instructions_); 4205 VIXL_ASSERT(OutsideITBlock()); 4206 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4207 ITScope it_scope(this, &cond); 4208 uqasx(cond, rd, rn, rm); 4209 } 4210 void Uqasx(Register rd, Register rn, Register rm) { Uqasx(al, rd, rn, rm); } 4211 4212 void Uqsax(Condition cond, Register rd, Register rn, Register rm) { 4213 VIXL_ASSERT(allow_macro_instructions_); 4214 VIXL_ASSERT(OutsideITBlock()); 4215 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4216 ITScope it_scope(this, &cond); 4217 uqsax(cond, rd, rn, rm); 4218 } 4219 void Uqsax(Register rd, Register rn, Register rm) { Uqsax(al, rd, rn, rm); } 4220 4221 void Uqsub16(Condition cond, Register rd, Register rn, Register rm) { 4222 VIXL_ASSERT(allow_macro_instructions_); 4223 VIXL_ASSERT(OutsideITBlock()); 4224 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4225 ITScope it_scope(this, &cond); 4226 uqsub16(cond, rd, rn, rm); 4227 } 4228 void Uqsub16(Register rd, Register rn, Register rm) { 4229 Uqsub16(al, rd, rn, rm); 4230 } 4231 4232 void Uqsub8(Condition cond, Register rd, Register rn, Register rm) { 4233 VIXL_ASSERT(allow_macro_instructions_); 4234 VIXL_ASSERT(OutsideITBlock()); 4235 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4236 ITScope it_scope(this, &cond); 4237 uqsub8(cond, rd, rn, rm); 4238 } 4239 void Uqsub8(Register rd, Register rn, Register rm) { Uqsub8(al, rd, rn, rm); } 4240 4241 void Usad8(Condition cond, Register rd, Register rn, Register rm) { 4242 VIXL_ASSERT(allow_macro_instructions_); 4243 VIXL_ASSERT(OutsideITBlock()); 4244 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4245 ITScope it_scope(this, &cond); 4246 usad8(cond, rd, rn, rm); 4247 } 4248 void Usad8(Register rd, Register rn, Register rm) { Usad8(al, rd, rn, rm); } 4249 4250 void Usada8( 4251 Condition cond, Register rd, Register rn, Register rm, Register ra) { 4252 VIXL_ASSERT(allow_macro_instructions_); 4253 VIXL_ASSERT(OutsideITBlock()); 4254 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4255 ITScope it_scope(this, &cond); 4256 usada8(cond, rd, rn, rm, ra); 4257 } 4258 void Usada8(Register rd, Register rn, Register rm, Register ra) { 4259 Usada8(al, rd, rn, rm, ra); 4260 } 4261 4262 void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) { 4263 VIXL_ASSERT(allow_macro_instructions_); 4264 VIXL_ASSERT(OutsideITBlock()); 4265 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4266 ITScope it_scope(this, &cond); 4267 usat(cond, rd, imm, operand); 4268 } 4269 void Usat(Register rd, uint32_t imm, const Operand& operand) { 4270 Usat(al, rd, imm, operand); 4271 } 4272 4273 void Usat16(Condition cond, Register rd, uint32_t imm, Register rn) { 4274 VIXL_ASSERT(allow_macro_instructions_); 4275 VIXL_ASSERT(OutsideITBlock()); 4276 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4277 ITScope it_scope(this, &cond); 4278 usat16(cond, rd, imm, rn); 4279 } 4280 void Usat16(Register rd, uint32_t imm, Register rn) { 4281 Usat16(al, rd, imm, rn); 4282 } 4283 4284 void Usax(Condition cond, Register rd, Register rn, Register rm) { 4285 VIXL_ASSERT(allow_macro_instructions_); 4286 VIXL_ASSERT(OutsideITBlock()); 4287 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4288 ITScope it_scope(this, &cond); 4289 usax(cond, rd, rn, rm); 4290 } 4291 void Usax(Register rd, Register rn, Register rm) { Usax(al, rd, rn, rm); } 4292 4293 void Usub16(Condition cond, Register rd, Register rn, Register rm) { 4294 VIXL_ASSERT(allow_macro_instructions_); 4295 VIXL_ASSERT(OutsideITBlock()); 4296 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4297 ITScope it_scope(this, &cond); 4298 usub16(cond, rd, rn, rm); 4299 } 4300 void Usub16(Register rd, Register rn, Register rm) { Usub16(al, rd, rn, rm); } 4301 4302 void Usub8(Condition cond, Register rd, Register rn, Register rm) { 4303 VIXL_ASSERT(allow_macro_instructions_); 4304 VIXL_ASSERT(OutsideITBlock()); 4305 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4306 ITScope it_scope(this, &cond); 4307 usub8(cond, rd, rn, rm); 4308 } 4309 void Usub8(Register rd, Register rn, Register rm) { Usub8(al, rd, rn, rm); } 4310 4311 void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) { 4312 VIXL_ASSERT(allow_macro_instructions_); 4313 VIXL_ASSERT(OutsideITBlock()); 4314 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4315 ITScope it_scope(this, &cond); 4316 uxtab(cond, rd, rn, operand); 4317 } 4318 void Uxtab(Register rd, Register rn, const Operand& operand) { 4319 Uxtab(al, rd, rn, operand); 4320 } 4321 4322 void Uxtab16(Condition cond, 4323 Register rd, 4324 Register rn, 4325 const Operand& operand) { 4326 VIXL_ASSERT(allow_macro_instructions_); 4327 VIXL_ASSERT(OutsideITBlock()); 4328 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4329 ITScope it_scope(this, &cond); 4330 uxtab16(cond, rd, rn, operand); 4331 } 4332 void Uxtab16(Register rd, Register rn, const Operand& operand) { 4333 Uxtab16(al, rd, rn, operand); 4334 } 4335 4336 void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) { 4337 VIXL_ASSERT(allow_macro_instructions_); 4338 VIXL_ASSERT(OutsideITBlock()); 4339 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4340 ITScope it_scope(this, &cond); 4341 uxtah(cond, rd, rn, operand); 4342 } 4343 void Uxtah(Register rd, Register rn, const Operand& operand) { 4344 Uxtah(al, rd, rn, operand); 4345 } 4346 4347 void Uxtb(Condition cond, Register rd, const Operand& operand) { 4348 VIXL_ASSERT(allow_macro_instructions_); 4349 VIXL_ASSERT(OutsideITBlock()); 4350 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4351 ITScope it_scope(this, &cond); 4352 uxtb(cond, rd, operand); 4353 } 4354 void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); } 4355 4356 void Uxtb16(Condition cond, Register rd, const Operand& operand) { 4357 VIXL_ASSERT(allow_macro_instructions_); 4358 VIXL_ASSERT(OutsideITBlock()); 4359 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4360 ITScope it_scope(this, &cond); 4361 uxtb16(cond, rd, operand); 4362 } 4363 void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); } 4364 4365 void Uxth(Condition cond, Register rd, const Operand& operand) { 4366 VIXL_ASSERT(allow_macro_instructions_); 4367 VIXL_ASSERT(OutsideITBlock()); 4368 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4369 ITScope it_scope(this, &cond); 4370 uxth(cond, rd, operand); 4371 } 4372 void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); } 4373 4374 void Vaba( 4375 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4376 VIXL_ASSERT(allow_macro_instructions_); 4377 VIXL_ASSERT(OutsideITBlock()); 4378 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4379 ITScope it_scope(this, &cond); 4380 vaba(cond, dt, rd, rn, rm); 4381 } 4382 void Vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4383 Vaba(al, dt, rd, rn, rm); 4384 } 4385 4386 void Vaba( 4387 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4388 VIXL_ASSERT(allow_macro_instructions_); 4389 VIXL_ASSERT(OutsideITBlock()); 4390 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4391 ITScope it_scope(this, &cond); 4392 vaba(cond, dt, rd, rn, rm); 4393 } 4394 void Vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4395 Vaba(al, dt, rd, rn, rm); 4396 } 4397 4398 void Vabal( 4399 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4400 VIXL_ASSERT(allow_macro_instructions_); 4401 VIXL_ASSERT(OutsideITBlock()); 4402 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4403 ITScope it_scope(this, &cond); 4404 vabal(cond, dt, rd, rn, rm); 4405 } 4406 void Vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4407 Vabal(al, dt, rd, rn, rm); 4408 } 4409 4410 void Vabd( 4411 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4412 VIXL_ASSERT(allow_macro_instructions_); 4413 VIXL_ASSERT(OutsideITBlock()); 4414 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4415 ITScope it_scope(this, &cond); 4416 vabd(cond, dt, rd, rn, rm); 4417 } 4418 void Vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4419 Vabd(al, dt, rd, rn, rm); 4420 } 4421 4422 void Vabd( 4423 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4424 VIXL_ASSERT(allow_macro_instructions_); 4425 VIXL_ASSERT(OutsideITBlock()); 4426 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4427 ITScope it_scope(this, &cond); 4428 vabd(cond, dt, rd, rn, rm); 4429 } 4430 void Vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4431 Vabd(al, dt, rd, rn, rm); 4432 } 4433 4434 void Vabdl( 4435 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4436 VIXL_ASSERT(allow_macro_instructions_); 4437 VIXL_ASSERT(OutsideITBlock()); 4438 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4439 ITScope it_scope(this, &cond); 4440 vabdl(cond, dt, rd, rn, rm); 4441 } 4442 void Vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4443 Vabdl(al, dt, rd, rn, rm); 4444 } 4445 4446 void Vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { 4447 VIXL_ASSERT(allow_macro_instructions_); 4448 VIXL_ASSERT(OutsideITBlock()); 4449 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4450 ITScope it_scope(this, &cond); 4451 vabs(cond, dt, rd, rm); 4452 } 4453 void Vabs(DataType dt, DRegister rd, DRegister rm) { Vabs(al, dt, rd, rm); } 4454 4455 void Vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { 4456 VIXL_ASSERT(allow_macro_instructions_); 4457 VIXL_ASSERT(OutsideITBlock()); 4458 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4459 ITScope it_scope(this, &cond); 4460 vabs(cond, dt, rd, rm); 4461 } 4462 void Vabs(DataType dt, QRegister rd, QRegister rm) { Vabs(al, dt, rd, rm); } 4463 4464 void Vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) { 4465 VIXL_ASSERT(allow_macro_instructions_); 4466 VIXL_ASSERT(OutsideITBlock()); 4467 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4468 ITScope it_scope(this, &cond); 4469 vabs(cond, dt, rd, rm); 4470 } 4471 void Vabs(DataType dt, SRegister rd, SRegister rm) { Vabs(al, dt, rd, rm); } 4472 4473 void Vacge( 4474 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4475 VIXL_ASSERT(allow_macro_instructions_); 4476 VIXL_ASSERT(OutsideITBlock()); 4477 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4478 ITScope it_scope(this, &cond); 4479 vacge(cond, dt, rd, rn, rm); 4480 } 4481 void Vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4482 Vacge(al, dt, rd, rn, rm); 4483 } 4484 4485 void Vacge( 4486 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4487 VIXL_ASSERT(allow_macro_instructions_); 4488 VIXL_ASSERT(OutsideITBlock()); 4489 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4490 ITScope it_scope(this, &cond); 4491 vacge(cond, dt, rd, rn, rm); 4492 } 4493 void Vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4494 Vacge(al, dt, rd, rn, rm); 4495 } 4496 4497 void Vacgt( 4498 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4499 VIXL_ASSERT(allow_macro_instructions_); 4500 VIXL_ASSERT(OutsideITBlock()); 4501 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4502 ITScope it_scope(this, &cond); 4503 vacgt(cond, dt, rd, rn, rm); 4504 } 4505 void Vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4506 Vacgt(al, dt, rd, rn, rm); 4507 } 4508 4509 void Vacgt( 4510 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4511 VIXL_ASSERT(allow_macro_instructions_); 4512 VIXL_ASSERT(OutsideITBlock()); 4513 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4514 ITScope it_scope(this, &cond); 4515 vacgt(cond, dt, rd, rn, rm); 4516 } 4517 void Vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4518 Vacgt(al, dt, rd, rn, rm); 4519 } 4520 4521 void Vacle( 4522 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4523 VIXL_ASSERT(allow_macro_instructions_); 4524 VIXL_ASSERT(OutsideITBlock()); 4525 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4526 ITScope it_scope(this, &cond); 4527 vacle(cond, dt, rd, rn, rm); 4528 } 4529 void Vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4530 Vacle(al, dt, rd, rn, rm); 4531 } 4532 4533 void Vacle( 4534 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4535 VIXL_ASSERT(allow_macro_instructions_); 4536 VIXL_ASSERT(OutsideITBlock()); 4537 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4538 ITScope it_scope(this, &cond); 4539 vacle(cond, dt, rd, rn, rm); 4540 } 4541 void Vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4542 Vacle(al, dt, rd, rn, rm); 4543 } 4544 4545 void Vaclt( 4546 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4547 VIXL_ASSERT(allow_macro_instructions_); 4548 VIXL_ASSERT(OutsideITBlock()); 4549 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4550 ITScope it_scope(this, &cond); 4551 vaclt(cond, dt, rd, rn, rm); 4552 } 4553 void Vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4554 Vaclt(al, dt, rd, rn, rm); 4555 } 4556 4557 void Vaclt( 4558 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4559 VIXL_ASSERT(allow_macro_instructions_); 4560 VIXL_ASSERT(OutsideITBlock()); 4561 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4562 ITScope it_scope(this, &cond); 4563 vaclt(cond, dt, rd, rn, rm); 4564 } 4565 void Vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4566 Vaclt(al, dt, rd, rn, rm); 4567 } 4568 4569 void Vadd( 4570 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4571 VIXL_ASSERT(allow_macro_instructions_); 4572 VIXL_ASSERT(OutsideITBlock()); 4573 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4574 ITScope it_scope(this, &cond); 4575 vadd(cond, dt, rd, rn, rm); 4576 } 4577 void Vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4578 Vadd(al, dt, rd, rn, rm); 4579 } 4580 4581 void Vadd( 4582 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4583 VIXL_ASSERT(allow_macro_instructions_); 4584 VIXL_ASSERT(OutsideITBlock()); 4585 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4586 ITScope it_scope(this, &cond); 4587 vadd(cond, dt, rd, rn, rm); 4588 } 4589 void Vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4590 Vadd(al, dt, rd, rn, rm); 4591 } 4592 4593 void Vadd( 4594 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4595 VIXL_ASSERT(allow_macro_instructions_); 4596 VIXL_ASSERT(OutsideITBlock()); 4597 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4598 ITScope it_scope(this, &cond); 4599 vadd(cond, dt, rd, rn, rm); 4600 } 4601 void Vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4602 Vadd(al, dt, rd, rn, rm); 4603 } 4604 4605 void Vaddhn( 4606 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 4607 VIXL_ASSERT(allow_macro_instructions_); 4608 VIXL_ASSERT(OutsideITBlock()); 4609 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4610 ITScope it_scope(this, &cond); 4611 vaddhn(cond, dt, rd, rn, rm); 4612 } 4613 void Vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 4614 Vaddhn(al, dt, rd, rn, rm); 4615 } 4616 4617 void Vaddl( 4618 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4619 VIXL_ASSERT(allow_macro_instructions_); 4620 VIXL_ASSERT(OutsideITBlock()); 4621 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4622 ITScope it_scope(this, &cond); 4623 vaddl(cond, dt, rd, rn, rm); 4624 } 4625 void Vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4626 Vaddl(al, dt, rd, rn, rm); 4627 } 4628 4629 void Vaddw( 4630 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { 4631 VIXL_ASSERT(allow_macro_instructions_); 4632 VIXL_ASSERT(OutsideITBlock()); 4633 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4634 ITScope it_scope(this, &cond); 4635 vaddw(cond, dt, rd, rn, rm); 4636 } 4637 void Vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 4638 Vaddw(al, dt, rd, rn, rm); 4639 } 4640 4641 void Vand(Condition cond, 4642 DataType dt, 4643 DRegister rd, 4644 DRegister rn, 4645 const DOperand& operand) { 4646 VIXL_ASSERT(allow_macro_instructions_); 4647 VIXL_ASSERT(OutsideITBlock()); 4648 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4649 ITScope it_scope(this, &cond); 4650 vand(cond, dt, rd, rn, operand); 4651 } 4652 void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 4653 Vand(al, dt, rd, rn, operand); 4654 } 4655 4656 void Vand(Condition cond, 4657 DataType dt, 4658 QRegister rd, 4659 QRegister rn, 4660 const QOperand& operand) { 4661 VIXL_ASSERT(allow_macro_instructions_); 4662 VIXL_ASSERT(OutsideITBlock()); 4663 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4664 ITScope it_scope(this, &cond); 4665 vand(cond, dt, rd, rn, operand); 4666 } 4667 void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 4668 Vand(al, dt, rd, rn, operand); 4669 } 4670 4671 void Vbic(Condition cond, 4672 DataType dt, 4673 DRegister rd, 4674 DRegister rn, 4675 const DOperand& operand) { 4676 VIXL_ASSERT(allow_macro_instructions_); 4677 VIXL_ASSERT(OutsideITBlock()); 4678 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4679 ITScope it_scope(this, &cond); 4680 vbic(cond, dt, rd, rn, operand); 4681 } 4682 void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 4683 Vbic(al, dt, rd, rn, operand); 4684 } 4685 4686 void Vbic(Condition cond, 4687 DataType dt, 4688 QRegister rd, 4689 QRegister rn, 4690 const QOperand& operand) { 4691 VIXL_ASSERT(allow_macro_instructions_); 4692 VIXL_ASSERT(OutsideITBlock()); 4693 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4694 ITScope it_scope(this, &cond); 4695 vbic(cond, dt, rd, rn, operand); 4696 } 4697 void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 4698 Vbic(al, dt, rd, rn, operand); 4699 } 4700 4701 void Vbif( 4702 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4703 VIXL_ASSERT(allow_macro_instructions_); 4704 VIXL_ASSERT(OutsideITBlock()); 4705 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4706 ITScope it_scope(this, &cond); 4707 vbif(cond, dt, rd, rn, rm); 4708 } 4709 void Vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4710 Vbif(al, dt, rd, rn, rm); 4711 } 4712 void Vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 4713 Vbif(cond, kDataTypeValueNone, rd, rn, rm); 4714 } 4715 void Vbif(DRegister rd, DRegister rn, DRegister rm) { 4716 Vbif(al, kDataTypeValueNone, rd, rn, rm); 4717 } 4718 4719 void Vbif( 4720 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4721 VIXL_ASSERT(allow_macro_instructions_); 4722 VIXL_ASSERT(OutsideITBlock()); 4723 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4724 ITScope it_scope(this, &cond); 4725 vbif(cond, dt, rd, rn, rm); 4726 } 4727 void Vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4728 Vbif(al, dt, rd, rn, rm); 4729 } 4730 void Vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 4731 Vbif(cond, kDataTypeValueNone, rd, rn, rm); 4732 } 4733 void Vbif(QRegister rd, QRegister rn, QRegister rm) { 4734 Vbif(al, kDataTypeValueNone, rd, rn, rm); 4735 } 4736 4737 void Vbit( 4738 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4739 VIXL_ASSERT(allow_macro_instructions_); 4740 VIXL_ASSERT(OutsideITBlock()); 4741 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4742 ITScope it_scope(this, &cond); 4743 vbit(cond, dt, rd, rn, rm); 4744 } 4745 void Vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4746 Vbit(al, dt, rd, rn, rm); 4747 } 4748 void Vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 4749 Vbit(cond, kDataTypeValueNone, rd, rn, rm); 4750 } 4751 void Vbit(DRegister rd, DRegister rn, DRegister rm) { 4752 Vbit(al, kDataTypeValueNone, rd, rn, rm); 4753 } 4754 4755 void Vbit( 4756 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4757 VIXL_ASSERT(allow_macro_instructions_); 4758 VIXL_ASSERT(OutsideITBlock()); 4759 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4760 ITScope it_scope(this, &cond); 4761 vbit(cond, dt, rd, rn, rm); 4762 } 4763 void Vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4764 Vbit(al, dt, rd, rn, rm); 4765 } 4766 void Vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 4767 Vbit(cond, kDataTypeValueNone, rd, rn, rm); 4768 } 4769 void Vbit(QRegister rd, QRegister rn, QRegister rm) { 4770 Vbit(al, kDataTypeValueNone, rd, rn, rm); 4771 } 4772 4773 void Vbsl( 4774 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4775 VIXL_ASSERT(allow_macro_instructions_); 4776 VIXL_ASSERT(OutsideITBlock()); 4777 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4778 ITScope it_scope(this, &cond); 4779 vbsl(cond, dt, rd, rn, rm); 4780 } 4781 void Vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4782 Vbsl(al, dt, rd, rn, rm); 4783 } 4784 void Vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 4785 Vbsl(cond, kDataTypeValueNone, rd, rn, rm); 4786 } 4787 void Vbsl(DRegister rd, DRegister rn, DRegister rm) { 4788 Vbsl(al, kDataTypeValueNone, rd, rn, rm); 4789 } 4790 4791 void Vbsl( 4792 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4793 VIXL_ASSERT(allow_macro_instructions_); 4794 VIXL_ASSERT(OutsideITBlock()); 4795 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4796 ITScope it_scope(this, &cond); 4797 vbsl(cond, dt, rd, rn, rm); 4798 } 4799 void Vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4800 Vbsl(al, dt, rd, rn, rm); 4801 } 4802 void Vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 4803 Vbsl(cond, kDataTypeValueNone, rd, rn, rm); 4804 } 4805 void Vbsl(QRegister rd, QRegister rn, QRegister rm) { 4806 Vbsl(al, kDataTypeValueNone, rd, rn, rm); 4807 } 4808 4809 void Vceq(Condition cond, 4810 DataType dt, 4811 DRegister rd, 4812 DRegister rm, 4813 const DOperand& operand) { 4814 VIXL_ASSERT(allow_macro_instructions_); 4815 VIXL_ASSERT(OutsideITBlock()); 4816 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4817 ITScope it_scope(this, &cond); 4818 vceq(cond, dt, rd, rm, operand); 4819 } 4820 void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4821 Vceq(al, dt, rd, rm, operand); 4822 } 4823 4824 void Vceq(Condition cond, 4825 DataType dt, 4826 QRegister rd, 4827 QRegister rm, 4828 const QOperand& operand) { 4829 VIXL_ASSERT(allow_macro_instructions_); 4830 VIXL_ASSERT(OutsideITBlock()); 4831 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4832 ITScope it_scope(this, &cond); 4833 vceq(cond, dt, rd, rm, operand); 4834 } 4835 void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4836 Vceq(al, dt, rd, rm, operand); 4837 } 4838 4839 void Vceq( 4840 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4841 VIXL_ASSERT(allow_macro_instructions_); 4842 VIXL_ASSERT(OutsideITBlock()); 4843 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4844 ITScope it_scope(this, &cond); 4845 vceq(cond, dt, rd, rn, rm); 4846 } 4847 void Vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4848 Vceq(al, dt, rd, rn, rm); 4849 } 4850 4851 void Vceq( 4852 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4853 VIXL_ASSERT(allow_macro_instructions_); 4854 VIXL_ASSERT(OutsideITBlock()); 4855 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4856 ITScope it_scope(this, &cond); 4857 vceq(cond, dt, rd, rn, rm); 4858 } 4859 void Vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4860 Vceq(al, dt, rd, rn, rm); 4861 } 4862 4863 void Vcge(Condition cond, 4864 DataType dt, 4865 DRegister rd, 4866 DRegister rm, 4867 const DOperand& operand) { 4868 VIXL_ASSERT(allow_macro_instructions_); 4869 VIXL_ASSERT(OutsideITBlock()); 4870 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4871 ITScope it_scope(this, &cond); 4872 vcge(cond, dt, rd, rm, operand); 4873 } 4874 void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4875 Vcge(al, dt, rd, rm, operand); 4876 } 4877 4878 void Vcge(Condition cond, 4879 DataType dt, 4880 QRegister rd, 4881 QRegister rm, 4882 const QOperand& operand) { 4883 VIXL_ASSERT(allow_macro_instructions_); 4884 VIXL_ASSERT(OutsideITBlock()); 4885 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4886 ITScope it_scope(this, &cond); 4887 vcge(cond, dt, rd, rm, operand); 4888 } 4889 void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4890 Vcge(al, dt, rd, rm, operand); 4891 } 4892 4893 void Vcge( 4894 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4895 VIXL_ASSERT(allow_macro_instructions_); 4896 VIXL_ASSERT(OutsideITBlock()); 4897 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4898 ITScope it_scope(this, &cond); 4899 vcge(cond, dt, rd, rn, rm); 4900 } 4901 void Vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4902 Vcge(al, dt, rd, rn, rm); 4903 } 4904 4905 void Vcge( 4906 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4907 VIXL_ASSERT(allow_macro_instructions_); 4908 VIXL_ASSERT(OutsideITBlock()); 4909 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4910 ITScope it_scope(this, &cond); 4911 vcge(cond, dt, rd, rn, rm); 4912 } 4913 void Vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4914 Vcge(al, dt, rd, rn, rm); 4915 } 4916 4917 void Vcgt(Condition cond, 4918 DataType dt, 4919 DRegister rd, 4920 DRegister rm, 4921 const DOperand& operand) { 4922 VIXL_ASSERT(allow_macro_instructions_); 4923 VIXL_ASSERT(OutsideITBlock()); 4924 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4925 ITScope it_scope(this, &cond); 4926 vcgt(cond, dt, rd, rm, operand); 4927 } 4928 void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4929 Vcgt(al, dt, rd, rm, operand); 4930 } 4931 4932 void Vcgt(Condition cond, 4933 DataType dt, 4934 QRegister rd, 4935 QRegister rm, 4936 const QOperand& operand) { 4937 VIXL_ASSERT(allow_macro_instructions_); 4938 VIXL_ASSERT(OutsideITBlock()); 4939 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4940 ITScope it_scope(this, &cond); 4941 vcgt(cond, dt, rd, rm, operand); 4942 } 4943 void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4944 Vcgt(al, dt, rd, rm, operand); 4945 } 4946 4947 void Vcgt( 4948 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4949 VIXL_ASSERT(allow_macro_instructions_); 4950 VIXL_ASSERT(OutsideITBlock()); 4951 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4952 ITScope it_scope(this, &cond); 4953 vcgt(cond, dt, rd, rn, rm); 4954 } 4955 void Vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4956 Vcgt(al, dt, rd, rn, rm); 4957 } 4958 4959 void Vcgt( 4960 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4961 VIXL_ASSERT(allow_macro_instructions_); 4962 VIXL_ASSERT(OutsideITBlock()); 4963 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4964 ITScope it_scope(this, &cond); 4965 vcgt(cond, dt, rd, rn, rm); 4966 } 4967 void Vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4968 Vcgt(al, dt, rd, rn, rm); 4969 } 4970 4971 void Vcle(Condition cond, 4972 DataType dt, 4973 DRegister rd, 4974 DRegister rm, 4975 const DOperand& operand) { 4976 VIXL_ASSERT(allow_macro_instructions_); 4977 VIXL_ASSERT(OutsideITBlock()); 4978 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4979 ITScope it_scope(this, &cond); 4980 vcle(cond, dt, rd, rm, operand); 4981 } 4982 void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4983 Vcle(al, dt, rd, rm, operand); 4984 } 4985 4986 void Vcle(Condition cond, 4987 DataType dt, 4988 QRegister rd, 4989 QRegister rm, 4990 const QOperand& operand) { 4991 VIXL_ASSERT(allow_macro_instructions_); 4992 VIXL_ASSERT(OutsideITBlock()); 4993 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 4994 ITScope it_scope(this, &cond); 4995 vcle(cond, dt, rd, rm, operand); 4996 } 4997 void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4998 Vcle(al, dt, rd, rm, operand); 4999 } 5000 5001 void Vcle( 5002 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5003 VIXL_ASSERT(allow_macro_instructions_); 5004 VIXL_ASSERT(OutsideITBlock()); 5005 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5006 ITScope it_scope(this, &cond); 5007 vcle(cond, dt, rd, rn, rm); 5008 } 5009 void Vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5010 Vcle(al, dt, rd, rn, rm); 5011 } 5012 5013 void Vcle( 5014 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5015 VIXL_ASSERT(allow_macro_instructions_); 5016 VIXL_ASSERT(OutsideITBlock()); 5017 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5018 ITScope it_scope(this, &cond); 5019 vcle(cond, dt, rd, rn, rm); 5020 } 5021 void Vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5022 Vcle(al, dt, rd, rn, rm); 5023 } 5024 5025 void Vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5026 VIXL_ASSERT(allow_macro_instructions_); 5027 VIXL_ASSERT(OutsideITBlock()); 5028 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5029 ITScope it_scope(this, &cond); 5030 vcls(cond, dt, rd, rm); 5031 } 5032 void Vcls(DataType dt, DRegister rd, DRegister rm) { Vcls(al, dt, rd, rm); } 5033 5034 void Vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) { 5035 VIXL_ASSERT(allow_macro_instructions_); 5036 VIXL_ASSERT(OutsideITBlock()); 5037 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5038 ITScope it_scope(this, &cond); 5039 vcls(cond, dt, rd, rm); 5040 } 5041 void Vcls(DataType dt, QRegister rd, QRegister rm) { Vcls(al, dt, rd, rm); } 5042 5043 void Vclt(Condition cond, 5044 DataType dt, 5045 DRegister rd, 5046 DRegister rm, 5047 const DOperand& operand) { 5048 VIXL_ASSERT(allow_macro_instructions_); 5049 VIXL_ASSERT(OutsideITBlock()); 5050 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5051 ITScope it_scope(this, &cond); 5052 vclt(cond, dt, rd, rm, operand); 5053 } 5054 void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5055 Vclt(al, dt, rd, rm, operand); 5056 } 5057 5058 void Vclt(Condition cond, 5059 DataType dt, 5060 QRegister rd, 5061 QRegister rm, 5062 const QOperand& operand) { 5063 VIXL_ASSERT(allow_macro_instructions_); 5064 VIXL_ASSERT(OutsideITBlock()); 5065 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5066 ITScope it_scope(this, &cond); 5067 vclt(cond, dt, rd, rm, operand); 5068 } 5069 void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5070 Vclt(al, dt, rd, rm, operand); 5071 } 5072 5073 void Vclt( 5074 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5075 VIXL_ASSERT(allow_macro_instructions_); 5076 VIXL_ASSERT(OutsideITBlock()); 5077 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5078 ITScope it_scope(this, &cond); 5079 vclt(cond, dt, rd, rn, rm); 5080 } 5081 void Vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5082 Vclt(al, dt, rd, rn, rm); 5083 } 5084 5085 void Vclt( 5086 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5087 VIXL_ASSERT(allow_macro_instructions_); 5088 VIXL_ASSERT(OutsideITBlock()); 5089 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5090 ITScope it_scope(this, &cond); 5091 vclt(cond, dt, rd, rn, rm); 5092 } 5093 void Vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5094 Vclt(al, dt, rd, rn, rm); 5095 } 5096 5097 void Vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5098 VIXL_ASSERT(allow_macro_instructions_); 5099 VIXL_ASSERT(OutsideITBlock()); 5100 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5101 ITScope it_scope(this, &cond); 5102 vclz(cond, dt, rd, rm); 5103 } 5104 void Vclz(DataType dt, DRegister rd, DRegister rm) { Vclz(al, dt, rd, rm); } 5105 5106 void Vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) { 5107 VIXL_ASSERT(allow_macro_instructions_); 5108 VIXL_ASSERT(OutsideITBlock()); 5109 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5110 ITScope it_scope(this, &cond); 5111 vclz(cond, dt, rd, rm); 5112 } 5113 void Vclz(DataType dt, QRegister rd, QRegister rm) { Vclz(al, dt, rd, rm); } 5114 5115 void Vcmp(Condition cond, DataType dt, SRegister rd, SRegister rm) { 5116 VIXL_ASSERT(allow_macro_instructions_); 5117 VIXL_ASSERT(OutsideITBlock()); 5118 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5119 ITScope it_scope(this, &cond); 5120 vcmp(cond, dt, rd, rm); 5121 } 5122 void Vcmp(DataType dt, SRegister rd, SRegister rm) { Vcmp(al, dt, rd, rm); } 5123 5124 void Vcmp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5125 VIXL_ASSERT(allow_macro_instructions_); 5126 VIXL_ASSERT(OutsideITBlock()); 5127 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5128 ITScope it_scope(this, &cond); 5129 vcmp(cond, dt, rd, rm); 5130 } 5131 void Vcmp(DataType dt, DRegister rd, DRegister rm) { Vcmp(al, dt, rd, rm); } 5132 5133 void Vcmp(Condition cond, DataType dt, SRegister rd, double imm) { 5134 VIXL_ASSERT(allow_macro_instructions_); 5135 VIXL_ASSERT(OutsideITBlock()); 5136 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5137 ITScope it_scope(this, &cond); 5138 vcmp(cond, dt, rd, imm); 5139 } 5140 void Vcmp(DataType dt, SRegister rd, double imm) { Vcmp(al, dt, rd, imm); } 5141 5142 void Vcmp(Condition cond, DataType dt, DRegister rd, double imm) { 5143 VIXL_ASSERT(allow_macro_instructions_); 5144 VIXL_ASSERT(OutsideITBlock()); 5145 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5146 ITScope it_scope(this, &cond); 5147 vcmp(cond, dt, rd, imm); 5148 } 5149 void Vcmp(DataType dt, DRegister rd, double imm) { Vcmp(al, dt, rd, imm); } 5150 5151 void Vcmpe(Condition cond, DataType dt, SRegister rd, SRegister rm) { 5152 VIXL_ASSERT(allow_macro_instructions_); 5153 VIXL_ASSERT(OutsideITBlock()); 5154 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5155 ITScope it_scope(this, &cond); 5156 vcmpe(cond, dt, rd, rm); 5157 } 5158 void Vcmpe(DataType dt, SRegister rd, SRegister rm) { Vcmpe(al, dt, rd, rm); } 5159 5160 void Vcmpe(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5161 VIXL_ASSERT(allow_macro_instructions_); 5162 VIXL_ASSERT(OutsideITBlock()); 5163 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5164 ITScope it_scope(this, &cond); 5165 vcmpe(cond, dt, rd, rm); 5166 } 5167 void Vcmpe(DataType dt, DRegister rd, DRegister rm) { Vcmpe(al, dt, rd, rm); } 5168 5169 void Vcmpe(Condition cond, DataType dt, SRegister rd, double imm) { 5170 VIXL_ASSERT(allow_macro_instructions_); 5171 VIXL_ASSERT(OutsideITBlock()); 5172 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5173 ITScope it_scope(this, &cond); 5174 vcmpe(cond, dt, rd, imm); 5175 } 5176 void Vcmpe(DataType dt, SRegister rd, double imm) { Vcmpe(al, dt, rd, imm); } 5177 5178 void Vcmpe(Condition cond, DataType dt, DRegister rd, double imm) { 5179 VIXL_ASSERT(allow_macro_instructions_); 5180 VIXL_ASSERT(OutsideITBlock()); 5181 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5182 ITScope it_scope(this, &cond); 5183 vcmpe(cond, dt, rd, imm); 5184 } 5185 void Vcmpe(DataType dt, DRegister rd, double imm) { Vcmpe(al, dt, rd, imm); } 5186 5187 void Vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5188 VIXL_ASSERT(allow_macro_instructions_); 5189 VIXL_ASSERT(OutsideITBlock()); 5190 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5191 ITScope it_scope(this, &cond); 5192 vcnt(cond, dt, rd, rm); 5193 } 5194 void Vcnt(DataType dt, DRegister rd, DRegister rm) { Vcnt(al, dt, rd, rm); } 5195 5196 void Vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) { 5197 VIXL_ASSERT(allow_macro_instructions_); 5198 VIXL_ASSERT(OutsideITBlock()); 5199 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5200 ITScope it_scope(this, &cond); 5201 vcnt(cond, dt, rd, rm); 5202 } 5203 void Vcnt(DataType dt, QRegister rd, QRegister rm) { Vcnt(al, dt, rd, rm); } 5204 5205 void Vcvt( 5206 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 5207 VIXL_ASSERT(allow_macro_instructions_); 5208 VIXL_ASSERT(OutsideITBlock()); 5209 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5210 ITScope it_scope(this, &cond); 5211 vcvt(cond, dt1, dt2, rd, rm); 5212 } 5213 void Vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 5214 Vcvt(al, dt1, dt2, rd, rm); 5215 } 5216 5217 void Vcvt( 5218 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5219 VIXL_ASSERT(allow_macro_instructions_); 5220 VIXL_ASSERT(OutsideITBlock()); 5221 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5222 ITScope it_scope(this, &cond); 5223 vcvt(cond, dt1, dt2, rd, rm); 5224 } 5225 void Vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5226 Vcvt(al, dt1, dt2, rd, rm); 5227 } 5228 5229 void Vcvt(Condition cond, 5230 DataType dt1, 5231 DataType dt2, 5232 DRegister rd, 5233 DRegister rm, 5234 int32_t fbits) { 5235 VIXL_ASSERT(allow_macro_instructions_); 5236 VIXL_ASSERT(OutsideITBlock()); 5237 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5238 ITScope it_scope(this, &cond); 5239 vcvt(cond, dt1, dt2, rd, rm, fbits); 5240 } 5241 void Vcvt( 5242 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { 5243 Vcvt(al, dt1, dt2, rd, rm, fbits); 5244 } 5245 5246 void Vcvt(Condition cond, 5247 DataType dt1, 5248 DataType dt2, 5249 QRegister rd, 5250 QRegister rm, 5251 int32_t fbits) { 5252 VIXL_ASSERT(allow_macro_instructions_); 5253 VIXL_ASSERT(OutsideITBlock()); 5254 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5255 ITScope it_scope(this, &cond); 5256 vcvt(cond, dt1, dt2, rd, rm, fbits); 5257 } 5258 void Vcvt( 5259 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { 5260 Vcvt(al, dt1, dt2, rd, rm, fbits); 5261 } 5262 5263 void Vcvt(Condition cond, 5264 DataType dt1, 5265 DataType dt2, 5266 SRegister rd, 5267 SRegister rm, 5268 int32_t fbits) { 5269 VIXL_ASSERT(allow_macro_instructions_); 5270 VIXL_ASSERT(OutsideITBlock()); 5271 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5272 ITScope it_scope(this, &cond); 5273 vcvt(cond, dt1, dt2, rd, rm, fbits); 5274 } 5275 void Vcvt( 5276 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { 5277 Vcvt(al, dt1, dt2, rd, rm, fbits); 5278 } 5279 5280 void Vcvt( 5281 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5282 VIXL_ASSERT(allow_macro_instructions_); 5283 VIXL_ASSERT(OutsideITBlock()); 5284 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5285 ITScope it_scope(this, &cond); 5286 vcvt(cond, dt1, dt2, rd, rm); 5287 } 5288 void Vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5289 Vcvt(al, dt1, dt2, rd, rm); 5290 } 5291 5292 void Vcvt( 5293 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 5294 VIXL_ASSERT(allow_macro_instructions_); 5295 VIXL_ASSERT(OutsideITBlock()); 5296 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5297 ITScope it_scope(this, &cond); 5298 vcvt(cond, dt1, dt2, rd, rm); 5299 } 5300 void Vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 5301 Vcvt(al, dt1, dt2, rd, rm); 5302 } 5303 5304 void Vcvt( 5305 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 5306 VIXL_ASSERT(allow_macro_instructions_); 5307 VIXL_ASSERT(OutsideITBlock()); 5308 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5309 ITScope it_scope(this, &cond); 5310 vcvt(cond, dt1, dt2, rd, rm); 5311 } 5312 void Vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 5313 Vcvt(al, dt1, dt2, rd, rm); 5314 } 5315 5316 void Vcvt( 5317 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 5318 VIXL_ASSERT(allow_macro_instructions_); 5319 VIXL_ASSERT(OutsideITBlock()); 5320 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5321 ITScope it_scope(this, &cond); 5322 vcvt(cond, dt1, dt2, rd, rm); 5323 } 5324 void Vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 5325 Vcvt(al, dt1, dt2, rd, rm); 5326 } 5327 5328 void Vcvt( 5329 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5330 VIXL_ASSERT(allow_macro_instructions_); 5331 VIXL_ASSERT(OutsideITBlock()); 5332 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5333 ITScope it_scope(this, &cond); 5334 vcvt(cond, dt1, dt2, rd, rm); 5335 } 5336 void Vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5337 Vcvt(al, dt1, dt2, rd, rm); 5338 } 5339 5340 void Vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5341 VIXL_ASSERT(allow_macro_instructions_); 5342 VIXL_ASSERT(OutsideITBlock()); 5343 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5344 vcvta(dt1, dt2, rd, rm); 5345 } 5346 5347 void Vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 5348 VIXL_ASSERT(allow_macro_instructions_); 5349 VIXL_ASSERT(OutsideITBlock()); 5350 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5351 vcvta(dt1, dt2, rd, rm); 5352 } 5353 5354 void Vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5355 VIXL_ASSERT(allow_macro_instructions_); 5356 VIXL_ASSERT(OutsideITBlock()); 5357 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5358 vcvta(dt1, dt2, rd, rm); 5359 } 5360 5361 void Vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5362 VIXL_ASSERT(allow_macro_instructions_); 5363 VIXL_ASSERT(OutsideITBlock()); 5364 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5365 vcvta(dt1, dt2, rd, rm); 5366 } 5367 5368 void Vcvtb( 5369 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5370 VIXL_ASSERT(allow_macro_instructions_); 5371 VIXL_ASSERT(OutsideITBlock()); 5372 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5373 ITScope it_scope(this, &cond); 5374 vcvtb(cond, dt1, dt2, rd, rm); 5375 } 5376 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5377 Vcvtb(al, dt1, dt2, rd, rm); 5378 } 5379 5380 void Vcvtb( 5381 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 5382 VIXL_ASSERT(allow_macro_instructions_); 5383 VIXL_ASSERT(OutsideITBlock()); 5384 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5385 ITScope it_scope(this, &cond); 5386 vcvtb(cond, dt1, dt2, rd, rm); 5387 } 5388 void Vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 5389 Vcvtb(al, dt1, dt2, rd, rm); 5390 } 5391 5392 void Vcvtb( 5393 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5394 VIXL_ASSERT(allow_macro_instructions_); 5395 VIXL_ASSERT(OutsideITBlock()); 5396 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5397 ITScope it_scope(this, &cond); 5398 vcvtb(cond, dt1, dt2, rd, rm); 5399 } 5400 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5401 Vcvtb(al, dt1, dt2, rd, rm); 5402 } 5403 5404 void Vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5405 VIXL_ASSERT(allow_macro_instructions_); 5406 VIXL_ASSERT(OutsideITBlock()); 5407 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5408 vcvtm(dt1, dt2, rd, rm); 5409 } 5410 5411 void Vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 5412 VIXL_ASSERT(allow_macro_instructions_); 5413 VIXL_ASSERT(OutsideITBlock()); 5414 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5415 vcvtm(dt1, dt2, rd, rm); 5416 } 5417 5418 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5419 VIXL_ASSERT(allow_macro_instructions_); 5420 VIXL_ASSERT(OutsideITBlock()); 5421 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5422 vcvtm(dt1, dt2, rd, rm); 5423 } 5424 5425 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5426 VIXL_ASSERT(allow_macro_instructions_); 5427 VIXL_ASSERT(OutsideITBlock()); 5428 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5429 vcvtm(dt1, dt2, rd, rm); 5430 } 5431 5432 void Vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5433 VIXL_ASSERT(allow_macro_instructions_); 5434 VIXL_ASSERT(OutsideITBlock()); 5435 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5436 vcvtn(dt1, dt2, rd, rm); 5437 } 5438 5439 void Vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 5440 VIXL_ASSERT(allow_macro_instructions_); 5441 VIXL_ASSERT(OutsideITBlock()); 5442 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5443 vcvtn(dt1, dt2, rd, rm); 5444 } 5445 5446 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5447 VIXL_ASSERT(allow_macro_instructions_); 5448 VIXL_ASSERT(OutsideITBlock()); 5449 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5450 vcvtn(dt1, dt2, rd, rm); 5451 } 5452 5453 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5454 VIXL_ASSERT(allow_macro_instructions_); 5455 VIXL_ASSERT(OutsideITBlock()); 5456 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5457 vcvtn(dt1, dt2, rd, rm); 5458 } 5459 5460 void Vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5461 VIXL_ASSERT(allow_macro_instructions_); 5462 VIXL_ASSERT(OutsideITBlock()); 5463 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5464 vcvtp(dt1, dt2, rd, rm); 5465 } 5466 5467 void Vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 5468 VIXL_ASSERT(allow_macro_instructions_); 5469 VIXL_ASSERT(OutsideITBlock()); 5470 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5471 vcvtp(dt1, dt2, rd, rm); 5472 } 5473 5474 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5475 VIXL_ASSERT(allow_macro_instructions_); 5476 VIXL_ASSERT(OutsideITBlock()); 5477 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5478 vcvtp(dt1, dt2, rd, rm); 5479 } 5480 5481 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5482 VIXL_ASSERT(allow_macro_instructions_); 5483 VIXL_ASSERT(OutsideITBlock()); 5484 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5485 vcvtp(dt1, dt2, rd, rm); 5486 } 5487 5488 void Vcvtr( 5489 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5490 VIXL_ASSERT(allow_macro_instructions_); 5491 VIXL_ASSERT(OutsideITBlock()); 5492 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5493 ITScope it_scope(this, &cond); 5494 vcvtr(cond, dt1, dt2, rd, rm); 5495 } 5496 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5497 Vcvtr(al, dt1, dt2, rd, rm); 5498 } 5499 5500 void Vcvtr( 5501 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5502 VIXL_ASSERT(allow_macro_instructions_); 5503 VIXL_ASSERT(OutsideITBlock()); 5504 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5505 ITScope it_scope(this, &cond); 5506 vcvtr(cond, dt1, dt2, rd, rm); 5507 } 5508 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5509 Vcvtr(al, dt1, dt2, rd, rm); 5510 } 5511 5512 void Vcvtt( 5513 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5514 VIXL_ASSERT(allow_macro_instructions_); 5515 VIXL_ASSERT(OutsideITBlock()); 5516 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5517 ITScope it_scope(this, &cond); 5518 vcvtt(cond, dt1, dt2, rd, rm); 5519 } 5520 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5521 Vcvtt(al, dt1, dt2, rd, rm); 5522 } 5523 5524 void Vcvtt( 5525 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 5526 VIXL_ASSERT(allow_macro_instructions_); 5527 VIXL_ASSERT(OutsideITBlock()); 5528 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5529 ITScope it_scope(this, &cond); 5530 vcvtt(cond, dt1, dt2, rd, rm); 5531 } 5532 void Vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 5533 Vcvtt(al, dt1, dt2, rd, rm); 5534 } 5535 5536 void Vcvtt( 5537 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5538 VIXL_ASSERT(allow_macro_instructions_); 5539 VIXL_ASSERT(OutsideITBlock()); 5540 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5541 ITScope it_scope(this, &cond); 5542 vcvtt(cond, dt1, dt2, rd, rm); 5543 } 5544 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 5545 Vcvtt(al, dt1, dt2, rd, rm); 5546 } 5547 5548 void Vdiv( 5549 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5550 VIXL_ASSERT(allow_macro_instructions_); 5551 VIXL_ASSERT(OutsideITBlock()); 5552 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5553 ITScope it_scope(this, &cond); 5554 vdiv(cond, dt, rd, rn, rm); 5555 } 5556 void Vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5557 Vdiv(al, dt, rd, rn, rm); 5558 } 5559 5560 void Vdiv( 5561 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5562 VIXL_ASSERT(allow_macro_instructions_); 5563 VIXL_ASSERT(OutsideITBlock()); 5564 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5565 ITScope it_scope(this, &cond); 5566 vdiv(cond, dt, rd, rn, rm); 5567 } 5568 void Vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5569 Vdiv(al, dt, rd, rn, rm); 5570 } 5571 5572 void Vdup(Condition cond, DataType dt, QRegister rd, Register rt) { 5573 VIXL_ASSERT(allow_macro_instructions_); 5574 VIXL_ASSERT(OutsideITBlock()); 5575 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5576 ITScope it_scope(this, &cond); 5577 vdup(cond, dt, rd, rt); 5578 } 5579 void Vdup(DataType dt, QRegister rd, Register rt) { Vdup(al, dt, rd, rt); } 5580 5581 void Vdup(Condition cond, DataType dt, DRegister rd, Register rt) { 5582 VIXL_ASSERT(allow_macro_instructions_); 5583 VIXL_ASSERT(OutsideITBlock()); 5584 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5585 ITScope it_scope(this, &cond); 5586 vdup(cond, dt, rd, rt); 5587 } 5588 void Vdup(DataType dt, DRegister rd, Register rt) { Vdup(al, dt, rd, rt); } 5589 5590 void Vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm) { 5591 VIXL_ASSERT(allow_macro_instructions_); 5592 VIXL_ASSERT(OutsideITBlock()); 5593 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5594 ITScope it_scope(this, &cond); 5595 vdup(cond, dt, rd, rm); 5596 } 5597 void Vdup(DataType dt, DRegister rd, DRegisterLane rm) { 5598 Vdup(al, dt, rd, rm); 5599 } 5600 5601 void Vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm) { 5602 VIXL_ASSERT(allow_macro_instructions_); 5603 VIXL_ASSERT(OutsideITBlock()); 5604 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5605 ITScope it_scope(this, &cond); 5606 vdup(cond, dt, rd, rm); 5607 } 5608 void Vdup(DataType dt, QRegister rd, DRegisterLane rm) { 5609 Vdup(al, dt, rd, rm); 5610 } 5611 5612 void Veor( 5613 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5614 VIXL_ASSERT(allow_macro_instructions_); 5615 VIXL_ASSERT(OutsideITBlock()); 5616 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5617 ITScope it_scope(this, &cond); 5618 veor(cond, dt, rd, rn, rm); 5619 } 5620 void Veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5621 Veor(al, dt, rd, rn, rm); 5622 } 5623 void Veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5624 Veor(cond, kDataTypeValueNone, rd, rn, rm); 5625 } 5626 void Veor(DRegister rd, DRegister rn, DRegister rm) { 5627 Veor(al, kDataTypeValueNone, rd, rn, rm); 5628 } 5629 5630 void Veor( 5631 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5632 VIXL_ASSERT(allow_macro_instructions_); 5633 VIXL_ASSERT(OutsideITBlock()); 5634 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5635 ITScope it_scope(this, &cond); 5636 veor(cond, dt, rd, rn, rm); 5637 } 5638 void Veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5639 Veor(al, dt, rd, rn, rm); 5640 } 5641 void Veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5642 Veor(cond, kDataTypeValueNone, rd, rn, rm); 5643 } 5644 void Veor(QRegister rd, QRegister rn, QRegister rm) { 5645 Veor(al, kDataTypeValueNone, rd, rn, rm); 5646 } 5647 5648 void Vext(Condition cond, 5649 DataType dt, 5650 DRegister rd, 5651 DRegister rn, 5652 DRegister rm, 5653 const DOperand& operand) { 5654 VIXL_ASSERT(allow_macro_instructions_); 5655 VIXL_ASSERT(OutsideITBlock()); 5656 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5657 ITScope it_scope(this, &cond); 5658 vext(cond, dt, rd, rn, rm, operand); 5659 } 5660 void Vext(DataType dt, 5661 DRegister rd, 5662 DRegister rn, 5663 DRegister rm, 5664 const DOperand& operand) { 5665 Vext(al, dt, rd, rn, rm, operand); 5666 } 5667 5668 void Vext(Condition cond, 5669 DataType dt, 5670 QRegister rd, 5671 QRegister rn, 5672 QRegister rm, 5673 const QOperand& operand) { 5674 VIXL_ASSERT(allow_macro_instructions_); 5675 VIXL_ASSERT(OutsideITBlock()); 5676 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5677 ITScope it_scope(this, &cond); 5678 vext(cond, dt, rd, rn, rm, operand); 5679 } 5680 void Vext(DataType dt, 5681 QRegister rd, 5682 QRegister rn, 5683 QRegister rm, 5684 const QOperand& operand) { 5685 Vext(al, dt, rd, rn, rm, operand); 5686 } 5687 5688 void Vfma( 5689 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5690 VIXL_ASSERT(allow_macro_instructions_); 5691 VIXL_ASSERT(OutsideITBlock()); 5692 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5693 ITScope it_scope(this, &cond); 5694 vfma(cond, dt, rd, rn, rm); 5695 } 5696 void Vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5697 Vfma(al, dt, rd, rn, rm); 5698 } 5699 5700 void Vfma( 5701 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5702 VIXL_ASSERT(allow_macro_instructions_); 5703 VIXL_ASSERT(OutsideITBlock()); 5704 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5705 ITScope it_scope(this, &cond); 5706 vfma(cond, dt, rd, rn, rm); 5707 } 5708 void Vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5709 Vfma(al, dt, rd, rn, rm); 5710 } 5711 5712 void Vfma( 5713 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5714 VIXL_ASSERT(allow_macro_instructions_); 5715 VIXL_ASSERT(OutsideITBlock()); 5716 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5717 ITScope it_scope(this, &cond); 5718 vfma(cond, dt, rd, rn, rm); 5719 } 5720 void Vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5721 Vfma(al, dt, rd, rn, rm); 5722 } 5723 5724 void Vfms( 5725 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5726 VIXL_ASSERT(allow_macro_instructions_); 5727 VIXL_ASSERT(OutsideITBlock()); 5728 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5729 ITScope it_scope(this, &cond); 5730 vfms(cond, dt, rd, rn, rm); 5731 } 5732 void Vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5733 Vfms(al, dt, rd, rn, rm); 5734 } 5735 5736 void Vfms( 5737 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5738 VIXL_ASSERT(allow_macro_instructions_); 5739 VIXL_ASSERT(OutsideITBlock()); 5740 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5741 ITScope it_scope(this, &cond); 5742 vfms(cond, dt, rd, rn, rm); 5743 } 5744 void Vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5745 Vfms(al, dt, rd, rn, rm); 5746 } 5747 5748 void Vfms( 5749 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5750 VIXL_ASSERT(allow_macro_instructions_); 5751 VIXL_ASSERT(OutsideITBlock()); 5752 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5753 ITScope it_scope(this, &cond); 5754 vfms(cond, dt, rd, rn, rm); 5755 } 5756 void Vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5757 Vfms(al, dt, rd, rn, rm); 5758 } 5759 5760 void Vfnma( 5761 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5762 VIXL_ASSERT(allow_macro_instructions_); 5763 VIXL_ASSERT(OutsideITBlock()); 5764 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5765 ITScope it_scope(this, &cond); 5766 vfnma(cond, dt, rd, rn, rm); 5767 } 5768 void Vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5769 Vfnma(al, dt, rd, rn, rm); 5770 } 5771 5772 void Vfnma( 5773 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5774 VIXL_ASSERT(allow_macro_instructions_); 5775 VIXL_ASSERT(OutsideITBlock()); 5776 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5777 ITScope it_scope(this, &cond); 5778 vfnma(cond, dt, rd, rn, rm); 5779 } 5780 void Vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5781 Vfnma(al, dt, rd, rn, rm); 5782 } 5783 5784 void Vfnms( 5785 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5786 VIXL_ASSERT(allow_macro_instructions_); 5787 VIXL_ASSERT(OutsideITBlock()); 5788 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5789 ITScope it_scope(this, &cond); 5790 vfnms(cond, dt, rd, rn, rm); 5791 } 5792 void Vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5793 Vfnms(al, dt, rd, rn, rm); 5794 } 5795 5796 void Vfnms( 5797 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5798 VIXL_ASSERT(allow_macro_instructions_); 5799 VIXL_ASSERT(OutsideITBlock()); 5800 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5801 ITScope it_scope(this, &cond); 5802 vfnms(cond, dt, rd, rn, rm); 5803 } 5804 void Vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5805 Vfnms(al, dt, rd, rn, rm); 5806 } 5807 5808 void Vhadd( 5809 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5810 VIXL_ASSERT(allow_macro_instructions_); 5811 VIXL_ASSERT(OutsideITBlock()); 5812 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5813 ITScope it_scope(this, &cond); 5814 vhadd(cond, dt, rd, rn, rm); 5815 } 5816 void Vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5817 Vhadd(al, dt, rd, rn, rm); 5818 } 5819 5820 void Vhadd( 5821 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5822 VIXL_ASSERT(allow_macro_instructions_); 5823 VIXL_ASSERT(OutsideITBlock()); 5824 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5825 ITScope it_scope(this, &cond); 5826 vhadd(cond, dt, rd, rn, rm); 5827 } 5828 void Vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5829 Vhadd(al, dt, rd, rn, rm); 5830 } 5831 5832 void Vhsub( 5833 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5834 VIXL_ASSERT(allow_macro_instructions_); 5835 VIXL_ASSERT(OutsideITBlock()); 5836 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5837 ITScope it_scope(this, &cond); 5838 vhsub(cond, dt, rd, rn, rm); 5839 } 5840 void Vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5841 Vhsub(al, dt, rd, rn, rm); 5842 } 5843 5844 void Vhsub( 5845 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5846 VIXL_ASSERT(allow_macro_instructions_); 5847 VIXL_ASSERT(OutsideITBlock()); 5848 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5849 ITScope it_scope(this, &cond); 5850 vhsub(cond, dt, rd, rn, rm); 5851 } 5852 void Vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5853 Vhsub(al, dt, rd, rn, rm); 5854 } 5855 5856 void Vld1(Condition cond, 5857 DataType dt, 5858 const NeonRegisterList& nreglist, 5859 const AlignedMemOperand& operand) { 5860 VIXL_ASSERT(allow_macro_instructions_); 5861 VIXL_ASSERT(OutsideITBlock()); 5862 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5863 ITScope it_scope(this, &cond); 5864 vld1(cond, dt, nreglist, operand); 5865 } 5866 void Vld1(DataType dt, 5867 const NeonRegisterList& nreglist, 5868 const AlignedMemOperand& operand) { 5869 Vld1(al, dt, nreglist, operand); 5870 } 5871 5872 void Vld2(Condition cond, 5873 DataType dt, 5874 const NeonRegisterList& nreglist, 5875 const AlignedMemOperand& operand) { 5876 VIXL_ASSERT(allow_macro_instructions_); 5877 VIXL_ASSERT(OutsideITBlock()); 5878 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5879 ITScope it_scope(this, &cond); 5880 vld2(cond, dt, nreglist, operand); 5881 } 5882 void Vld2(DataType dt, 5883 const NeonRegisterList& nreglist, 5884 const AlignedMemOperand& operand) { 5885 Vld2(al, dt, nreglist, operand); 5886 } 5887 5888 void Vld3(Condition cond, 5889 DataType dt, 5890 const NeonRegisterList& nreglist, 5891 const AlignedMemOperand& operand) { 5892 VIXL_ASSERT(allow_macro_instructions_); 5893 VIXL_ASSERT(OutsideITBlock()); 5894 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5895 ITScope it_scope(this, &cond); 5896 vld3(cond, dt, nreglist, operand); 5897 } 5898 void Vld3(DataType dt, 5899 const NeonRegisterList& nreglist, 5900 const AlignedMemOperand& operand) { 5901 Vld3(al, dt, nreglist, operand); 5902 } 5903 5904 void Vld3(Condition cond, 5905 DataType dt, 5906 const NeonRegisterList& nreglist, 5907 const MemOperand& operand) { 5908 VIXL_ASSERT(allow_macro_instructions_); 5909 VIXL_ASSERT(OutsideITBlock()); 5910 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5911 ITScope it_scope(this, &cond); 5912 vld3(cond, dt, nreglist, operand); 5913 } 5914 void Vld3(DataType dt, 5915 const NeonRegisterList& nreglist, 5916 const MemOperand& operand) { 5917 Vld3(al, dt, nreglist, operand); 5918 } 5919 5920 void Vld4(Condition cond, 5921 DataType dt, 5922 const NeonRegisterList& nreglist, 5923 const AlignedMemOperand& operand) { 5924 VIXL_ASSERT(allow_macro_instructions_); 5925 VIXL_ASSERT(OutsideITBlock()); 5926 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5927 ITScope it_scope(this, &cond); 5928 vld4(cond, dt, nreglist, operand); 5929 } 5930 void Vld4(DataType dt, 5931 const NeonRegisterList& nreglist, 5932 const AlignedMemOperand& operand) { 5933 Vld4(al, dt, nreglist, operand); 5934 } 5935 5936 void Vldm(Condition cond, 5937 DataType dt, 5938 Register rn, 5939 WriteBack write_back, 5940 DRegisterList dreglist) { 5941 VIXL_ASSERT(allow_macro_instructions_); 5942 VIXL_ASSERT(OutsideITBlock()); 5943 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5944 ITScope it_scope(this, &cond); 5945 vldm(cond, dt, rn, write_back, dreglist); 5946 } 5947 void Vldm(DataType dt, 5948 Register rn, 5949 WriteBack write_back, 5950 DRegisterList dreglist) { 5951 Vldm(al, dt, rn, write_back, dreglist); 5952 } 5953 void Vldm(Condition cond, 5954 Register rn, 5955 WriteBack write_back, 5956 DRegisterList dreglist) { 5957 Vldm(cond, kDataTypeValueNone, rn, write_back, dreglist); 5958 } 5959 void Vldm(Register rn, WriteBack write_back, DRegisterList dreglist) { 5960 Vldm(al, kDataTypeValueNone, rn, write_back, dreglist); 5961 } 5962 5963 void Vldm(Condition cond, 5964 DataType dt, 5965 Register rn, 5966 WriteBack write_back, 5967 SRegisterList sreglist) { 5968 VIXL_ASSERT(allow_macro_instructions_); 5969 VIXL_ASSERT(OutsideITBlock()); 5970 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5971 ITScope it_scope(this, &cond); 5972 vldm(cond, dt, rn, write_back, sreglist); 5973 } 5974 void Vldm(DataType dt, 5975 Register rn, 5976 WriteBack write_back, 5977 SRegisterList sreglist) { 5978 Vldm(al, dt, rn, write_back, sreglist); 5979 } 5980 void Vldm(Condition cond, 5981 Register rn, 5982 WriteBack write_back, 5983 SRegisterList sreglist) { 5984 Vldm(cond, kDataTypeValueNone, rn, write_back, sreglist); 5985 } 5986 void Vldm(Register rn, WriteBack write_back, SRegisterList sreglist) { 5987 Vldm(al, kDataTypeValueNone, rn, write_back, sreglist); 5988 } 5989 5990 void Vldmdb(Condition cond, 5991 DataType dt, 5992 Register rn, 5993 WriteBack write_back, 5994 DRegisterList dreglist) { 5995 VIXL_ASSERT(allow_macro_instructions_); 5996 VIXL_ASSERT(OutsideITBlock()); 5997 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 5998 ITScope it_scope(this, &cond); 5999 vldmdb(cond, dt, rn, write_back, dreglist); 6000 } 6001 void Vldmdb(DataType dt, 6002 Register rn, 6003 WriteBack write_back, 6004 DRegisterList dreglist) { 6005 Vldmdb(al, dt, rn, write_back, dreglist); 6006 } 6007 void Vldmdb(Condition cond, 6008 Register rn, 6009 WriteBack write_back, 6010 DRegisterList dreglist) { 6011 Vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 6012 } 6013 void Vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 6014 Vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 6015 } 6016 6017 void Vldmdb(Condition cond, 6018 DataType dt, 6019 Register rn, 6020 WriteBack write_back, 6021 SRegisterList sreglist) { 6022 VIXL_ASSERT(allow_macro_instructions_); 6023 VIXL_ASSERT(OutsideITBlock()); 6024 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6025 ITScope it_scope(this, &cond); 6026 vldmdb(cond, dt, rn, write_back, sreglist); 6027 } 6028 void Vldmdb(DataType dt, 6029 Register rn, 6030 WriteBack write_back, 6031 SRegisterList sreglist) { 6032 Vldmdb(al, dt, rn, write_back, sreglist); 6033 } 6034 void Vldmdb(Condition cond, 6035 Register rn, 6036 WriteBack write_back, 6037 SRegisterList sreglist) { 6038 Vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 6039 } 6040 void Vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 6041 Vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 6042 } 6043 6044 void Vldmia(Condition cond, 6045 DataType dt, 6046 Register rn, 6047 WriteBack write_back, 6048 DRegisterList dreglist) { 6049 VIXL_ASSERT(allow_macro_instructions_); 6050 VIXL_ASSERT(OutsideITBlock()); 6051 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6052 ITScope it_scope(this, &cond); 6053 vldmia(cond, dt, rn, write_back, dreglist); 6054 } 6055 void Vldmia(DataType dt, 6056 Register rn, 6057 WriteBack write_back, 6058 DRegisterList dreglist) { 6059 Vldmia(al, dt, rn, write_back, dreglist); 6060 } 6061 void Vldmia(Condition cond, 6062 Register rn, 6063 WriteBack write_back, 6064 DRegisterList dreglist) { 6065 Vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 6066 } 6067 void Vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 6068 Vldmia(al, kDataTypeValueNone, rn, write_back, dreglist); 6069 } 6070 6071 void Vldmia(Condition cond, 6072 DataType dt, 6073 Register rn, 6074 WriteBack write_back, 6075 SRegisterList sreglist) { 6076 VIXL_ASSERT(allow_macro_instructions_); 6077 VIXL_ASSERT(OutsideITBlock()); 6078 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6079 ITScope it_scope(this, &cond); 6080 vldmia(cond, dt, rn, write_back, sreglist); 6081 } 6082 void Vldmia(DataType dt, 6083 Register rn, 6084 WriteBack write_back, 6085 SRegisterList sreglist) { 6086 Vldmia(al, dt, rn, write_back, sreglist); 6087 } 6088 void Vldmia(Condition cond, 6089 Register rn, 6090 WriteBack write_back, 6091 SRegisterList sreglist) { 6092 Vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 6093 } 6094 void Vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 6095 Vldmia(al, kDataTypeValueNone, rn, write_back, sreglist); 6096 } 6097 6098 void Vldr(Condition cond, DataType dt, DRegister rd, Label* label) { 6099 VIXL_ASSERT(allow_macro_instructions_); 6100 VIXL_ASSERT(OutsideITBlock()); 6101 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6102 ITScope it_scope(this, &cond); 6103 vldr(cond, dt, rd, label); 6104 } 6105 void Vldr(DataType dt, DRegister rd, Label* label) { 6106 Vldr(al, dt, rd, label); 6107 } 6108 void Vldr(Condition cond, DRegister rd, Label* label) { 6109 Vldr(cond, Untyped64, rd, label); 6110 } 6111 void Vldr(DRegister rd, Label* label) { Vldr(al, Untyped64, rd, label); } 6112 6113 void Vldr(Condition cond, 6114 DataType dt, 6115 DRegister rd, 6116 const MemOperand& operand) { 6117 VIXL_ASSERT(allow_macro_instructions_); 6118 VIXL_ASSERT(OutsideITBlock()); 6119 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6120 ITScope it_scope(this, &cond); 6121 vldr(cond, dt, rd, operand); 6122 } 6123 void Vldr(DataType dt, DRegister rd, const MemOperand& operand) { 6124 Vldr(al, dt, rd, operand); 6125 } 6126 void Vldr(Condition cond, DRegister rd, const MemOperand& operand) { 6127 Vldr(cond, Untyped64, rd, operand); 6128 } 6129 void Vldr(DRegister rd, const MemOperand& operand) { 6130 Vldr(al, Untyped64, rd, operand); 6131 } 6132 6133 void Vldr(Condition cond, DataType dt, SRegister rd, Label* label) { 6134 VIXL_ASSERT(allow_macro_instructions_); 6135 VIXL_ASSERT(OutsideITBlock()); 6136 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6137 ITScope it_scope(this, &cond); 6138 vldr(cond, dt, rd, label); 6139 } 6140 void Vldr(DataType dt, SRegister rd, Label* label) { 6141 Vldr(al, dt, rd, label); 6142 } 6143 void Vldr(Condition cond, SRegister rd, Label* label) { 6144 Vldr(cond, Untyped32, rd, label); 6145 } 6146 void Vldr(SRegister rd, Label* label) { Vldr(al, Untyped32, rd, label); } 6147 6148 void Vldr(Condition cond, 6149 DataType dt, 6150 SRegister rd, 6151 const MemOperand& operand) { 6152 VIXL_ASSERT(allow_macro_instructions_); 6153 VIXL_ASSERT(OutsideITBlock()); 6154 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6155 ITScope it_scope(this, &cond); 6156 vldr(cond, dt, rd, operand); 6157 } 6158 void Vldr(DataType dt, SRegister rd, const MemOperand& operand) { 6159 Vldr(al, dt, rd, operand); 6160 } 6161 void Vldr(Condition cond, SRegister rd, const MemOperand& operand) { 6162 Vldr(cond, Untyped32, rd, operand); 6163 } 6164 void Vldr(SRegister rd, const MemOperand& operand) { 6165 Vldr(al, Untyped32, rd, operand); 6166 } 6167 6168 void Vmax( 6169 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6170 VIXL_ASSERT(allow_macro_instructions_); 6171 VIXL_ASSERT(OutsideITBlock()); 6172 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6173 ITScope it_scope(this, &cond); 6174 vmax(cond, dt, rd, rn, rm); 6175 } 6176 void Vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6177 Vmax(al, dt, rd, rn, rm); 6178 } 6179 6180 void Vmax( 6181 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6182 VIXL_ASSERT(allow_macro_instructions_); 6183 VIXL_ASSERT(OutsideITBlock()); 6184 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6185 ITScope it_scope(this, &cond); 6186 vmax(cond, dt, rd, rn, rm); 6187 } 6188 void Vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6189 Vmax(al, dt, rd, rn, rm); 6190 } 6191 6192 void Vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6193 VIXL_ASSERT(allow_macro_instructions_); 6194 VIXL_ASSERT(OutsideITBlock()); 6195 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6196 vmaxnm(dt, rd, rn, rm); 6197 } 6198 6199 void Vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6200 VIXL_ASSERT(allow_macro_instructions_); 6201 VIXL_ASSERT(OutsideITBlock()); 6202 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6203 vmaxnm(dt, rd, rn, rm); 6204 } 6205 6206 void Vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6207 VIXL_ASSERT(allow_macro_instructions_); 6208 VIXL_ASSERT(OutsideITBlock()); 6209 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6210 vmaxnm(dt, rd, rn, rm); 6211 } 6212 6213 void Vmin( 6214 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6215 VIXL_ASSERT(allow_macro_instructions_); 6216 VIXL_ASSERT(OutsideITBlock()); 6217 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6218 ITScope it_scope(this, &cond); 6219 vmin(cond, dt, rd, rn, rm); 6220 } 6221 void Vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6222 Vmin(al, dt, rd, rn, rm); 6223 } 6224 6225 void Vmin( 6226 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6227 VIXL_ASSERT(allow_macro_instructions_); 6228 VIXL_ASSERT(OutsideITBlock()); 6229 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6230 ITScope it_scope(this, &cond); 6231 vmin(cond, dt, rd, rn, rm); 6232 } 6233 void Vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6234 Vmin(al, dt, rd, rn, rm); 6235 } 6236 6237 void Vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6238 VIXL_ASSERT(allow_macro_instructions_); 6239 VIXL_ASSERT(OutsideITBlock()); 6240 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6241 vminnm(dt, rd, rn, rm); 6242 } 6243 6244 void Vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6245 VIXL_ASSERT(allow_macro_instructions_); 6246 VIXL_ASSERT(OutsideITBlock()); 6247 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6248 vminnm(dt, rd, rn, rm); 6249 } 6250 6251 void Vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6252 VIXL_ASSERT(allow_macro_instructions_); 6253 VIXL_ASSERT(OutsideITBlock()); 6254 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6255 vminnm(dt, rd, rn, rm); 6256 } 6257 6258 void Vmla(Condition cond, 6259 DataType dt, 6260 DRegister rd, 6261 DRegister rn, 6262 DRegisterLane rm) { 6263 VIXL_ASSERT(allow_macro_instructions_); 6264 VIXL_ASSERT(OutsideITBlock()); 6265 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6266 ITScope it_scope(this, &cond); 6267 vmla(cond, dt, rd, rn, rm); 6268 } 6269 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 6270 Vmla(al, dt, rd, rn, rm); 6271 } 6272 6273 void Vmla(Condition cond, 6274 DataType dt, 6275 QRegister rd, 6276 QRegister rn, 6277 DRegisterLane rm) { 6278 VIXL_ASSERT(allow_macro_instructions_); 6279 VIXL_ASSERT(OutsideITBlock()); 6280 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6281 ITScope it_scope(this, &cond); 6282 vmla(cond, dt, rd, rn, rm); 6283 } 6284 void Vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 6285 Vmla(al, dt, rd, rn, rm); 6286 } 6287 6288 void Vmla( 6289 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6290 VIXL_ASSERT(allow_macro_instructions_); 6291 VIXL_ASSERT(OutsideITBlock()); 6292 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6293 ITScope it_scope(this, &cond); 6294 vmla(cond, dt, rd, rn, rm); 6295 } 6296 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6297 Vmla(al, dt, rd, rn, rm); 6298 } 6299 6300 void Vmla( 6301 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6302 VIXL_ASSERT(allow_macro_instructions_); 6303 VIXL_ASSERT(OutsideITBlock()); 6304 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6305 ITScope it_scope(this, &cond); 6306 vmla(cond, dt, rd, rn, rm); 6307 } 6308 void Vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6309 Vmla(al, dt, rd, rn, rm); 6310 } 6311 6312 void Vmla( 6313 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6314 VIXL_ASSERT(allow_macro_instructions_); 6315 VIXL_ASSERT(OutsideITBlock()); 6316 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6317 ITScope it_scope(this, &cond); 6318 vmla(cond, dt, rd, rn, rm); 6319 } 6320 void Vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6321 Vmla(al, dt, rd, rn, rm); 6322 } 6323 6324 void Vmlal(Condition cond, 6325 DataType dt, 6326 QRegister rd, 6327 DRegister rn, 6328 DRegisterLane rm) { 6329 VIXL_ASSERT(allow_macro_instructions_); 6330 VIXL_ASSERT(OutsideITBlock()); 6331 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6332 ITScope it_scope(this, &cond); 6333 vmlal(cond, dt, rd, rn, rm); 6334 } 6335 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 6336 Vmlal(al, dt, rd, rn, rm); 6337 } 6338 6339 void Vmlal( 6340 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6341 VIXL_ASSERT(allow_macro_instructions_); 6342 VIXL_ASSERT(OutsideITBlock()); 6343 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6344 ITScope it_scope(this, &cond); 6345 vmlal(cond, dt, rd, rn, rm); 6346 } 6347 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6348 Vmlal(al, dt, rd, rn, rm); 6349 } 6350 6351 void Vmls(Condition cond, 6352 DataType dt, 6353 DRegister rd, 6354 DRegister rn, 6355 DRegisterLane rm) { 6356 VIXL_ASSERT(allow_macro_instructions_); 6357 VIXL_ASSERT(OutsideITBlock()); 6358 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6359 ITScope it_scope(this, &cond); 6360 vmls(cond, dt, rd, rn, rm); 6361 } 6362 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 6363 Vmls(al, dt, rd, rn, rm); 6364 } 6365 6366 void Vmls(Condition cond, 6367 DataType dt, 6368 QRegister rd, 6369 QRegister rn, 6370 DRegisterLane rm) { 6371 VIXL_ASSERT(allow_macro_instructions_); 6372 VIXL_ASSERT(OutsideITBlock()); 6373 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6374 ITScope it_scope(this, &cond); 6375 vmls(cond, dt, rd, rn, rm); 6376 } 6377 void Vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 6378 Vmls(al, dt, rd, rn, rm); 6379 } 6380 6381 void Vmls( 6382 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6383 VIXL_ASSERT(allow_macro_instructions_); 6384 VIXL_ASSERT(OutsideITBlock()); 6385 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6386 ITScope it_scope(this, &cond); 6387 vmls(cond, dt, rd, rn, rm); 6388 } 6389 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6390 Vmls(al, dt, rd, rn, rm); 6391 } 6392 6393 void Vmls( 6394 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6395 VIXL_ASSERT(allow_macro_instructions_); 6396 VIXL_ASSERT(OutsideITBlock()); 6397 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6398 ITScope it_scope(this, &cond); 6399 vmls(cond, dt, rd, rn, rm); 6400 } 6401 void Vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6402 Vmls(al, dt, rd, rn, rm); 6403 } 6404 6405 void Vmls( 6406 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6407 VIXL_ASSERT(allow_macro_instructions_); 6408 VIXL_ASSERT(OutsideITBlock()); 6409 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6410 ITScope it_scope(this, &cond); 6411 vmls(cond, dt, rd, rn, rm); 6412 } 6413 void Vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6414 Vmls(al, dt, rd, rn, rm); 6415 } 6416 6417 void Vmlsl(Condition cond, 6418 DataType dt, 6419 QRegister rd, 6420 DRegister rn, 6421 DRegisterLane rm) { 6422 VIXL_ASSERT(allow_macro_instructions_); 6423 VIXL_ASSERT(OutsideITBlock()); 6424 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6425 ITScope it_scope(this, &cond); 6426 vmlsl(cond, dt, rd, rn, rm); 6427 } 6428 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 6429 Vmlsl(al, dt, rd, rn, rm); 6430 } 6431 6432 void Vmlsl( 6433 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6434 VIXL_ASSERT(allow_macro_instructions_); 6435 VIXL_ASSERT(OutsideITBlock()); 6436 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6437 ITScope it_scope(this, &cond); 6438 vmlsl(cond, dt, rd, rn, rm); 6439 } 6440 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6441 Vmlsl(al, dt, rd, rn, rm); 6442 } 6443 6444 void Vmov(Condition cond, Register rt, SRegister rn) { 6445 VIXL_ASSERT(allow_macro_instructions_); 6446 VIXL_ASSERT(OutsideITBlock()); 6447 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6448 ITScope it_scope(this, &cond); 6449 vmov(cond, rt, rn); 6450 } 6451 void Vmov(Register rt, SRegister rn) { Vmov(al, rt, rn); } 6452 6453 void Vmov(Condition cond, SRegister rn, Register rt) { 6454 VIXL_ASSERT(allow_macro_instructions_); 6455 VIXL_ASSERT(OutsideITBlock()); 6456 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6457 ITScope it_scope(this, &cond); 6458 vmov(cond, rn, rt); 6459 } 6460 void Vmov(SRegister rn, Register rt) { Vmov(al, rn, rt); } 6461 6462 void Vmov(Condition cond, Register rt, Register rt2, DRegister rm) { 6463 VIXL_ASSERT(allow_macro_instructions_); 6464 VIXL_ASSERT(OutsideITBlock()); 6465 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6466 ITScope it_scope(this, &cond); 6467 vmov(cond, rt, rt2, rm); 6468 } 6469 void Vmov(Register rt, Register rt2, DRegister rm) { Vmov(al, rt, rt2, rm); } 6470 6471 void Vmov(Condition cond, DRegister rm, Register rt, Register rt2) { 6472 VIXL_ASSERT(allow_macro_instructions_); 6473 VIXL_ASSERT(OutsideITBlock()); 6474 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6475 ITScope it_scope(this, &cond); 6476 vmov(cond, rm, rt, rt2); 6477 } 6478 void Vmov(DRegister rm, Register rt, Register rt2) { Vmov(al, rm, rt, rt2); } 6479 6480 void Vmov( 6481 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) { 6482 VIXL_ASSERT(allow_macro_instructions_); 6483 VIXL_ASSERT(OutsideITBlock()); 6484 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6485 ITScope it_scope(this, &cond); 6486 vmov(cond, rt, rt2, rm, rm1); 6487 } 6488 void Vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) { 6489 Vmov(al, rt, rt2, rm, rm1); 6490 } 6491 6492 void Vmov( 6493 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) { 6494 VIXL_ASSERT(allow_macro_instructions_); 6495 VIXL_ASSERT(OutsideITBlock()); 6496 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6497 ITScope it_scope(this, &cond); 6498 vmov(cond, rm, rm1, rt, rt2); 6499 } 6500 void Vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) { 6501 Vmov(al, rm, rm1, rt, rt2); 6502 } 6503 6504 void Vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt) { 6505 VIXL_ASSERT(allow_macro_instructions_); 6506 VIXL_ASSERT(OutsideITBlock()); 6507 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6508 ITScope it_scope(this, &cond); 6509 vmov(cond, dt, rd, rt); 6510 } 6511 void Vmov(DataType dt, DRegisterLane rd, Register rt) { 6512 Vmov(al, dt, rd, rt); 6513 } 6514 void Vmov(Condition cond, DRegisterLane rd, Register rt) { 6515 Vmov(cond, kDataTypeValueNone, rd, rt); 6516 } 6517 void Vmov(DRegisterLane rd, Register rt) { 6518 Vmov(al, kDataTypeValueNone, rd, rt); 6519 } 6520 6521 void Vmov(Condition cond, 6522 DataType dt, 6523 DRegister rd, 6524 const DOperand& operand) { 6525 VIXL_ASSERT(allow_macro_instructions_); 6526 VIXL_ASSERT(OutsideITBlock()); 6527 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6528 ITScope it_scope(this, &cond); 6529 vmov(cond, dt, rd, operand); 6530 } 6531 void Vmov(DataType dt, DRegister rd, const DOperand& operand) { 6532 Vmov(al, dt, rd, operand); 6533 } 6534 6535 void Vmov(Condition cond, 6536 DataType dt, 6537 QRegister rd, 6538 const QOperand& operand) { 6539 VIXL_ASSERT(allow_macro_instructions_); 6540 VIXL_ASSERT(OutsideITBlock()); 6541 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6542 ITScope it_scope(this, &cond); 6543 vmov(cond, dt, rd, operand); 6544 } 6545 void Vmov(DataType dt, QRegister rd, const QOperand& operand) { 6546 Vmov(al, dt, rd, operand); 6547 } 6548 6549 void Vmov(Condition cond, 6550 DataType dt, 6551 SRegister rd, 6552 const SOperand& operand) { 6553 VIXL_ASSERT(allow_macro_instructions_); 6554 VIXL_ASSERT(OutsideITBlock()); 6555 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6556 ITScope it_scope(this, &cond); 6557 vmov(cond, dt, rd, operand); 6558 } 6559 void Vmov(DataType dt, SRegister rd, const SOperand& operand) { 6560 Vmov(al, dt, rd, operand); 6561 } 6562 6563 void Vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn) { 6564 VIXL_ASSERT(allow_macro_instructions_); 6565 VIXL_ASSERT(OutsideITBlock()); 6566 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6567 ITScope it_scope(this, &cond); 6568 vmov(cond, dt, rt, rn); 6569 } 6570 void Vmov(DataType dt, Register rt, DRegisterLane rn) { 6571 Vmov(al, dt, rt, rn); 6572 } 6573 void Vmov(Condition cond, Register rt, DRegisterLane rn) { 6574 Vmov(cond, kDataTypeValueNone, rt, rn); 6575 } 6576 void Vmov(Register rt, DRegisterLane rn) { 6577 Vmov(al, kDataTypeValueNone, rt, rn); 6578 } 6579 6580 void Vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) { 6581 VIXL_ASSERT(allow_macro_instructions_); 6582 VIXL_ASSERT(OutsideITBlock()); 6583 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6584 ITScope it_scope(this, &cond); 6585 vmovl(cond, dt, rd, rm); 6586 } 6587 void Vmovl(DataType dt, QRegister rd, DRegister rm) { Vmovl(al, dt, rd, rm); } 6588 6589 void Vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) { 6590 VIXL_ASSERT(allow_macro_instructions_); 6591 VIXL_ASSERT(OutsideITBlock()); 6592 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6593 ITScope it_scope(this, &cond); 6594 vmovn(cond, dt, rd, rm); 6595 } 6596 void Vmovn(DataType dt, DRegister rd, QRegister rm) { Vmovn(al, dt, rd, rm); } 6597 6598 void Vmrs(Condition cond, 6599 RegisterOrAPSR_nzcv rt, 6600 SpecialFPRegister spec_reg) { 6601 VIXL_ASSERT(allow_macro_instructions_); 6602 VIXL_ASSERT(OutsideITBlock()); 6603 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6604 ITScope it_scope(this, &cond); 6605 vmrs(cond, rt, spec_reg); 6606 } 6607 void Vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) { 6608 Vmrs(al, rt, spec_reg); 6609 } 6610 6611 void Vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) { 6612 VIXL_ASSERT(allow_macro_instructions_); 6613 VIXL_ASSERT(OutsideITBlock()); 6614 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6615 ITScope it_scope(this, &cond); 6616 vmsr(cond, spec_reg, rt); 6617 } 6618 void Vmsr(SpecialFPRegister spec_reg, Register rt) { Vmsr(al, spec_reg, rt); } 6619 6620 void Vmul(Condition cond, 6621 DataType dt, 6622 DRegister rd, 6623 DRegister rn, 6624 DRegister dm, 6625 unsigned index) { 6626 VIXL_ASSERT(allow_macro_instructions_); 6627 VIXL_ASSERT(OutsideITBlock()); 6628 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6629 ITScope it_scope(this, &cond); 6630 vmul(cond, dt, rd, rn, dm, index); 6631 } 6632 void Vmul( 6633 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) { 6634 Vmul(al, dt, rd, rn, dm, index); 6635 } 6636 6637 void Vmul(Condition cond, 6638 DataType dt, 6639 QRegister rd, 6640 QRegister rn, 6641 DRegister dm, 6642 unsigned index) { 6643 VIXL_ASSERT(allow_macro_instructions_); 6644 VIXL_ASSERT(OutsideITBlock()); 6645 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6646 ITScope it_scope(this, &cond); 6647 vmul(cond, dt, rd, rn, dm, index); 6648 } 6649 void Vmul( 6650 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) { 6651 Vmul(al, dt, rd, rn, dm, index); 6652 } 6653 6654 void Vmul( 6655 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6656 VIXL_ASSERT(allow_macro_instructions_); 6657 VIXL_ASSERT(OutsideITBlock()); 6658 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6659 ITScope it_scope(this, &cond); 6660 vmul(cond, dt, rd, rn, rm); 6661 } 6662 void Vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6663 Vmul(al, dt, rd, rn, rm); 6664 } 6665 6666 void Vmul( 6667 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6668 VIXL_ASSERT(allow_macro_instructions_); 6669 VIXL_ASSERT(OutsideITBlock()); 6670 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6671 ITScope it_scope(this, &cond); 6672 vmul(cond, dt, rd, rn, rm); 6673 } 6674 void Vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6675 Vmul(al, dt, rd, rn, rm); 6676 } 6677 6678 void Vmul( 6679 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6680 VIXL_ASSERT(allow_macro_instructions_); 6681 VIXL_ASSERT(OutsideITBlock()); 6682 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6683 ITScope it_scope(this, &cond); 6684 vmul(cond, dt, rd, rn, rm); 6685 } 6686 void Vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6687 Vmul(al, dt, rd, rn, rm); 6688 } 6689 6690 void Vmull(Condition cond, 6691 DataType dt, 6692 QRegister rd, 6693 DRegister rn, 6694 DRegister dm, 6695 unsigned index) { 6696 VIXL_ASSERT(allow_macro_instructions_); 6697 VIXL_ASSERT(OutsideITBlock()); 6698 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6699 ITScope it_scope(this, &cond); 6700 vmull(cond, dt, rd, rn, dm, index); 6701 } 6702 void Vmull( 6703 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 6704 Vmull(al, dt, rd, rn, dm, index); 6705 } 6706 6707 void Vmull( 6708 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6709 VIXL_ASSERT(allow_macro_instructions_); 6710 VIXL_ASSERT(OutsideITBlock()); 6711 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6712 ITScope it_scope(this, &cond); 6713 vmull(cond, dt, rd, rn, rm); 6714 } 6715 void Vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6716 Vmull(al, dt, rd, rn, rm); 6717 } 6718 6719 void Vmvn(Condition cond, 6720 DataType dt, 6721 DRegister rd, 6722 const DOperand& operand) { 6723 VIXL_ASSERT(allow_macro_instructions_); 6724 VIXL_ASSERT(OutsideITBlock()); 6725 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6726 ITScope it_scope(this, &cond); 6727 vmvn(cond, dt, rd, operand); 6728 } 6729 void Vmvn(DataType dt, DRegister rd, const DOperand& operand) { 6730 Vmvn(al, dt, rd, operand); 6731 } 6732 6733 void Vmvn(Condition cond, 6734 DataType dt, 6735 QRegister rd, 6736 const QOperand& operand) { 6737 VIXL_ASSERT(allow_macro_instructions_); 6738 VIXL_ASSERT(OutsideITBlock()); 6739 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6740 ITScope it_scope(this, &cond); 6741 vmvn(cond, dt, rd, operand); 6742 } 6743 void Vmvn(DataType dt, QRegister rd, const QOperand& operand) { 6744 Vmvn(al, dt, rd, operand); 6745 } 6746 6747 void Vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6748 VIXL_ASSERT(allow_macro_instructions_); 6749 VIXL_ASSERT(OutsideITBlock()); 6750 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6751 ITScope it_scope(this, &cond); 6752 vneg(cond, dt, rd, rm); 6753 } 6754 void Vneg(DataType dt, DRegister rd, DRegister rm) { Vneg(al, dt, rd, rm); } 6755 6756 void Vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6757 VIXL_ASSERT(allow_macro_instructions_); 6758 VIXL_ASSERT(OutsideITBlock()); 6759 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6760 ITScope it_scope(this, &cond); 6761 vneg(cond, dt, rd, rm); 6762 } 6763 void Vneg(DataType dt, QRegister rd, QRegister rm) { Vneg(al, dt, rd, rm); } 6764 6765 void Vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) { 6766 VIXL_ASSERT(allow_macro_instructions_); 6767 VIXL_ASSERT(OutsideITBlock()); 6768 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6769 ITScope it_scope(this, &cond); 6770 vneg(cond, dt, rd, rm); 6771 } 6772 void Vneg(DataType dt, SRegister rd, SRegister rm) { Vneg(al, dt, rd, rm); } 6773 6774 void Vnmla( 6775 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6776 VIXL_ASSERT(allow_macro_instructions_); 6777 VIXL_ASSERT(OutsideITBlock()); 6778 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6779 ITScope it_scope(this, &cond); 6780 vnmla(cond, dt, rd, rn, rm); 6781 } 6782 void Vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6783 Vnmla(al, dt, rd, rn, rm); 6784 } 6785 6786 void Vnmla( 6787 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6788 VIXL_ASSERT(allow_macro_instructions_); 6789 VIXL_ASSERT(OutsideITBlock()); 6790 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6791 ITScope it_scope(this, &cond); 6792 vnmla(cond, dt, rd, rn, rm); 6793 } 6794 void Vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6795 Vnmla(al, dt, rd, rn, rm); 6796 } 6797 6798 void Vnmls( 6799 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6800 VIXL_ASSERT(allow_macro_instructions_); 6801 VIXL_ASSERT(OutsideITBlock()); 6802 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6803 ITScope it_scope(this, &cond); 6804 vnmls(cond, dt, rd, rn, rm); 6805 } 6806 void Vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6807 Vnmls(al, dt, rd, rn, rm); 6808 } 6809 6810 void Vnmls( 6811 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6812 VIXL_ASSERT(allow_macro_instructions_); 6813 VIXL_ASSERT(OutsideITBlock()); 6814 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6815 ITScope it_scope(this, &cond); 6816 vnmls(cond, dt, rd, rn, rm); 6817 } 6818 void Vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6819 Vnmls(al, dt, rd, rn, rm); 6820 } 6821 6822 void Vnmul( 6823 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6824 VIXL_ASSERT(allow_macro_instructions_); 6825 VIXL_ASSERT(OutsideITBlock()); 6826 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6827 ITScope it_scope(this, &cond); 6828 vnmul(cond, dt, rd, rn, rm); 6829 } 6830 void Vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6831 Vnmul(al, dt, rd, rn, rm); 6832 } 6833 6834 void Vnmul( 6835 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6836 VIXL_ASSERT(allow_macro_instructions_); 6837 VIXL_ASSERT(OutsideITBlock()); 6838 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6839 ITScope it_scope(this, &cond); 6840 vnmul(cond, dt, rd, rn, rm); 6841 } 6842 void Vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6843 Vnmul(al, dt, rd, rn, rm); 6844 } 6845 6846 void Vorn(Condition cond, 6847 DataType dt, 6848 DRegister rd, 6849 DRegister rn, 6850 const DOperand& operand) { 6851 VIXL_ASSERT(allow_macro_instructions_); 6852 VIXL_ASSERT(OutsideITBlock()); 6853 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6854 ITScope it_scope(this, &cond); 6855 vorn(cond, dt, rd, rn, operand); 6856 } 6857 void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 6858 Vorn(al, dt, rd, rn, operand); 6859 } 6860 6861 void Vorn(Condition cond, 6862 DataType dt, 6863 QRegister rd, 6864 QRegister rn, 6865 const QOperand& operand) { 6866 VIXL_ASSERT(allow_macro_instructions_); 6867 VIXL_ASSERT(OutsideITBlock()); 6868 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6869 ITScope it_scope(this, &cond); 6870 vorn(cond, dt, rd, rn, operand); 6871 } 6872 void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 6873 Vorn(al, dt, rd, rn, operand); 6874 } 6875 6876 void Vorr(Condition cond, 6877 DataType dt, 6878 DRegister rd, 6879 DRegister rn, 6880 const DOperand& operand) { 6881 VIXL_ASSERT(allow_macro_instructions_); 6882 VIXL_ASSERT(OutsideITBlock()); 6883 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6884 ITScope it_scope(this, &cond); 6885 vorr(cond, dt, rd, rn, operand); 6886 } 6887 void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 6888 Vorr(al, dt, rd, rn, operand); 6889 } 6890 void Vorr(Condition cond, 6891 DRegister rd, 6892 DRegister rn, 6893 const DOperand& operand) { 6894 Vorr(cond, kDataTypeValueNone, rd, rn, operand); 6895 } 6896 void Vorr(DRegister rd, DRegister rn, const DOperand& operand) { 6897 Vorr(al, kDataTypeValueNone, rd, rn, operand); 6898 } 6899 6900 void Vorr(Condition cond, 6901 DataType dt, 6902 QRegister rd, 6903 QRegister rn, 6904 const QOperand& operand) { 6905 VIXL_ASSERT(allow_macro_instructions_); 6906 VIXL_ASSERT(OutsideITBlock()); 6907 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6908 ITScope it_scope(this, &cond); 6909 vorr(cond, dt, rd, rn, operand); 6910 } 6911 void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 6912 Vorr(al, dt, rd, rn, operand); 6913 } 6914 void Vorr(Condition cond, 6915 QRegister rd, 6916 QRegister rn, 6917 const QOperand& operand) { 6918 Vorr(cond, kDataTypeValueNone, rd, rn, operand); 6919 } 6920 void Vorr(QRegister rd, QRegister rn, const QOperand& operand) { 6921 Vorr(al, kDataTypeValueNone, rd, rn, operand); 6922 } 6923 6924 void Vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6925 VIXL_ASSERT(allow_macro_instructions_); 6926 VIXL_ASSERT(OutsideITBlock()); 6927 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6928 ITScope it_scope(this, &cond); 6929 vpadal(cond, dt, rd, rm); 6930 } 6931 void Vpadal(DataType dt, DRegister rd, DRegister rm) { 6932 Vpadal(al, dt, rd, rm); 6933 } 6934 6935 void Vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6936 VIXL_ASSERT(allow_macro_instructions_); 6937 VIXL_ASSERT(OutsideITBlock()); 6938 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6939 ITScope it_scope(this, &cond); 6940 vpadal(cond, dt, rd, rm); 6941 } 6942 void Vpadal(DataType dt, QRegister rd, QRegister rm) { 6943 Vpadal(al, dt, rd, rm); 6944 } 6945 6946 void Vpadd( 6947 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6948 VIXL_ASSERT(allow_macro_instructions_); 6949 VIXL_ASSERT(OutsideITBlock()); 6950 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6951 ITScope it_scope(this, &cond); 6952 vpadd(cond, dt, rd, rn, rm); 6953 } 6954 void Vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6955 Vpadd(al, dt, rd, rn, rm); 6956 } 6957 6958 void Vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6959 VIXL_ASSERT(allow_macro_instructions_); 6960 VIXL_ASSERT(OutsideITBlock()); 6961 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6962 ITScope it_scope(this, &cond); 6963 vpaddl(cond, dt, rd, rm); 6964 } 6965 void Vpaddl(DataType dt, DRegister rd, DRegister rm) { 6966 Vpaddl(al, dt, rd, rm); 6967 } 6968 6969 void Vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6970 VIXL_ASSERT(allow_macro_instructions_); 6971 VIXL_ASSERT(OutsideITBlock()); 6972 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6973 ITScope it_scope(this, &cond); 6974 vpaddl(cond, dt, rd, rm); 6975 } 6976 void Vpaddl(DataType dt, QRegister rd, QRegister rm) { 6977 Vpaddl(al, dt, rd, rm); 6978 } 6979 6980 void Vpmax( 6981 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6982 VIXL_ASSERT(allow_macro_instructions_); 6983 VIXL_ASSERT(OutsideITBlock()); 6984 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6985 ITScope it_scope(this, &cond); 6986 vpmax(cond, dt, rd, rn, rm); 6987 } 6988 void Vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6989 Vpmax(al, dt, rd, rn, rm); 6990 } 6991 6992 void Vpmin( 6993 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6994 VIXL_ASSERT(allow_macro_instructions_); 6995 VIXL_ASSERT(OutsideITBlock()); 6996 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 6997 ITScope it_scope(this, &cond); 6998 vpmin(cond, dt, rd, rn, rm); 6999 } 7000 void Vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7001 Vpmin(al, dt, rd, rn, rm); 7002 } 7003 7004 void Vpop(Condition cond, DataType dt, DRegisterList dreglist) { 7005 VIXL_ASSERT(allow_macro_instructions_); 7006 VIXL_ASSERT(OutsideITBlock()); 7007 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7008 ITScope it_scope(this, &cond); 7009 vpop(cond, dt, dreglist); 7010 } 7011 void Vpop(DataType dt, DRegisterList dreglist) { Vpop(al, dt, dreglist); } 7012 void Vpop(Condition cond, DRegisterList dreglist) { 7013 Vpop(cond, kDataTypeValueNone, dreglist); 7014 } 7015 void Vpop(DRegisterList dreglist) { Vpop(al, kDataTypeValueNone, dreglist); } 7016 7017 void Vpop(Condition cond, DataType dt, SRegisterList sreglist) { 7018 VIXL_ASSERT(allow_macro_instructions_); 7019 VIXL_ASSERT(OutsideITBlock()); 7020 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7021 ITScope it_scope(this, &cond); 7022 vpop(cond, dt, sreglist); 7023 } 7024 void Vpop(DataType dt, SRegisterList sreglist) { Vpop(al, dt, sreglist); } 7025 void Vpop(Condition cond, SRegisterList sreglist) { 7026 Vpop(cond, kDataTypeValueNone, sreglist); 7027 } 7028 void Vpop(SRegisterList sreglist) { Vpop(al, kDataTypeValueNone, sreglist); } 7029 7030 void Vpush(Condition cond, DataType dt, DRegisterList dreglist) { 7031 VIXL_ASSERT(allow_macro_instructions_); 7032 VIXL_ASSERT(OutsideITBlock()); 7033 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7034 ITScope it_scope(this, &cond); 7035 vpush(cond, dt, dreglist); 7036 } 7037 void Vpush(DataType dt, DRegisterList dreglist) { Vpush(al, dt, dreglist); } 7038 void Vpush(Condition cond, DRegisterList dreglist) { 7039 Vpush(cond, kDataTypeValueNone, dreglist); 7040 } 7041 void Vpush(DRegisterList dreglist) { 7042 Vpush(al, kDataTypeValueNone, dreglist); 7043 } 7044 7045 void Vpush(Condition cond, DataType dt, SRegisterList sreglist) { 7046 VIXL_ASSERT(allow_macro_instructions_); 7047 VIXL_ASSERT(OutsideITBlock()); 7048 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7049 ITScope it_scope(this, &cond); 7050 vpush(cond, dt, sreglist); 7051 } 7052 void Vpush(DataType dt, SRegisterList sreglist) { Vpush(al, dt, sreglist); } 7053 void Vpush(Condition cond, SRegisterList sreglist) { 7054 Vpush(cond, kDataTypeValueNone, sreglist); 7055 } 7056 void Vpush(SRegisterList sreglist) { 7057 Vpush(al, kDataTypeValueNone, sreglist); 7058 } 7059 7060 void Vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7061 VIXL_ASSERT(allow_macro_instructions_); 7062 VIXL_ASSERT(OutsideITBlock()); 7063 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7064 ITScope it_scope(this, &cond); 7065 vqabs(cond, dt, rd, rm); 7066 } 7067 void Vqabs(DataType dt, DRegister rd, DRegister rm) { Vqabs(al, dt, rd, rm); } 7068 7069 void Vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7070 VIXL_ASSERT(allow_macro_instructions_); 7071 VIXL_ASSERT(OutsideITBlock()); 7072 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7073 ITScope it_scope(this, &cond); 7074 vqabs(cond, dt, rd, rm); 7075 } 7076 void Vqabs(DataType dt, QRegister rd, QRegister rm) { Vqabs(al, dt, rd, rm); } 7077 7078 void Vqadd( 7079 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7080 VIXL_ASSERT(allow_macro_instructions_); 7081 VIXL_ASSERT(OutsideITBlock()); 7082 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7083 ITScope it_scope(this, &cond); 7084 vqadd(cond, dt, rd, rn, rm); 7085 } 7086 void Vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7087 Vqadd(al, dt, rd, rn, rm); 7088 } 7089 7090 void Vqadd( 7091 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7092 VIXL_ASSERT(allow_macro_instructions_); 7093 VIXL_ASSERT(OutsideITBlock()); 7094 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7095 ITScope it_scope(this, &cond); 7096 vqadd(cond, dt, rd, rn, rm); 7097 } 7098 void Vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7099 Vqadd(al, dt, rd, rn, rm); 7100 } 7101 7102 void Vqdmlal( 7103 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7104 VIXL_ASSERT(allow_macro_instructions_); 7105 VIXL_ASSERT(OutsideITBlock()); 7106 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7107 ITScope it_scope(this, &cond); 7108 vqdmlal(cond, dt, rd, rn, rm); 7109 } 7110 void Vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7111 Vqdmlal(al, dt, rd, rn, rm); 7112 } 7113 7114 void Vqdmlal(Condition cond, 7115 DataType dt, 7116 QRegister rd, 7117 DRegister rn, 7118 DRegister dm, 7119 unsigned index) { 7120 VIXL_ASSERT(allow_macro_instructions_); 7121 VIXL_ASSERT(OutsideITBlock()); 7122 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7123 ITScope it_scope(this, &cond); 7124 vqdmlal(cond, dt, rd, rn, dm, index); 7125 } 7126 void Vqdmlal( 7127 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 7128 Vqdmlal(al, dt, rd, rn, dm, index); 7129 } 7130 7131 void Vqdmlsl( 7132 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7133 VIXL_ASSERT(allow_macro_instructions_); 7134 VIXL_ASSERT(OutsideITBlock()); 7135 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7136 ITScope it_scope(this, &cond); 7137 vqdmlsl(cond, dt, rd, rn, rm); 7138 } 7139 void Vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7140 Vqdmlsl(al, dt, rd, rn, rm); 7141 } 7142 7143 void Vqdmlsl(Condition cond, 7144 DataType dt, 7145 QRegister rd, 7146 DRegister rn, 7147 DRegister dm, 7148 unsigned index) { 7149 VIXL_ASSERT(allow_macro_instructions_); 7150 VIXL_ASSERT(OutsideITBlock()); 7151 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7152 ITScope it_scope(this, &cond); 7153 vqdmlsl(cond, dt, rd, rn, dm, index); 7154 } 7155 void Vqdmlsl( 7156 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 7157 Vqdmlsl(al, dt, rd, rn, dm, index); 7158 } 7159 7160 void Vqdmulh( 7161 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7162 VIXL_ASSERT(allow_macro_instructions_); 7163 VIXL_ASSERT(OutsideITBlock()); 7164 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7165 ITScope it_scope(this, &cond); 7166 vqdmulh(cond, dt, rd, rn, rm); 7167 } 7168 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7169 Vqdmulh(al, dt, rd, rn, rm); 7170 } 7171 7172 void Vqdmulh( 7173 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7174 VIXL_ASSERT(allow_macro_instructions_); 7175 VIXL_ASSERT(OutsideITBlock()); 7176 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7177 ITScope it_scope(this, &cond); 7178 vqdmulh(cond, dt, rd, rn, rm); 7179 } 7180 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7181 Vqdmulh(al, dt, rd, rn, rm); 7182 } 7183 7184 void Vqdmulh(Condition cond, 7185 DataType dt, 7186 DRegister rd, 7187 DRegister rn, 7188 DRegisterLane rm) { 7189 VIXL_ASSERT(allow_macro_instructions_); 7190 VIXL_ASSERT(OutsideITBlock()); 7191 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7192 ITScope it_scope(this, &cond); 7193 vqdmulh(cond, dt, rd, rn, rm); 7194 } 7195 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 7196 Vqdmulh(al, dt, rd, rn, rm); 7197 } 7198 7199 void Vqdmulh(Condition cond, 7200 DataType dt, 7201 QRegister rd, 7202 QRegister rn, 7203 DRegisterLane rm) { 7204 VIXL_ASSERT(allow_macro_instructions_); 7205 VIXL_ASSERT(OutsideITBlock()); 7206 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7207 ITScope it_scope(this, &cond); 7208 vqdmulh(cond, dt, rd, rn, rm); 7209 } 7210 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 7211 Vqdmulh(al, dt, rd, rn, rm); 7212 } 7213 7214 void Vqdmull( 7215 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7216 VIXL_ASSERT(allow_macro_instructions_); 7217 VIXL_ASSERT(OutsideITBlock()); 7218 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7219 ITScope it_scope(this, &cond); 7220 vqdmull(cond, dt, rd, rn, rm); 7221 } 7222 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7223 Vqdmull(al, dt, rd, rn, rm); 7224 } 7225 7226 void Vqdmull(Condition cond, 7227 DataType dt, 7228 QRegister rd, 7229 DRegister rn, 7230 DRegisterLane rm) { 7231 VIXL_ASSERT(allow_macro_instructions_); 7232 VIXL_ASSERT(OutsideITBlock()); 7233 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7234 ITScope it_scope(this, &cond); 7235 vqdmull(cond, dt, rd, rn, rm); 7236 } 7237 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 7238 Vqdmull(al, dt, rd, rn, rm); 7239 } 7240 7241 void Vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) { 7242 VIXL_ASSERT(allow_macro_instructions_); 7243 VIXL_ASSERT(OutsideITBlock()); 7244 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7245 ITScope it_scope(this, &cond); 7246 vqmovn(cond, dt, rd, rm); 7247 } 7248 void Vqmovn(DataType dt, DRegister rd, QRegister rm) { 7249 Vqmovn(al, dt, rd, rm); 7250 } 7251 7252 void Vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm) { 7253 VIXL_ASSERT(allow_macro_instructions_); 7254 VIXL_ASSERT(OutsideITBlock()); 7255 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7256 ITScope it_scope(this, &cond); 7257 vqmovun(cond, dt, rd, rm); 7258 } 7259 void Vqmovun(DataType dt, DRegister rd, QRegister rm) { 7260 Vqmovun(al, dt, rd, rm); 7261 } 7262 7263 void Vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7264 VIXL_ASSERT(allow_macro_instructions_); 7265 VIXL_ASSERT(OutsideITBlock()); 7266 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7267 ITScope it_scope(this, &cond); 7268 vqneg(cond, dt, rd, rm); 7269 } 7270 void Vqneg(DataType dt, DRegister rd, DRegister rm) { Vqneg(al, dt, rd, rm); } 7271 7272 void Vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7273 VIXL_ASSERT(allow_macro_instructions_); 7274 VIXL_ASSERT(OutsideITBlock()); 7275 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7276 ITScope it_scope(this, &cond); 7277 vqneg(cond, dt, rd, rm); 7278 } 7279 void Vqneg(DataType dt, QRegister rd, QRegister rm) { Vqneg(al, dt, rd, rm); } 7280 7281 void Vqrdmulh( 7282 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7283 VIXL_ASSERT(allow_macro_instructions_); 7284 VIXL_ASSERT(OutsideITBlock()); 7285 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7286 ITScope it_scope(this, &cond); 7287 vqrdmulh(cond, dt, rd, rn, rm); 7288 } 7289 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7290 Vqrdmulh(al, dt, rd, rn, rm); 7291 } 7292 7293 void Vqrdmulh( 7294 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7295 VIXL_ASSERT(allow_macro_instructions_); 7296 VIXL_ASSERT(OutsideITBlock()); 7297 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7298 ITScope it_scope(this, &cond); 7299 vqrdmulh(cond, dt, rd, rn, rm); 7300 } 7301 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7302 Vqrdmulh(al, dt, rd, rn, rm); 7303 } 7304 7305 void Vqrdmulh(Condition cond, 7306 DataType dt, 7307 DRegister rd, 7308 DRegister rn, 7309 DRegisterLane rm) { 7310 VIXL_ASSERT(allow_macro_instructions_); 7311 VIXL_ASSERT(OutsideITBlock()); 7312 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7313 ITScope it_scope(this, &cond); 7314 vqrdmulh(cond, dt, rd, rn, rm); 7315 } 7316 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 7317 Vqrdmulh(al, dt, rd, rn, rm); 7318 } 7319 7320 void Vqrdmulh(Condition cond, 7321 DataType dt, 7322 QRegister rd, 7323 QRegister rn, 7324 DRegisterLane rm) { 7325 VIXL_ASSERT(allow_macro_instructions_); 7326 VIXL_ASSERT(OutsideITBlock()); 7327 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7328 ITScope it_scope(this, &cond); 7329 vqrdmulh(cond, dt, rd, rn, rm); 7330 } 7331 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 7332 Vqrdmulh(al, dt, rd, rn, rm); 7333 } 7334 7335 void Vqrshl( 7336 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { 7337 VIXL_ASSERT(allow_macro_instructions_); 7338 VIXL_ASSERT(OutsideITBlock()); 7339 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7340 ITScope it_scope(this, &cond); 7341 vqrshl(cond, dt, rd, rm, rn); 7342 } 7343 void Vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 7344 Vqrshl(al, dt, rd, rm, rn); 7345 } 7346 7347 void Vqrshl( 7348 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { 7349 VIXL_ASSERT(allow_macro_instructions_); 7350 VIXL_ASSERT(OutsideITBlock()); 7351 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7352 ITScope it_scope(this, &cond); 7353 vqrshl(cond, dt, rd, rm, rn); 7354 } 7355 void Vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 7356 Vqrshl(al, dt, rd, rm, rn); 7357 } 7358 7359 void Vqrshrn(Condition cond, 7360 DataType dt, 7361 DRegister rd, 7362 QRegister rm, 7363 const QOperand& operand) { 7364 VIXL_ASSERT(allow_macro_instructions_); 7365 VIXL_ASSERT(OutsideITBlock()); 7366 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7367 ITScope it_scope(this, &cond); 7368 vqrshrn(cond, dt, rd, rm, operand); 7369 } 7370 void Vqrshrn(DataType dt, 7371 DRegister rd, 7372 QRegister rm, 7373 const QOperand& operand) { 7374 Vqrshrn(al, dt, rd, rm, operand); 7375 } 7376 7377 void Vqrshrun(Condition cond, 7378 DataType dt, 7379 DRegister rd, 7380 QRegister rm, 7381 const QOperand& operand) { 7382 VIXL_ASSERT(allow_macro_instructions_); 7383 VIXL_ASSERT(OutsideITBlock()); 7384 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7385 ITScope it_scope(this, &cond); 7386 vqrshrun(cond, dt, rd, rm, operand); 7387 } 7388 void Vqrshrun(DataType dt, 7389 DRegister rd, 7390 QRegister rm, 7391 const QOperand& operand) { 7392 Vqrshrun(al, dt, rd, rm, operand); 7393 } 7394 7395 void Vqshl(Condition cond, 7396 DataType dt, 7397 DRegister rd, 7398 DRegister rm, 7399 const DOperand& operand) { 7400 VIXL_ASSERT(allow_macro_instructions_); 7401 VIXL_ASSERT(OutsideITBlock()); 7402 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7403 ITScope it_scope(this, &cond); 7404 vqshl(cond, dt, rd, rm, operand); 7405 } 7406 void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 7407 Vqshl(al, dt, rd, rm, operand); 7408 } 7409 7410 void Vqshl(Condition cond, 7411 DataType dt, 7412 QRegister rd, 7413 QRegister rm, 7414 const QOperand& operand) { 7415 VIXL_ASSERT(allow_macro_instructions_); 7416 VIXL_ASSERT(OutsideITBlock()); 7417 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7418 ITScope it_scope(this, &cond); 7419 vqshl(cond, dt, rd, rm, operand); 7420 } 7421 void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 7422 Vqshl(al, dt, rd, rm, operand); 7423 } 7424 7425 void Vqshlu(Condition cond, 7426 DataType dt, 7427 DRegister rd, 7428 DRegister rm, 7429 const DOperand& operand) { 7430 VIXL_ASSERT(allow_macro_instructions_); 7431 VIXL_ASSERT(OutsideITBlock()); 7432 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7433 ITScope it_scope(this, &cond); 7434 vqshlu(cond, dt, rd, rm, operand); 7435 } 7436 void Vqshlu(DataType dt, 7437 DRegister rd, 7438 DRegister rm, 7439 const DOperand& operand) { 7440 Vqshlu(al, dt, rd, rm, operand); 7441 } 7442 7443 void Vqshlu(Condition cond, 7444 DataType dt, 7445 QRegister rd, 7446 QRegister rm, 7447 const QOperand& operand) { 7448 VIXL_ASSERT(allow_macro_instructions_); 7449 VIXL_ASSERT(OutsideITBlock()); 7450 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7451 ITScope it_scope(this, &cond); 7452 vqshlu(cond, dt, rd, rm, operand); 7453 } 7454 void Vqshlu(DataType dt, 7455 QRegister rd, 7456 QRegister rm, 7457 const QOperand& operand) { 7458 Vqshlu(al, dt, rd, rm, operand); 7459 } 7460 7461 void Vqshrn(Condition cond, 7462 DataType dt, 7463 DRegister rd, 7464 QRegister rm, 7465 const QOperand& operand) { 7466 VIXL_ASSERT(allow_macro_instructions_); 7467 VIXL_ASSERT(OutsideITBlock()); 7468 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7469 ITScope it_scope(this, &cond); 7470 vqshrn(cond, dt, rd, rm, operand); 7471 } 7472 void Vqshrn(DataType dt, 7473 DRegister rd, 7474 QRegister rm, 7475 const QOperand& operand) { 7476 Vqshrn(al, dt, rd, rm, operand); 7477 } 7478 7479 void Vqshrun(Condition cond, 7480 DataType dt, 7481 DRegister rd, 7482 QRegister rm, 7483 const QOperand& operand) { 7484 VIXL_ASSERT(allow_macro_instructions_); 7485 VIXL_ASSERT(OutsideITBlock()); 7486 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7487 ITScope it_scope(this, &cond); 7488 vqshrun(cond, dt, rd, rm, operand); 7489 } 7490 void Vqshrun(DataType dt, 7491 DRegister rd, 7492 QRegister rm, 7493 const QOperand& operand) { 7494 Vqshrun(al, dt, rd, rm, operand); 7495 } 7496 7497 void Vqsub( 7498 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7499 VIXL_ASSERT(allow_macro_instructions_); 7500 VIXL_ASSERT(OutsideITBlock()); 7501 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7502 ITScope it_scope(this, &cond); 7503 vqsub(cond, dt, rd, rn, rm); 7504 } 7505 void Vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7506 Vqsub(al, dt, rd, rn, rm); 7507 } 7508 7509 void Vqsub( 7510 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7511 VIXL_ASSERT(allow_macro_instructions_); 7512 VIXL_ASSERT(OutsideITBlock()); 7513 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7514 ITScope it_scope(this, &cond); 7515 vqsub(cond, dt, rd, rn, rm); 7516 } 7517 void Vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7518 Vqsub(al, dt, rd, rn, rm); 7519 } 7520 7521 void Vraddhn( 7522 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 7523 VIXL_ASSERT(allow_macro_instructions_); 7524 VIXL_ASSERT(OutsideITBlock()); 7525 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7526 ITScope it_scope(this, &cond); 7527 vraddhn(cond, dt, rd, rn, rm); 7528 } 7529 void Vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 7530 Vraddhn(al, dt, rd, rn, rm); 7531 } 7532 7533 void Vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7534 VIXL_ASSERT(allow_macro_instructions_); 7535 VIXL_ASSERT(OutsideITBlock()); 7536 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7537 ITScope it_scope(this, &cond); 7538 vrecpe(cond, dt, rd, rm); 7539 } 7540 void Vrecpe(DataType dt, DRegister rd, DRegister rm) { 7541 Vrecpe(al, dt, rd, rm); 7542 } 7543 7544 void Vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7545 VIXL_ASSERT(allow_macro_instructions_); 7546 VIXL_ASSERT(OutsideITBlock()); 7547 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7548 ITScope it_scope(this, &cond); 7549 vrecpe(cond, dt, rd, rm); 7550 } 7551 void Vrecpe(DataType dt, QRegister rd, QRegister rm) { 7552 Vrecpe(al, dt, rd, rm); 7553 } 7554 7555 void Vrecps( 7556 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7557 VIXL_ASSERT(allow_macro_instructions_); 7558 VIXL_ASSERT(OutsideITBlock()); 7559 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7560 ITScope it_scope(this, &cond); 7561 vrecps(cond, dt, rd, rn, rm); 7562 } 7563 void Vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7564 Vrecps(al, dt, rd, rn, rm); 7565 } 7566 7567 void Vrecps( 7568 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7569 VIXL_ASSERT(allow_macro_instructions_); 7570 VIXL_ASSERT(OutsideITBlock()); 7571 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7572 ITScope it_scope(this, &cond); 7573 vrecps(cond, dt, rd, rn, rm); 7574 } 7575 void Vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7576 Vrecps(al, dt, rd, rn, rm); 7577 } 7578 7579 void Vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7580 VIXL_ASSERT(allow_macro_instructions_); 7581 VIXL_ASSERT(OutsideITBlock()); 7582 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7583 ITScope it_scope(this, &cond); 7584 vrev16(cond, dt, rd, rm); 7585 } 7586 void Vrev16(DataType dt, DRegister rd, DRegister rm) { 7587 Vrev16(al, dt, rd, rm); 7588 } 7589 7590 void Vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7591 VIXL_ASSERT(allow_macro_instructions_); 7592 VIXL_ASSERT(OutsideITBlock()); 7593 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7594 ITScope it_scope(this, &cond); 7595 vrev16(cond, dt, rd, rm); 7596 } 7597 void Vrev16(DataType dt, QRegister rd, QRegister rm) { 7598 Vrev16(al, dt, rd, rm); 7599 } 7600 7601 void Vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7602 VIXL_ASSERT(allow_macro_instructions_); 7603 VIXL_ASSERT(OutsideITBlock()); 7604 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7605 ITScope it_scope(this, &cond); 7606 vrev32(cond, dt, rd, rm); 7607 } 7608 void Vrev32(DataType dt, DRegister rd, DRegister rm) { 7609 Vrev32(al, dt, rd, rm); 7610 } 7611 7612 void Vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7613 VIXL_ASSERT(allow_macro_instructions_); 7614 VIXL_ASSERT(OutsideITBlock()); 7615 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7616 ITScope it_scope(this, &cond); 7617 vrev32(cond, dt, rd, rm); 7618 } 7619 void Vrev32(DataType dt, QRegister rd, QRegister rm) { 7620 Vrev32(al, dt, rd, rm); 7621 } 7622 7623 void Vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7624 VIXL_ASSERT(allow_macro_instructions_); 7625 VIXL_ASSERT(OutsideITBlock()); 7626 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7627 ITScope it_scope(this, &cond); 7628 vrev64(cond, dt, rd, rm); 7629 } 7630 void Vrev64(DataType dt, DRegister rd, DRegister rm) { 7631 Vrev64(al, dt, rd, rm); 7632 } 7633 7634 void Vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7635 VIXL_ASSERT(allow_macro_instructions_); 7636 VIXL_ASSERT(OutsideITBlock()); 7637 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7638 ITScope it_scope(this, &cond); 7639 vrev64(cond, dt, rd, rm); 7640 } 7641 void Vrev64(DataType dt, QRegister rd, QRegister rm) { 7642 Vrev64(al, dt, rd, rm); 7643 } 7644 7645 void Vrhadd( 7646 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7647 VIXL_ASSERT(allow_macro_instructions_); 7648 VIXL_ASSERT(OutsideITBlock()); 7649 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7650 ITScope it_scope(this, &cond); 7651 vrhadd(cond, dt, rd, rn, rm); 7652 } 7653 void Vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7654 Vrhadd(al, dt, rd, rn, rm); 7655 } 7656 7657 void Vrhadd( 7658 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7659 VIXL_ASSERT(allow_macro_instructions_); 7660 VIXL_ASSERT(OutsideITBlock()); 7661 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7662 ITScope it_scope(this, &cond); 7663 vrhadd(cond, dt, rd, rn, rm); 7664 } 7665 void Vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7666 Vrhadd(al, dt, rd, rn, rm); 7667 } 7668 7669 void Vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7670 VIXL_ASSERT(allow_macro_instructions_); 7671 VIXL_ASSERT(OutsideITBlock()); 7672 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7673 vrinta(dt1, dt2, rd, rm); 7674 } 7675 7676 void Vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 7677 VIXL_ASSERT(allow_macro_instructions_); 7678 VIXL_ASSERT(OutsideITBlock()); 7679 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7680 vrinta(dt1, dt2, rd, rm); 7681 } 7682 7683 void Vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7684 VIXL_ASSERT(allow_macro_instructions_); 7685 VIXL_ASSERT(OutsideITBlock()); 7686 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7687 vrinta(dt1, dt2, rd, rm); 7688 } 7689 7690 void Vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7691 VIXL_ASSERT(allow_macro_instructions_); 7692 VIXL_ASSERT(OutsideITBlock()); 7693 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7694 vrintm(dt1, dt2, rd, rm); 7695 } 7696 7697 void Vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 7698 VIXL_ASSERT(allow_macro_instructions_); 7699 VIXL_ASSERT(OutsideITBlock()); 7700 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7701 vrintm(dt1, dt2, rd, rm); 7702 } 7703 7704 void Vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7705 VIXL_ASSERT(allow_macro_instructions_); 7706 VIXL_ASSERT(OutsideITBlock()); 7707 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7708 vrintm(dt1, dt2, rd, rm); 7709 } 7710 7711 void Vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7712 VIXL_ASSERT(allow_macro_instructions_); 7713 VIXL_ASSERT(OutsideITBlock()); 7714 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7715 vrintn(dt1, dt2, rd, rm); 7716 } 7717 7718 void Vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 7719 VIXL_ASSERT(allow_macro_instructions_); 7720 VIXL_ASSERT(OutsideITBlock()); 7721 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7722 vrintn(dt1, dt2, rd, rm); 7723 } 7724 7725 void Vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7726 VIXL_ASSERT(allow_macro_instructions_); 7727 VIXL_ASSERT(OutsideITBlock()); 7728 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7729 vrintn(dt1, dt2, rd, rm); 7730 } 7731 7732 void Vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7733 VIXL_ASSERT(allow_macro_instructions_); 7734 VIXL_ASSERT(OutsideITBlock()); 7735 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7736 vrintp(dt1, dt2, rd, rm); 7737 } 7738 7739 void Vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 7740 VIXL_ASSERT(allow_macro_instructions_); 7741 VIXL_ASSERT(OutsideITBlock()); 7742 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7743 vrintp(dt1, dt2, rd, rm); 7744 } 7745 7746 void Vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7747 VIXL_ASSERT(allow_macro_instructions_); 7748 VIXL_ASSERT(OutsideITBlock()); 7749 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7750 vrintp(dt1, dt2, rd, rm); 7751 } 7752 7753 void Vrintr( 7754 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7755 VIXL_ASSERT(allow_macro_instructions_); 7756 VIXL_ASSERT(OutsideITBlock()); 7757 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7758 ITScope it_scope(this, &cond); 7759 vrintr(cond, dt1, dt2, rd, rm); 7760 } 7761 void Vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7762 Vrintr(al, dt1, dt2, rd, rm); 7763 } 7764 7765 void Vrintr( 7766 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7767 VIXL_ASSERT(allow_macro_instructions_); 7768 VIXL_ASSERT(OutsideITBlock()); 7769 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7770 ITScope it_scope(this, &cond); 7771 vrintr(cond, dt1, dt2, rd, rm); 7772 } 7773 void Vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7774 Vrintr(al, dt1, dt2, rd, rm); 7775 } 7776 7777 void Vrintx( 7778 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7779 VIXL_ASSERT(allow_macro_instructions_); 7780 VIXL_ASSERT(OutsideITBlock()); 7781 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7782 ITScope it_scope(this, &cond); 7783 vrintx(cond, dt1, dt2, rd, rm); 7784 } 7785 void Vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7786 Vrintx(al, dt1, dt2, rd, rm); 7787 } 7788 7789 void Vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 7790 VIXL_ASSERT(allow_macro_instructions_); 7791 VIXL_ASSERT(OutsideITBlock()); 7792 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7793 vrintx(dt1, dt2, rd, rm); 7794 } 7795 7796 void Vrintx( 7797 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7798 VIXL_ASSERT(allow_macro_instructions_); 7799 VIXL_ASSERT(OutsideITBlock()); 7800 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7801 ITScope it_scope(this, &cond); 7802 vrintx(cond, dt1, dt2, rd, rm); 7803 } 7804 void Vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7805 Vrintx(al, dt1, dt2, rd, rm); 7806 } 7807 7808 void Vrintz( 7809 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7810 VIXL_ASSERT(allow_macro_instructions_); 7811 VIXL_ASSERT(OutsideITBlock()); 7812 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7813 ITScope it_scope(this, &cond); 7814 vrintz(cond, dt1, dt2, rd, rm); 7815 } 7816 void Vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 7817 Vrintz(al, dt1, dt2, rd, rm); 7818 } 7819 7820 void Vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 7821 VIXL_ASSERT(allow_macro_instructions_); 7822 VIXL_ASSERT(OutsideITBlock()); 7823 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7824 vrintz(dt1, dt2, rd, rm); 7825 } 7826 7827 void Vrintz( 7828 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7829 VIXL_ASSERT(allow_macro_instructions_); 7830 VIXL_ASSERT(OutsideITBlock()); 7831 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7832 ITScope it_scope(this, &cond); 7833 vrintz(cond, dt1, dt2, rd, rm); 7834 } 7835 void Vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 7836 Vrintz(al, dt1, dt2, rd, rm); 7837 } 7838 7839 void Vrshl( 7840 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { 7841 VIXL_ASSERT(allow_macro_instructions_); 7842 VIXL_ASSERT(OutsideITBlock()); 7843 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7844 ITScope it_scope(this, &cond); 7845 vrshl(cond, dt, rd, rm, rn); 7846 } 7847 void Vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 7848 Vrshl(al, dt, rd, rm, rn); 7849 } 7850 7851 void Vrshl( 7852 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { 7853 VIXL_ASSERT(allow_macro_instructions_); 7854 VIXL_ASSERT(OutsideITBlock()); 7855 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7856 ITScope it_scope(this, &cond); 7857 vrshl(cond, dt, rd, rm, rn); 7858 } 7859 void Vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 7860 Vrshl(al, dt, rd, rm, rn); 7861 } 7862 7863 void Vrshr(Condition cond, 7864 DataType dt, 7865 DRegister rd, 7866 DRegister rm, 7867 const DOperand& operand) { 7868 VIXL_ASSERT(allow_macro_instructions_); 7869 VIXL_ASSERT(OutsideITBlock()); 7870 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7871 ITScope it_scope(this, &cond); 7872 vrshr(cond, dt, rd, rm, operand); 7873 } 7874 void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 7875 Vrshr(al, dt, rd, rm, operand); 7876 } 7877 7878 void Vrshr(Condition cond, 7879 DataType dt, 7880 QRegister rd, 7881 QRegister rm, 7882 const QOperand& operand) { 7883 VIXL_ASSERT(allow_macro_instructions_); 7884 VIXL_ASSERT(OutsideITBlock()); 7885 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7886 ITScope it_scope(this, &cond); 7887 vrshr(cond, dt, rd, rm, operand); 7888 } 7889 void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 7890 Vrshr(al, dt, rd, rm, operand); 7891 } 7892 7893 void Vrshrn(Condition cond, 7894 DataType dt, 7895 DRegister rd, 7896 QRegister rm, 7897 const QOperand& operand) { 7898 VIXL_ASSERT(allow_macro_instructions_); 7899 VIXL_ASSERT(OutsideITBlock()); 7900 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7901 ITScope it_scope(this, &cond); 7902 vrshrn(cond, dt, rd, rm, operand); 7903 } 7904 void Vrshrn(DataType dt, 7905 DRegister rd, 7906 QRegister rm, 7907 const QOperand& operand) { 7908 Vrshrn(al, dt, rd, rm, operand); 7909 } 7910 7911 void Vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm) { 7912 VIXL_ASSERT(allow_macro_instructions_); 7913 VIXL_ASSERT(OutsideITBlock()); 7914 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7915 ITScope it_scope(this, &cond); 7916 vrsqrte(cond, dt, rd, rm); 7917 } 7918 void Vrsqrte(DataType dt, DRegister rd, DRegister rm) { 7919 Vrsqrte(al, dt, rd, rm); 7920 } 7921 7922 void Vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm) { 7923 VIXL_ASSERT(allow_macro_instructions_); 7924 VIXL_ASSERT(OutsideITBlock()); 7925 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7926 ITScope it_scope(this, &cond); 7927 vrsqrte(cond, dt, rd, rm); 7928 } 7929 void Vrsqrte(DataType dt, QRegister rd, QRegister rm) { 7930 Vrsqrte(al, dt, rd, rm); 7931 } 7932 7933 void Vrsqrts( 7934 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7935 VIXL_ASSERT(allow_macro_instructions_); 7936 VIXL_ASSERT(OutsideITBlock()); 7937 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7938 ITScope it_scope(this, &cond); 7939 vrsqrts(cond, dt, rd, rn, rm); 7940 } 7941 void Vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7942 Vrsqrts(al, dt, rd, rn, rm); 7943 } 7944 7945 void Vrsqrts( 7946 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7947 VIXL_ASSERT(allow_macro_instructions_); 7948 VIXL_ASSERT(OutsideITBlock()); 7949 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7950 ITScope it_scope(this, &cond); 7951 vrsqrts(cond, dt, rd, rn, rm); 7952 } 7953 void Vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7954 Vrsqrts(al, dt, rd, rn, rm); 7955 } 7956 7957 void Vrsra(Condition cond, 7958 DataType dt, 7959 DRegister rd, 7960 DRegister rm, 7961 const DOperand& operand) { 7962 VIXL_ASSERT(allow_macro_instructions_); 7963 VIXL_ASSERT(OutsideITBlock()); 7964 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7965 ITScope it_scope(this, &cond); 7966 vrsra(cond, dt, rd, rm, operand); 7967 } 7968 void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 7969 Vrsra(al, dt, rd, rm, operand); 7970 } 7971 7972 void Vrsra(Condition cond, 7973 DataType dt, 7974 QRegister rd, 7975 QRegister rm, 7976 const QOperand& operand) { 7977 VIXL_ASSERT(allow_macro_instructions_); 7978 VIXL_ASSERT(OutsideITBlock()); 7979 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7980 ITScope it_scope(this, &cond); 7981 vrsra(cond, dt, rd, rm, operand); 7982 } 7983 void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 7984 Vrsra(al, dt, rd, rm, operand); 7985 } 7986 7987 void Vrsubhn( 7988 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 7989 VIXL_ASSERT(allow_macro_instructions_); 7990 VIXL_ASSERT(OutsideITBlock()); 7991 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 7992 ITScope it_scope(this, &cond); 7993 vrsubhn(cond, dt, rd, rn, rm); 7994 } 7995 void Vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 7996 Vrsubhn(al, dt, rd, rn, rm); 7997 } 7998 7999 void Vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8000 VIXL_ASSERT(allow_macro_instructions_); 8001 VIXL_ASSERT(OutsideITBlock()); 8002 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8003 vseleq(dt, rd, rn, rm); 8004 } 8005 8006 void Vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8007 VIXL_ASSERT(allow_macro_instructions_); 8008 VIXL_ASSERT(OutsideITBlock()); 8009 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8010 vseleq(dt, rd, rn, rm); 8011 } 8012 8013 void Vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8014 VIXL_ASSERT(allow_macro_instructions_); 8015 VIXL_ASSERT(OutsideITBlock()); 8016 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8017 vselge(dt, rd, rn, rm); 8018 } 8019 8020 void Vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8021 VIXL_ASSERT(allow_macro_instructions_); 8022 VIXL_ASSERT(OutsideITBlock()); 8023 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8024 vselge(dt, rd, rn, rm); 8025 } 8026 8027 void Vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8028 VIXL_ASSERT(allow_macro_instructions_); 8029 VIXL_ASSERT(OutsideITBlock()); 8030 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8031 vselgt(dt, rd, rn, rm); 8032 } 8033 8034 void Vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8035 VIXL_ASSERT(allow_macro_instructions_); 8036 VIXL_ASSERT(OutsideITBlock()); 8037 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8038 vselgt(dt, rd, rn, rm); 8039 } 8040 8041 void Vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8042 VIXL_ASSERT(allow_macro_instructions_); 8043 VIXL_ASSERT(OutsideITBlock()); 8044 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8045 vselvs(dt, rd, rn, rm); 8046 } 8047 8048 void Vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8049 VIXL_ASSERT(allow_macro_instructions_); 8050 VIXL_ASSERT(OutsideITBlock()); 8051 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8052 vselvs(dt, rd, rn, rm); 8053 } 8054 8055 void Vshl(Condition cond, 8056 DataType dt, 8057 DRegister rd, 8058 DRegister rm, 8059 const DOperand& operand) { 8060 VIXL_ASSERT(allow_macro_instructions_); 8061 VIXL_ASSERT(OutsideITBlock()); 8062 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8063 ITScope it_scope(this, &cond); 8064 vshl(cond, dt, rd, rm, operand); 8065 } 8066 void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8067 Vshl(al, dt, rd, rm, operand); 8068 } 8069 8070 void Vshl(Condition cond, 8071 DataType dt, 8072 QRegister rd, 8073 QRegister rm, 8074 const QOperand& operand) { 8075 VIXL_ASSERT(allow_macro_instructions_); 8076 VIXL_ASSERT(OutsideITBlock()); 8077 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8078 ITScope it_scope(this, &cond); 8079 vshl(cond, dt, rd, rm, operand); 8080 } 8081 void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8082 Vshl(al, dt, rd, rm, operand); 8083 } 8084 8085 void Vshll(Condition cond, 8086 DataType dt, 8087 QRegister rd, 8088 DRegister rm, 8089 const DOperand& operand) { 8090 VIXL_ASSERT(allow_macro_instructions_); 8091 VIXL_ASSERT(OutsideITBlock()); 8092 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8093 ITScope it_scope(this, &cond); 8094 vshll(cond, dt, rd, rm, operand); 8095 } 8096 void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) { 8097 Vshll(al, dt, rd, rm, operand); 8098 } 8099 8100 void Vshr(Condition cond, 8101 DataType dt, 8102 DRegister rd, 8103 DRegister rm, 8104 const DOperand& operand) { 8105 VIXL_ASSERT(allow_macro_instructions_); 8106 VIXL_ASSERT(OutsideITBlock()); 8107 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8108 ITScope it_scope(this, &cond); 8109 vshr(cond, dt, rd, rm, operand); 8110 } 8111 void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8112 Vshr(al, dt, rd, rm, operand); 8113 } 8114 8115 void Vshr(Condition cond, 8116 DataType dt, 8117 QRegister rd, 8118 QRegister rm, 8119 const QOperand& operand) { 8120 VIXL_ASSERT(allow_macro_instructions_); 8121 VIXL_ASSERT(OutsideITBlock()); 8122 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8123 ITScope it_scope(this, &cond); 8124 vshr(cond, dt, rd, rm, operand); 8125 } 8126 void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8127 Vshr(al, dt, rd, rm, operand); 8128 } 8129 8130 void Vshrn(Condition cond, 8131 DataType dt, 8132 DRegister rd, 8133 QRegister rm, 8134 const QOperand& operand) { 8135 VIXL_ASSERT(allow_macro_instructions_); 8136 VIXL_ASSERT(OutsideITBlock()); 8137 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8138 ITScope it_scope(this, &cond); 8139 vshrn(cond, dt, rd, rm, operand); 8140 } 8141 void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { 8142 Vshrn(al, dt, rd, rm, operand); 8143 } 8144 8145 void Vsli(Condition cond, 8146 DataType dt, 8147 DRegister rd, 8148 DRegister rm, 8149 const DOperand& operand) { 8150 VIXL_ASSERT(allow_macro_instructions_); 8151 VIXL_ASSERT(OutsideITBlock()); 8152 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8153 ITScope it_scope(this, &cond); 8154 vsli(cond, dt, rd, rm, operand); 8155 } 8156 void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8157 Vsli(al, dt, rd, rm, operand); 8158 } 8159 8160 void Vsli(Condition cond, 8161 DataType dt, 8162 QRegister rd, 8163 QRegister rm, 8164 const QOperand& operand) { 8165 VIXL_ASSERT(allow_macro_instructions_); 8166 VIXL_ASSERT(OutsideITBlock()); 8167 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8168 ITScope it_scope(this, &cond); 8169 vsli(cond, dt, rd, rm, operand); 8170 } 8171 void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8172 Vsli(al, dt, rd, rm, operand); 8173 } 8174 8175 void Vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) { 8176 VIXL_ASSERT(allow_macro_instructions_); 8177 VIXL_ASSERT(OutsideITBlock()); 8178 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8179 ITScope it_scope(this, &cond); 8180 vsqrt(cond, dt, rd, rm); 8181 } 8182 void Vsqrt(DataType dt, SRegister rd, SRegister rm) { Vsqrt(al, dt, rd, rm); } 8183 8184 void Vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8185 VIXL_ASSERT(allow_macro_instructions_); 8186 VIXL_ASSERT(OutsideITBlock()); 8187 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8188 ITScope it_scope(this, &cond); 8189 vsqrt(cond, dt, rd, rm); 8190 } 8191 void Vsqrt(DataType dt, DRegister rd, DRegister rm) { Vsqrt(al, dt, rd, rm); } 8192 8193 void Vsra(Condition cond, 8194 DataType dt, 8195 DRegister rd, 8196 DRegister rm, 8197 const DOperand& operand) { 8198 VIXL_ASSERT(allow_macro_instructions_); 8199 VIXL_ASSERT(OutsideITBlock()); 8200 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8201 ITScope it_scope(this, &cond); 8202 vsra(cond, dt, rd, rm, operand); 8203 } 8204 void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8205 Vsra(al, dt, rd, rm, operand); 8206 } 8207 8208 void Vsra(Condition cond, 8209 DataType dt, 8210 QRegister rd, 8211 QRegister rm, 8212 const QOperand& operand) { 8213 VIXL_ASSERT(allow_macro_instructions_); 8214 VIXL_ASSERT(OutsideITBlock()); 8215 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8216 ITScope it_scope(this, &cond); 8217 vsra(cond, dt, rd, rm, operand); 8218 } 8219 void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8220 Vsra(al, dt, rd, rm, operand); 8221 } 8222 8223 void Vsri(Condition cond, 8224 DataType dt, 8225 DRegister rd, 8226 DRegister rm, 8227 const DOperand& operand) { 8228 VIXL_ASSERT(allow_macro_instructions_); 8229 VIXL_ASSERT(OutsideITBlock()); 8230 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8231 ITScope it_scope(this, &cond); 8232 vsri(cond, dt, rd, rm, operand); 8233 } 8234 void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8235 Vsri(al, dt, rd, rm, operand); 8236 } 8237 8238 void Vsri(Condition cond, 8239 DataType dt, 8240 QRegister rd, 8241 QRegister rm, 8242 const QOperand& operand) { 8243 VIXL_ASSERT(allow_macro_instructions_); 8244 VIXL_ASSERT(OutsideITBlock()); 8245 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8246 ITScope it_scope(this, &cond); 8247 vsri(cond, dt, rd, rm, operand); 8248 } 8249 void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8250 Vsri(al, dt, rd, rm, operand); 8251 } 8252 8253 void Vst1(Condition cond, 8254 DataType dt, 8255 const NeonRegisterList& nreglist, 8256 const AlignedMemOperand& operand) { 8257 VIXL_ASSERT(allow_macro_instructions_); 8258 VIXL_ASSERT(OutsideITBlock()); 8259 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8260 ITScope it_scope(this, &cond); 8261 vst1(cond, dt, nreglist, operand); 8262 } 8263 void Vst1(DataType dt, 8264 const NeonRegisterList& nreglist, 8265 const AlignedMemOperand& operand) { 8266 Vst1(al, dt, nreglist, operand); 8267 } 8268 8269 void Vst2(Condition cond, 8270 DataType dt, 8271 const NeonRegisterList& nreglist, 8272 const AlignedMemOperand& operand) { 8273 VIXL_ASSERT(allow_macro_instructions_); 8274 VIXL_ASSERT(OutsideITBlock()); 8275 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8276 ITScope it_scope(this, &cond); 8277 vst2(cond, dt, nreglist, operand); 8278 } 8279 void Vst2(DataType dt, 8280 const NeonRegisterList& nreglist, 8281 const AlignedMemOperand& operand) { 8282 Vst2(al, dt, nreglist, operand); 8283 } 8284 8285 void Vst3(Condition cond, 8286 DataType dt, 8287 const NeonRegisterList& nreglist, 8288 const AlignedMemOperand& operand) { 8289 VIXL_ASSERT(allow_macro_instructions_); 8290 VIXL_ASSERT(OutsideITBlock()); 8291 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8292 ITScope it_scope(this, &cond); 8293 vst3(cond, dt, nreglist, operand); 8294 } 8295 void Vst3(DataType dt, 8296 const NeonRegisterList& nreglist, 8297 const AlignedMemOperand& operand) { 8298 Vst3(al, dt, nreglist, operand); 8299 } 8300 8301 void Vst3(Condition cond, 8302 DataType dt, 8303 const NeonRegisterList& nreglist, 8304 const MemOperand& operand) { 8305 VIXL_ASSERT(allow_macro_instructions_); 8306 VIXL_ASSERT(OutsideITBlock()); 8307 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8308 ITScope it_scope(this, &cond); 8309 vst3(cond, dt, nreglist, operand); 8310 } 8311 void Vst3(DataType dt, 8312 const NeonRegisterList& nreglist, 8313 const MemOperand& operand) { 8314 Vst3(al, dt, nreglist, operand); 8315 } 8316 8317 void Vst4(Condition cond, 8318 DataType dt, 8319 const NeonRegisterList& nreglist, 8320 const AlignedMemOperand& operand) { 8321 VIXL_ASSERT(allow_macro_instructions_); 8322 VIXL_ASSERT(OutsideITBlock()); 8323 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8324 ITScope it_scope(this, &cond); 8325 vst4(cond, dt, nreglist, operand); 8326 } 8327 void Vst4(DataType dt, 8328 const NeonRegisterList& nreglist, 8329 const AlignedMemOperand& operand) { 8330 Vst4(al, dt, nreglist, operand); 8331 } 8332 8333 void Vstm(Condition cond, 8334 DataType dt, 8335 Register rn, 8336 WriteBack write_back, 8337 DRegisterList dreglist) { 8338 VIXL_ASSERT(allow_macro_instructions_); 8339 VIXL_ASSERT(OutsideITBlock()); 8340 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8341 ITScope it_scope(this, &cond); 8342 vstm(cond, dt, rn, write_back, dreglist); 8343 } 8344 void Vstm(DataType dt, 8345 Register rn, 8346 WriteBack write_back, 8347 DRegisterList dreglist) { 8348 Vstm(al, dt, rn, write_back, dreglist); 8349 } 8350 void Vstm(Condition cond, 8351 Register rn, 8352 WriteBack write_back, 8353 DRegisterList dreglist) { 8354 Vstm(cond, kDataTypeValueNone, rn, write_back, dreglist); 8355 } 8356 void Vstm(Register rn, WriteBack write_back, DRegisterList dreglist) { 8357 Vstm(al, kDataTypeValueNone, rn, write_back, dreglist); 8358 } 8359 8360 void Vstm(Condition cond, 8361 DataType dt, 8362 Register rn, 8363 WriteBack write_back, 8364 SRegisterList sreglist) { 8365 VIXL_ASSERT(allow_macro_instructions_); 8366 VIXL_ASSERT(OutsideITBlock()); 8367 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8368 ITScope it_scope(this, &cond); 8369 vstm(cond, dt, rn, write_back, sreglist); 8370 } 8371 void Vstm(DataType dt, 8372 Register rn, 8373 WriteBack write_back, 8374 SRegisterList sreglist) { 8375 Vstm(al, dt, rn, write_back, sreglist); 8376 } 8377 void Vstm(Condition cond, 8378 Register rn, 8379 WriteBack write_back, 8380 SRegisterList sreglist) { 8381 Vstm(cond, kDataTypeValueNone, rn, write_back, sreglist); 8382 } 8383 void Vstm(Register rn, WriteBack write_back, SRegisterList sreglist) { 8384 Vstm(al, kDataTypeValueNone, rn, write_back, sreglist); 8385 } 8386 8387 void Vstmdb(Condition cond, 8388 DataType dt, 8389 Register rn, 8390 WriteBack write_back, 8391 DRegisterList dreglist) { 8392 VIXL_ASSERT(allow_macro_instructions_); 8393 VIXL_ASSERT(OutsideITBlock()); 8394 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8395 ITScope it_scope(this, &cond); 8396 vstmdb(cond, dt, rn, write_back, dreglist); 8397 } 8398 void Vstmdb(DataType dt, 8399 Register rn, 8400 WriteBack write_back, 8401 DRegisterList dreglist) { 8402 Vstmdb(al, dt, rn, write_back, dreglist); 8403 } 8404 void Vstmdb(Condition cond, 8405 Register rn, 8406 WriteBack write_back, 8407 DRegisterList dreglist) { 8408 Vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 8409 } 8410 void Vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 8411 Vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 8412 } 8413 8414 void Vstmdb(Condition cond, 8415 DataType dt, 8416 Register rn, 8417 WriteBack write_back, 8418 SRegisterList sreglist) { 8419 VIXL_ASSERT(allow_macro_instructions_); 8420 VIXL_ASSERT(OutsideITBlock()); 8421 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8422 ITScope it_scope(this, &cond); 8423 vstmdb(cond, dt, rn, write_back, sreglist); 8424 } 8425 void Vstmdb(DataType dt, 8426 Register rn, 8427 WriteBack write_back, 8428 SRegisterList sreglist) { 8429 Vstmdb(al, dt, rn, write_back, sreglist); 8430 } 8431 void Vstmdb(Condition cond, 8432 Register rn, 8433 WriteBack write_back, 8434 SRegisterList sreglist) { 8435 Vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 8436 } 8437 void Vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 8438 Vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 8439 } 8440 8441 void Vstmia(Condition cond, 8442 DataType dt, 8443 Register rn, 8444 WriteBack write_back, 8445 DRegisterList dreglist) { 8446 VIXL_ASSERT(allow_macro_instructions_); 8447 VIXL_ASSERT(OutsideITBlock()); 8448 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8449 ITScope it_scope(this, &cond); 8450 vstmia(cond, dt, rn, write_back, dreglist); 8451 } 8452 void Vstmia(DataType dt, 8453 Register rn, 8454 WriteBack write_back, 8455 DRegisterList dreglist) { 8456 Vstmia(al, dt, rn, write_back, dreglist); 8457 } 8458 void Vstmia(Condition cond, 8459 Register rn, 8460 WriteBack write_back, 8461 DRegisterList dreglist) { 8462 Vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 8463 } 8464 void Vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 8465 Vstmia(al, kDataTypeValueNone, rn, write_back, dreglist); 8466 } 8467 8468 void Vstmia(Condition cond, 8469 DataType dt, 8470 Register rn, 8471 WriteBack write_back, 8472 SRegisterList sreglist) { 8473 VIXL_ASSERT(allow_macro_instructions_); 8474 VIXL_ASSERT(OutsideITBlock()); 8475 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8476 ITScope it_scope(this, &cond); 8477 vstmia(cond, dt, rn, write_back, sreglist); 8478 } 8479 void Vstmia(DataType dt, 8480 Register rn, 8481 WriteBack write_back, 8482 SRegisterList sreglist) { 8483 Vstmia(al, dt, rn, write_back, sreglist); 8484 } 8485 void Vstmia(Condition cond, 8486 Register rn, 8487 WriteBack write_back, 8488 SRegisterList sreglist) { 8489 Vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 8490 } 8491 void Vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 8492 Vstmia(al, kDataTypeValueNone, rn, write_back, sreglist); 8493 } 8494 8495 void Vstr(Condition cond, 8496 DataType dt, 8497 DRegister rd, 8498 const MemOperand& operand) { 8499 VIXL_ASSERT(allow_macro_instructions_); 8500 VIXL_ASSERT(OutsideITBlock()); 8501 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8502 ITScope it_scope(this, &cond); 8503 vstr(cond, dt, rd, operand); 8504 } 8505 void Vstr(DataType dt, DRegister rd, const MemOperand& operand) { 8506 Vstr(al, dt, rd, operand); 8507 } 8508 void Vstr(Condition cond, DRegister rd, const MemOperand& operand) { 8509 Vstr(cond, Untyped64, rd, operand); 8510 } 8511 void Vstr(DRegister rd, const MemOperand& operand) { 8512 Vstr(al, Untyped64, rd, operand); 8513 } 8514 8515 void Vstr(Condition cond, 8516 DataType dt, 8517 SRegister rd, 8518 const MemOperand& operand) { 8519 VIXL_ASSERT(allow_macro_instructions_); 8520 VIXL_ASSERT(OutsideITBlock()); 8521 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8522 ITScope it_scope(this, &cond); 8523 vstr(cond, dt, rd, operand); 8524 } 8525 void Vstr(DataType dt, SRegister rd, const MemOperand& operand) { 8526 Vstr(al, dt, rd, operand); 8527 } 8528 void Vstr(Condition cond, SRegister rd, const MemOperand& operand) { 8529 Vstr(cond, Untyped32, rd, operand); 8530 } 8531 void Vstr(SRegister rd, const MemOperand& operand) { 8532 Vstr(al, Untyped32, rd, operand); 8533 } 8534 8535 void Vsub( 8536 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8537 VIXL_ASSERT(allow_macro_instructions_); 8538 VIXL_ASSERT(OutsideITBlock()); 8539 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8540 ITScope it_scope(this, &cond); 8541 vsub(cond, dt, rd, rn, rm); 8542 } 8543 void Vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8544 Vsub(al, dt, rd, rn, rm); 8545 } 8546 8547 void Vsub( 8548 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8549 VIXL_ASSERT(allow_macro_instructions_); 8550 VIXL_ASSERT(OutsideITBlock()); 8551 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8552 ITScope it_scope(this, &cond); 8553 vsub(cond, dt, rd, rn, rm); 8554 } 8555 void Vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8556 Vsub(al, dt, rd, rn, rm); 8557 } 8558 8559 void Vsub( 8560 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8561 VIXL_ASSERT(allow_macro_instructions_); 8562 VIXL_ASSERT(OutsideITBlock()); 8563 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8564 ITScope it_scope(this, &cond); 8565 vsub(cond, dt, rd, rn, rm); 8566 } 8567 void Vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8568 Vsub(al, dt, rd, rn, rm); 8569 } 8570 8571 void Vsubhn( 8572 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 8573 VIXL_ASSERT(allow_macro_instructions_); 8574 VIXL_ASSERT(OutsideITBlock()); 8575 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8576 ITScope it_scope(this, &cond); 8577 vsubhn(cond, dt, rd, rn, rm); 8578 } 8579 void Vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 8580 Vsubhn(al, dt, rd, rn, rm); 8581 } 8582 8583 void Vsubl( 8584 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8585 VIXL_ASSERT(allow_macro_instructions_); 8586 VIXL_ASSERT(OutsideITBlock()); 8587 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8588 ITScope it_scope(this, &cond); 8589 vsubl(cond, dt, rd, rn, rm); 8590 } 8591 void Vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8592 Vsubl(al, dt, rd, rn, rm); 8593 } 8594 8595 void Vsubw( 8596 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { 8597 VIXL_ASSERT(allow_macro_instructions_); 8598 VIXL_ASSERT(OutsideITBlock()); 8599 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8600 ITScope it_scope(this, &cond); 8601 vsubw(cond, dt, rd, rn, rm); 8602 } 8603 void Vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 8604 Vsubw(al, dt, rd, rn, rm); 8605 } 8606 8607 void Vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8608 VIXL_ASSERT(allow_macro_instructions_); 8609 VIXL_ASSERT(OutsideITBlock()); 8610 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8611 ITScope it_scope(this, &cond); 8612 vswp(cond, dt, rd, rm); 8613 } 8614 void Vswp(DataType dt, DRegister rd, DRegister rm) { Vswp(al, dt, rd, rm); } 8615 void Vswp(Condition cond, DRegister rd, DRegister rm) { 8616 Vswp(cond, kDataTypeValueNone, rd, rm); 8617 } 8618 void Vswp(DRegister rd, DRegister rm) { 8619 Vswp(al, kDataTypeValueNone, rd, rm); 8620 } 8621 8622 void Vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8623 VIXL_ASSERT(allow_macro_instructions_); 8624 VIXL_ASSERT(OutsideITBlock()); 8625 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8626 ITScope it_scope(this, &cond); 8627 vswp(cond, dt, rd, rm); 8628 } 8629 void Vswp(DataType dt, QRegister rd, QRegister rm) { Vswp(al, dt, rd, rm); } 8630 void Vswp(Condition cond, QRegister rd, QRegister rm) { 8631 Vswp(cond, kDataTypeValueNone, rd, rm); 8632 } 8633 void Vswp(QRegister rd, QRegister rm) { 8634 Vswp(al, kDataTypeValueNone, rd, rm); 8635 } 8636 8637 void Vtbl(Condition cond, 8638 DataType dt, 8639 DRegister rd, 8640 const NeonRegisterList& nreglist, 8641 DRegister rm) { 8642 VIXL_ASSERT(allow_macro_instructions_); 8643 VIXL_ASSERT(OutsideITBlock()); 8644 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8645 ITScope it_scope(this, &cond); 8646 vtbl(cond, dt, rd, nreglist, rm); 8647 } 8648 void Vtbl(DataType dt, 8649 DRegister rd, 8650 const NeonRegisterList& nreglist, 8651 DRegister rm) { 8652 Vtbl(al, dt, rd, nreglist, rm); 8653 } 8654 8655 void Vtbx(Condition cond, 8656 DataType dt, 8657 DRegister rd, 8658 const NeonRegisterList& nreglist, 8659 DRegister rm) { 8660 VIXL_ASSERT(allow_macro_instructions_); 8661 VIXL_ASSERT(OutsideITBlock()); 8662 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8663 ITScope it_scope(this, &cond); 8664 vtbx(cond, dt, rd, nreglist, rm); 8665 } 8666 void Vtbx(DataType dt, 8667 DRegister rd, 8668 const NeonRegisterList& nreglist, 8669 DRegister rm) { 8670 Vtbx(al, dt, rd, nreglist, rm); 8671 } 8672 8673 void Vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8674 VIXL_ASSERT(allow_macro_instructions_); 8675 VIXL_ASSERT(OutsideITBlock()); 8676 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8677 ITScope it_scope(this, &cond); 8678 vtrn(cond, dt, rd, rm); 8679 } 8680 void Vtrn(DataType dt, DRegister rd, DRegister rm) { Vtrn(al, dt, rd, rm); } 8681 8682 void Vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8683 VIXL_ASSERT(allow_macro_instructions_); 8684 VIXL_ASSERT(OutsideITBlock()); 8685 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8686 ITScope it_scope(this, &cond); 8687 vtrn(cond, dt, rd, rm); 8688 } 8689 void Vtrn(DataType dt, QRegister rd, QRegister rm) { Vtrn(al, dt, rd, rm); } 8690 8691 void Vtst( 8692 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8693 VIXL_ASSERT(allow_macro_instructions_); 8694 VIXL_ASSERT(OutsideITBlock()); 8695 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8696 ITScope it_scope(this, &cond); 8697 vtst(cond, dt, rd, rn, rm); 8698 } 8699 void Vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8700 Vtst(al, dt, rd, rn, rm); 8701 } 8702 8703 void Vtst( 8704 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8705 VIXL_ASSERT(allow_macro_instructions_); 8706 VIXL_ASSERT(OutsideITBlock()); 8707 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8708 ITScope it_scope(this, &cond); 8709 vtst(cond, dt, rd, rn, rm); 8710 } 8711 void Vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8712 Vtst(al, dt, rd, rn, rm); 8713 } 8714 8715 void Vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8716 VIXL_ASSERT(allow_macro_instructions_); 8717 VIXL_ASSERT(OutsideITBlock()); 8718 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8719 ITScope it_scope(this, &cond); 8720 vuzp(cond, dt, rd, rm); 8721 } 8722 void Vuzp(DataType dt, DRegister rd, DRegister rm) { Vuzp(al, dt, rd, rm); } 8723 8724 void Vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8725 VIXL_ASSERT(allow_macro_instructions_); 8726 VIXL_ASSERT(OutsideITBlock()); 8727 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8728 ITScope it_scope(this, &cond); 8729 vuzp(cond, dt, rd, rm); 8730 } 8731 void Vuzp(DataType dt, QRegister rd, QRegister rm) { Vuzp(al, dt, rd, rm); } 8732 8733 void Vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8734 VIXL_ASSERT(allow_macro_instructions_); 8735 VIXL_ASSERT(OutsideITBlock()); 8736 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8737 ITScope it_scope(this, &cond); 8738 vzip(cond, dt, rd, rm); 8739 } 8740 void Vzip(DataType dt, DRegister rd, DRegister rm) { Vzip(al, dt, rd, rm); } 8741 8742 void Vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8743 VIXL_ASSERT(allow_macro_instructions_); 8744 VIXL_ASSERT(OutsideITBlock()); 8745 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8746 ITScope it_scope(this, &cond); 8747 vzip(cond, dt, rd, rm); 8748 } 8749 void Vzip(DataType dt, QRegister rd, QRegister rm) { Vzip(al, dt, rd, rm); } 8750 8751 void Yield(Condition cond) { 8752 VIXL_ASSERT(allow_macro_instructions_); 8753 VIXL_ASSERT(OutsideITBlock()); 8754 AllowAssemblerEmissionScope allow_scope(this, kMaxInstructionSizeInBytes); 8755 ITScope it_scope(this, &cond); 8756 yield(cond); 8757 } 8758 void Yield() { Yield(al); } 8759 void Vabs(Condition cond, VRegister rd, VRegister rm) { 8760 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8761 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8762 if (rd.IsS()) { 8763 Vabs(cond, F32, rd.S(), rm.S()); 8764 } else { 8765 Vabs(cond, F64, rd.D(), rm.D()); 8766 } 8767 } 8768 void Vabs(VRegister rd, VRegister rm) { Vabs(al, rd, rm); } 8769 void Vadd(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8770 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8771 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8772 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8773 if (rd.IsS()) { 8774 Vadd(cond, F32, rd.S(), rn.S(), rm.S()); 8775 } else { 8776 Vadd(cond, F64, rd.D(), rn.D(), rm.D()); 8777 } 8778 } 8779 void Vadd(VRegister rd, VRegister rn, VRegister rm) { Vadd(al, rd, rn, rm); } 8780 void Vcmp(Condition cond, VRegister rd, VRegister rm) { 8781 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8782 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8783 if (rd.IsS()) { 8784 Vcmp(cond, F32, rd.S(), rm.S()); 8785 } else { 8786 Vcmp(cond, F64, rd.D(), rm.D()); 8787 } 8788 } 8789 void Vcmp(VRegister rd, VRegister rm) { Vcmp(al, rd, rm); } 8790 void Vcmpe(Condition cond, VRegister rd, VRegister rm) { 8791 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8792 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8793 if (rd.IsS()) { 8794 Vcmpe(cond, F32, rd.S(), rm.S()); 8795 } else { 8796 Vcmpe(cond, F64, rd.D(), rm.D()); 8797 } 8798 } 8799 void Vcmpe(VRegister rd, VRegister rm) { Vcmpe(al, rd, rm); } 8800 void Vdiv(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8801 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8802 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8803 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8804 if (rd.IsS()) { 8805 Vdiv(cond, F32, rd.S(), rn.S(), rm.S()); 8806 } else { 8807 Vdiv(cond, F64, rd.D(), rn.D(), rm.D()); 8808 } 8809 } 8810 void Vdiv(VRegister rd, VRegister rn, VRegister rm) { Vdiv(al, rd, rn, rm); } 8811 void Vfma(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8812 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8813 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8814 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8815 if (rd.IsS()) { 8816 Vfma(cond, F32, rd.S(), rn.S(), rm.S()); 8817 } else { 8818 Vfma(cond, F64, rd.D(), rn.D(), rm.D()); 8819 } 8820 } 8821 void Vfma(VRegister rd, VRegister rn, VRegister rm) { Vfma(al, rd, rn, rm); } 8822 void Vfms(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8823 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8824 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8825 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8826 if (rd.IsS()) { 8827 Vfms(cond, F32, rd.S(), rn.S(), rm.S()); 8828 } else { 8829 Vfms(cond, F64, rd.D(), rn.D(), rm.D()); 8830 } 8831 } 8832 void Vfms(VRegister rd, VRegister rn, VRegister rm) { Vfms(al, rd, rn, rm); } 8833 void Vfnma(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8834 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8835 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8836 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8837 if (rd.IsS()) { 8838 Vfnma(cond, F32, rd.S(), rn.S(), rm.S()); 8839 } else { 8840 Vfnma(cond, F64, rd.D(), rn.D(), rm.D()); 8841 } 8842 } 8843 void Vfnma(VRegister rd, VRegister rn, VRegister rm) { 8844 Vfnma(al, rd, rn, rm); 8845 } 8846 void Vfnms(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8847 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8848 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8849 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8850 if (rd.IsS()) { 8851 Vfnms(cond, F32, rd.S(), rn.S(), rm.S()); 8852 } else { 8853 Vfnms(cond, F64, rd.D(), rn.D(), rm.D()); 8854 } 8855 } 8856 void Vfnms(VRegister rd, VRegister rn, VRegister rm) { 8857 Vfnms(al, rd, rn, rm); 8858 } 8859 void Vmaxnm(VRegister rd, VRegister rn, VRegister rm) { 8860 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8861 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8862 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8863 if (rd.IsS()) { 8864 Vmaxnm(F32, rd.S(), rn.S(), rm.S()); 8865 } else { 8866 Vmaxnm(F64, rd.D(), rn.D(), rm.D()); 8867 } 8868 } 8869 void Vminnm(VRegister rd, VRegister rn, VRegister rm) { 8870 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8871 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8872 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8873 if (rd.IsS()) { 8874 Vminnm(F32, rd.S(), rn.S(), rm.S()); 8875 } else { 8876 Vminnm(F64, rd.D(), rn.D(), rm.D()); 8877 } 8878 } 8879 void Vmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8880 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8881 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8882 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8883 if (rd.IsS()) { 8884 Vmla(cond, F32, rd.S(), rn.S(), rm.S()); 8885 } else { 8886 Vmla(cond, F64, rd.D(), rn.D(), rm.D()); 8887 } 8888 } 8889 void Vmla(VRegister rd, VRegister rn, VRegister rm) { Vmla(al, rd, rn, rm); } 8890 void Vmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8891 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8892 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8893 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8894 if (rd.IsS()) { 8895 Vmls(cond, F32, rd.S(), rn.S(), rm.S()); 8896 } else { 8897 Vmls(cond, F64, rd.D(), rn.D(), rm.D()); 8898 } 8899 } 8900 void Vmls(VRegister rd, VRegister rn, VRegister rm) { Vmls(al, rd, rn, rm); } 8901 void Vmov(Condition cond, VRegister rd, VRegister rm) { 8902 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8903 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8904 if (rd.IsS()) { 8905 Vmov(cond, F32, rd.S(), rm.S()); 8906 } else { 8907 Vmov(cond, F64, rd.D(), rm.D()); 8908 } 8909 } 8910 void Vmov(VRegister rd, VRegister rm) { Vmov(al, rd, rm); } 8911 void Vmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8912 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8913 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8914 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8915 if (rd.IsS()) { 8916 Vmul(cond, F32, rd.S(), rn.S(), rm.S()); 8917 } else { 8918 Vmul(cond, F64, rd.D(), rn.D(), rm.D()); 8919 } 8920 } 8921 void Vmul(VRegister rd, VRegister rn, VRegister rm) { Vmul(al, rd, rn, rm); } 8922 void Vneg(Condition cond, VRegister rd, VRegister rm) { 8923 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8924 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8925 if (rd.IsS()) { 8926 Vneg(cond, F32, rd.S(), rm.S()); 8927 } else { 8928 Vneg(cond, F64, rd.D(), rm.D()); 8929 } 8930 } 8931 void Vneg(VRegister rd, VRegister rm) { Vneg(al, rd, rm); } 8932 void Vnmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8933 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8934 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8935 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8936 if (rd.IsS()) { 8937 Vnmla(cond, F32, rd.S(), rn.S(), rm.S()); 8938 } else { 8939 Vnmla(cond, F64, rd.D(), rn.D(), rm.D()); 8940 } 8941 } 8942 void Vnmla(VRegister rd, VRegister rn, VRegister rm) { 8943 Vnmla(al, rd, rn, rm); 8944 } 8945 void Vnmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8946 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8947 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8948 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8949 if (rd.IsS()) { 8950 Vnmls(cond, F32, rd.S(), rn.S(), rm.S()); 8951 } else { 8952 Vnmls(cond, F64, rd.D(), rn.D(), rm.D()); 8953 } 8954 } 8955 void Vnmls(VRegister rd, VRegister rn, VRegister rm) { 8956 Vnmls(al, rd, rn, rm); 8957 } 8958 void Vnmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 8959 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8960 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8961 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8962 if (rd.IsS()) { 8963 Vnmul(cond, F32, rd.S(), rn.S(), rm.S()); 8964 } else { 8965 Vnmul(cond, F64, rd.D(), rn.D(), rm.D()); 8966 } 8967 } 8968 void Vnmul(VRegister rd, VRegister rn, VRegister rm) { 8969 Vnmul(al, rd, rn, rm); 8970 } 8971 void Vseleq(VRegister rd, VRegister rn, VRegister rm) { 8972 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8973 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8974 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8975 if (rd.IsS()) { 8976 Vseleq(F32, rd.S(), rn.S(), rm.S()); 8977 } else { 8978 Vseleq(F64, rd.D(), rn.D(), rm.D()); 8979 } 8980 } 8981 void Vselge(VRegister rd, VRegister rn, VRegister rm) { 8982 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8983 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8984 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8985 if (rd.IsS()) { 8986 Vselge(F32, rd.S(), rn.S(), rm.S()); 8987 } else { 8988 Vselge(F64, rd.D(), rn.D(), rm.D()); 8989 } 8990 } 8991 void Vselgt(VRegister rd, VRegister rn, VRegister rm) { 8992 VIXL_ASSERT(rd.IsS() || rd.IsD()); 8993 VIXL_ASSERT(rd.GetType() == rn.GetType()); 8994 VIXL_ASSERT(rd.GetType() == rm.GetType()); 8995 if (rd.IsS()) { 8996 Vselgt(F32, rd.S(), rn.S(), rm.S()); 8997 } else { 8998 Vselgt(F64, rd.D(), rn.D(), rm.D()); 8999 } 9000 } 9001 void Vselvs(VRegister rd, VRegister rn, VRegister rm) { 9002 VIXL_ASSERT(rd.IsS() || rd.IsD()); 9003 VIXL_ASSERT(rd.GetType() == rn.GetType()); 9004 VIXL_ASSERT(rd.GetType() == rm.GetType()); 9005 if (rd.IsS()) { 9006 Vselvs(F32, rd.S(), rn.S(), rm.S()); 9007 } else { 9008 Vselvs(F64, rd.D(), rn.D(), rm.D()); 9009 } 9010 } 9011 void Vsqrt(Condition cond, VRegister rd, VRegister rm) { 9012 VIXL_ASSERT(rd.IsS() || rd.IsD()); 9013 VIXL_ASSERT(rd.GetType() == rm.GetType()); 9014 if (rd.IsS()) { 9015 Vsqrt(cond, F32, rd.S(), rm.S()); 9016 } else { 9017 Vsqrt(cond, F64, rd.D(), rm.D()); 9018 } 9019 } 9020 void Vsqrt(VRegister rd, VRegister rm) { Vsqrt(al, rd, rm); } 9021 void Vsub(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 9022 VIXL_ASSERT(rd.IsS() || rd.IsD()); 9023 VIXL_ASSERT(rd.GetType() == rn.GetType()); 9024 VIXL_ASSERT(rd.GetType() == rm.GetType()); 9025 if (rd.IsS()) { 9026 Vsub(cond, F32, rd.S(), rn.S(), rm.S()); 9027 } else { 9028 Vsub(cond, F64, rd.D(), rn.D(), rm.D()); 9029 } 9030 } 9031 void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); } 9032 // End of generated code. 9033 private: 9034 RegisterList available_; 9035 VRegisterList available_vfp_; 9036 MacroAssemblerContext context_; 9037 Label::Offset checkpoint_; 9038 LiteralPoolManager literal_pool_manager_; 9039 VeneerPoolManager veneer_pool_manager_; 9040 bool generate_simulator_code_; 9041 bool allow_macro_instructions_; 9042}; 9043 9044// This scope is used to ensure that the specified size of instructions will be 9045// emitted contiguously. The assert policy kExtactSize should only be used 9046// when you use directly the assembler as it's difficult to know exactly how 9047// many instructions will be emitted by the macro-assembler. Using the assembler 9048// means that you directly use the assembler instructions (in lower case) from a 9049// MacroAssembler object. 9050class CodeBufferCheckScope { 9051 public: 9052 // Tell whether or not the scope should assert the amount of code emitted 9053 // within the scope is consistent with the requested amount. 9054 enum AssertPolicy { 9055 kNoAssert, // No assert required. 9056 kExactSize, // The code emitted must be exactly size bytes. 9057 kMaximumSize // The code emitted must be at most size bytes. 9058 }; 9059 9060 CodeBufferCheckScope(MacroAssembler* masm, 9061 uint32_t size, 9062 AssertPolicy assert_policy = kMaximumSize) 9063 : masm_(masm) { 9064 masm->EnsureEmitFor(size); 9065#ifdef VIXL_DEBUG 9066 initial_cursor_offset_ = masm->GetCursorOffset(); 9067 size_ = size; 9068 assert_policy_ = assert_policy; 9069#else 9070 USE(assert_policy); 9071#endif 9072 } 9073 9074 ~CodeBufferCheckScope() { 9075#ifdef VIXL_DEBUG 9076 switch (assert_policy_) { 9077 case kNoAssert: 9078 break; 9079 case kExactSize: 9080 VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ == size_); 9081 break; 9082 case kMaximumSize: 9083 VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <= size_); 9084 break; 9085 default: 9086 VIXL_UNREACHABLE(); 9087 } 9088#endif 9089 } 9090 9091 protected: 9092 MacroAssembler* masm_; 9093 uint32_t initial_cursor_offset_; 9094 uint32_t size_; 9095 AssertPolicy assert_policy_; 9096}; 9097 9098// Use this scope when you need a one-to-one mapping between methods and 9099// instructions. This scope prevents the MacroAssembler functions from being 9100// called and the literal pools and veneers from being emitted (they can only be 9101// emitted when you create the scope). It also asserts the size of the emitted 9102// instructions is the specified size (or not greater than the specified size). 9103// This scope must be used when you want to directly use the assembler. It will 9104// ensure that the buffer is big enough and that you don't break the pool and 9105// veneer mechanisms. 9106class AssemblerAccurateScope : public CodeBufferCheckScope { 9107 public: 9108 AssemblerAccurateScope(MacroAssembler* masm, 9109 uint32_t size, 9110 AssertPolicy policy = kExactSize) 9111 : CodeBufferCheckScope(masm, size, policy) { 9112 VIXL_ASSERT(policy != kNoAssert); 9113#ifdef VIXL_DEBUG 9114 old_allow_macro_instructions_ = masm->AllowMacroInstructions(); 9115 old_allow_assembler_ = masm->AllowAssembler(); 9116 masm->SetAllowMacroInstructions(false); 9117 masm->SetAllowAssembler(true); 9118#else 9119 USE(old_allow_macro_instructions_); 9120 USE(old_allow_assembler_); 9121#endif 9122 } 9123 9124 ~AssemblerAccurateScope() { 9125#ifdef VIXL_DEBUG 9126 masm_->SetAllowMacroInstructions(old_allow_macro_instructions_); 9127 masm_->SetAllowAssembler(old_allow_assembler_); 9128#endif 9129 } 9130 9131 private: 9132 bool old_allow_macro_instructions_; 9133 bool old_allow_assembler_; 9134}; 9135 9136// This scope utility allows scratch registers to be managed safely. The 9137// MacroAssembler's GetScratchRegisterList() is used as a pool of scratch 9138// registers. These registers can be allocated on demand, and will be returned 9139// at the end of the scope. 9140// 9141// When the scope ends, the MacroAssembler's lists will be restored to their 9142// original state, even if the lists were modified by some other means. 9143class UseScratchRegisterScope { 9144 public: 9145 // This constructor implicitly calls the `Open` function to initialise the 9146 // scope, so it is ready to use immediately after it has been constructed. 9147 explicit UseScratchRegisterScope(MacroAssembler* masm) 9148 : available_(NULL), 9149 available_vfp_(NULL), 9150 old_available_(0), 9151 old_available_vfp_(0) { 9152 Open(masm); 9153 } 9154 // This constructor allows deferred and optional initialisation of the scope. 9155 // The user is required to explicitly call the `Open` function before using 9156 // the scope. 9157 UseScratchRegisterScope() 9158 : available_(NULL), 9159 available_vfp_(NULL), 9160 old_available_(0), 9161 old_available_vfp_(0) {} 9162 9163 // This function performs the actual initialisation work. 9164 void Open(MacroAssembler* masm); 9165 9166 // The destructor always implicitly calls the `Close` function. 9167 ~UseScratchRegisterScope() { Close(); } 9168 9169 // This function performs the cleaning-up work. It must succeed even if the 9170 // scope has not been opened. It is safe to call multiple times. 9171 void Close(); 9172 9173 bool IsAvailable(const Register& reg) const; 9174 bool IsAvailable(const VRegister& reg) const; 9175 9176 // Take a register from the temp list. It will be returned automatically when 9177 // the scope ends. 9178 Register Acquire(); 9179 VRegister AcquireV(unsigned size_in_bits); 9180 QRegister AcquireQ(); 9181 DRegister AcquireD(); 9182 SRegister AcquireS(); 9183 9184 // Explicitly release an acquired (or excluded) register, putting it back in 9185 // the temp list. 9186 void Release(const Register& reg); 9187 void Release(const VRegister& reg); 9188 9189 // Make the specified registers available as scratch registers for the 9190 // duration of this scope. 9191 void Include(const RegisterList& list); 9192 void Include(const Register& reg1, 9193 const Register& reg2 = NoReg, 9194 const Register& reg3 = NoReg, 9195 const Register& reg4 = NoReg) { 9196 Include(RegisterList(reg1, reg2, reg3, reg4)); 9197 } 9198 void Include(const VRegisterList& list); 9199 void Include(const VRegister& reg1, 9200 const VRegister& reg2 = NoVReg, 9201 const VRegister& reg3 = NoVReg, 9202 const VRegister& reg4 = NoVReg) { 9203 Include(VRegisterList(reg1, reg2, reg3, reg4)); 9204 } 9205 9206 // Make sure that the specified registers are not available in this scope. 9207 // This can be used to prevent helper functions from using sensitive 9208 // registers, for example. 9209 void Exclude(const RegisterList& list); 9210 void Exclude(const Register& reg1, 9211 const Register& reg2 = NoReg, 9212 const Register& reg3 = NoReg, 9213 const Register& reg4 = NoReg) { 9214 Exclude(RegisterList(reg1, reg2, reg3, reg4)); 9215 } 9216 void Exclude(const VRegisterList& list); 9217 void Exclude(const VRegister& reg1, 9218 const VRegister& reg2 = NoVReg, 9219 const VRegister& reg3 = NoVReg, 9220 const VRegister& reg4 = NoVReg) { 9221 Exclude(VRegisterList(reg1, reg2, reg3, reg4)); 9222 } 9223 9224 // Prevent any scratch registers from being used in this scope. 9225 void ExcludeAll(); 9226 9227 private: 9228 // Available scratch registers. 9229 RegisterList* available_; // kRRegister 9230 VRegisterList* available_vfp_; // kVRegister 9231 9232 // The state of the available lists at the start of this scope. 9233 uint32_t old_available_; // kRRegister 9234 uint64_t old_available_vfp_; // kVRegister 9235 9236 VIXL_DEBUG_NO_RETURN UseScratchRegisterScope(const UseScratchRegisterScope&) { 9237 VIXL_UNREACHABLE(); 9238 } 9239 VIXL_DEBUG_NO_RETURN void operator=(const UseScratchRegisterScope&) { 9240 VIXL_UNREACHABLE(); 9241 } 9242}; 9243 9244class JumpTableBase { 9245 protected: 9246 JumpTableBase(int len, int offset_size) 9247 : table_location_(Label::kMaxOffset), 9248 branch_location_(Label::kMaxOffset), 9249 length_(len), 9250 offset_shift_(WhichPowerOf2(offset_size)), 9251 presence_(length_) { 9252 VIXL_ASSERT((length_ >= 0) && (offset_size <= 4)); 9253 } 9254 virtual ~JumpTableBase() {} 9255 9256 public: 9257 int GetTableSizeInBytes() const { return length_ * (1 << offset_shift_); } 9258 int GetOffsetShift() const { return offset_shift_; } 9259 int GetLength() const { return length_; } 9260 Label* GetDefaultLabel() { return &default_; } 9261 Label* GetEndLabel() { return &end_; } 9262 void SetBranchLocation(uint32_t branch_location) { 9263 branch_location_ = branch_location; 9264 } 9265 uint32_t GetBranchLocation() const { return branch_location_; } 9266 void BindTable(uint32_t location) { table_location_ = location; } 9267 virtual void Link(MacroAssembler* masm, 9268 int case_index, 9269 uint32_t location) = 0; 9270 9271 uint32_t GetLocationForCase(int i) { 9272 VIXL_ASSERT((i >= 0) && (i < length_)); 9273 return table_location_ + (i * (1 << offset_shift_)); 9274 } 9275 void SetPresenceBitForCase(int i) { 9276 VIXL_ASSERT((i >= 0) && (i < length_)); 9277 presence_.Set(i); 9278 } 9279 9280 void Finalize(MacroAssembler* masm) { 9281 if (!default_.IsBound()) { 9282 masm->Bind(&default_); 9283 } 9284 masm->Bind(&end_); 9285 9286 presence_.ForEachBitNotSet(LinkIt(this, masm, default_.GetLocation())); 9287 } 9288 9289 private: 9290 uint32_t table_location_; 9291 uint32_t branch_location_; 9292 const int length_; 9293 const int offset_shift_; 9294 BitField presence_; 9295 Label default_; 9296 Label end_; 9297 struct LinkIt { 9298 JumpTableBase* table_; 9299 MacroAssembler* const masm_; 9300 const uint32_t location_; 9301 LinkIt(JumpTableBase* table, MacroAssembler* const masm, uint32_t location) 9302 : table_(table), masm_(masm), location_(location) {} 9303 bool execute(int id) const { 9304 VIXL_ASSERT(id < table_->GetLength()); 9305 table_->Link(masm_, static_cast<int>(id), location_); 9306 return true; 9307 } 9308 }; 9309}; 9310 9311// JumpTable<T>(len): Helper to describe a jump table 9312// len here describes the number of possible case. Values in [0, n[ can have a 9313// jump offset. Any other value will assert. 9314template <typename T> 9315class JumpTable : public JumpTableBase { 9316 protected: 9317 explicit JumpTable(int length) : JumpTableBase(length, sizeof(T)) {} 9318 9319 public: 9320 virtual void Link(MacroAssembler* masm, int case_index, uint32_t location) { 9321 uint32_t position_in_table = GetLocationForCase(case_index); 9322 uint32_t from = GetBranchLocation(); 9323 int offset = location - from; 9324 T* case_offset = masm->GetBuffer().GetOffsetAddress<T*>(position_in_table); 9325 if (masm->IsUsingT32()) { 9326 *case_offset = offset >> 1; 9327 } else { 9328 *case_offset = offset >> 2; 9329 } 9330 } 9331}; 9332 9333class JumpTable8bitOffset : public JumpTable<uint8_t> { 9334 public: 9335 explicit JumpTable8bitOffset(int length) : JumpTable<uint8_t>(length) {} 9336}; 9337 9338class JumpTable16bitOffset : public JumpTable<uint16_t> { 9339 public: 9340 explicit JumpTable16bitOffset(int length) : JumpTable<uint16_t>(length) {} 9341}; 9342 9343class JumpTable32bitOffset : public JumpTable<uint32_t> { 9344 public: 9345 explicit JumpTable32bitOffset(int length) : JumpTable<uint32_t>(length) {} 9346}; 9347 9348} // namespace aarch32 9349} // namespace vixl 9350 9351#endif // VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 9352