1/* ------------------------------------------------------------------
2 * Copyright (C) 1998-2009 PacketVideo
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
13 * express or implied.
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
17 */
18/*
19------------------------------------------------------------------------------
20   PacketVideo Corp.
21   MP3 Decoder Library
22
23   Pathname: ./cpp/include/pv_mp3dec_fxd_op_arm_gcc.h
24
25     Date: 08/20/2007
26
27------------------------------------------------------------------------------
28 REVISION HISTORY
29
30 Description:
31------------------------------------------------------------------------------
32 INCLUDE DESCRIPTION
33
34 This file select the associated fixed point functions with the OS/ARCH.
35
36
37------------------------------------------------------------------------------
38*/
39
40#ifndef PV_MP3DEC_FXD_OP_ARM_GCC_H
41#define PV_MP3DEC_FXD_OP_ARM_GCC_H
42
43
44#ifdef __cplusplus
45extern "C"
46{
47#endif
48
49#include "pvmp3_audio_type_defs.h"
50
51
52#if (defined(PV_ARM_GCC_V5)||defined(PV_ARM_GCC_V4))
53
54#define Qfmt_31(a)   (int32)(a*0x7FFFFFFF + (a>=0?0.5F:-0.5F))
55
56#define Qfmt15(x)   (Int16)(x*((int32)1<<15) + (x>=0?0.5F:-0.5F))
57
58    static inline int32 fxp_mul32_Q30(const int32 a, const int32 b)
59    {
60        int32 result64_hi;
61        int32 result64_lo;
62        register int32 ra = (int32)a;
63        register int32 rb = (int32)b;
64        asm volatile("smull %1, %0, %2, %3\n\t"
65                     "mov   %1, %1, lsr #30\n\t"
66                     "add   %0, %1, %0, asl #2"
67             : "=&r*i"(result64_hi),
68                     "=&r*i"(result64_lo)
69                             : "r"(ra),
70                             "r"(rb));
71        return (result64_hi);
72    }
73
74
75    static inline int32 fxp_mac32_Q30(const int32 a, const int32 b, int32 L_add)
76{
77        int32 result64_hi;
78        int32 result64_lo;
79        register int32 ra = (int32)a;
80        register int32 rb = (int32)b;
81        register int32 rc = (int32)L_add;
82
83        asm volatile("smull %1, %0, %2, %3\n\t"
84                     "add %4, %4, %0, asl #2\n\t"
85                     "add %0, %4, %1, lsr #30"
86             : "=&r*i"(result64_hi),
87                     "=&r*i"(result64_lo)
88                             : "r"(ra),
89                             "r"(rb),
90                             "r"(rc));
91
92        return (result64_hi);
93    }
94
95
96
97    static inline int32 fxp_mul32_Q32(const int32 a, const int32 b)
98{
99        int32 result64_hi;
100        int32 result64_lo;
101        register int32 ra = (int32)a;
102        register int32 rb = (int32)b;
103        asm volatile(
104            "smull %1, %0, %2, %3"
105    : "=&r*i"(result64_hi),
106            "=&r*i"(result64_lo)
107                    : "r"(ra),
108                    "r"(rb));
109
110        return (result64_hi);
111    }
112
113
114    static inline int32 fxp_mul32_Q29(const int32 a, const int32 b)
115{
116        int32 result64_hi;
117        int32 result64_lo;
118        register int32 ra = (int32)a;
119        register int32 rb = (int32)b;
120        asm volatile("smull %1, %0, %2, %3\n\t"
121                     "mov   %1, %1, lsr #29\n\t"
122                     "add   %0, %1, %0, asl #3"
123             : "=&r*i"(result64_hi),
124                     "=&r*i"(result64_lo)
125                             : "r"(ra),
126                             "r"(rb));
127        return (result64_hi);
128
129    }
130
131    static inline int32 fxp_mul32_Q28(const int32 a, const int32 b)
132{
133
134        int32 result64_hi;
135        int32 result64_lo;
136        register int32 ra = (int32)a;
137        register int32 rb = (int32)b;
138        asm volatile("smull %1, %0, %2, %3\n\t"
139                     "mov   %1, %1, lsr #28\n\t"
140                     "add   %0, %1, %0, asl #4"
141             : "=&r*i"(result64_hi),
142                     "=&r*i"(result64_lo)
143                             : "r"(ra),
144                             "r"(rb));
145        return (result64_hi);
146
147    }
148
149
150    static inline int32 fxp_mul32_Q27(const int32 a, const int32 b)
151{
152        int32 result64_hi;
153        int32 result64_lo;
154        register int32 ra = (int32)a;
155        register int32 rb = (int32)b;
156        asm volatile("smull %1, %0, %2, %3\n\t"
157                     "mov   %1, %1, lsr #27\n\t"
158                     "add   %0, %1, %0, asl #5"
159             : "=&r*i"(result64_hi),
160                     "=&r*i"(result64_lo)
161                             : "r"(ra),
162                             "r"(rb));
163        return (result64_hi);
164
165    }
166
167
168    static inline int32 fxp_mul32_Q26(const int32 a, const int32 b)
169{
170        int32 result64_hi;
171        int32 result64_lo;
172        register int32 ra = (int32)a;
173        register int32 rb = (int32)b;
174        asm volatile("smull %1, %0, %2, %3\n\t"
175                     "mov   %1, %1, lsr #26\n\t"
176                     "add   %0, %1, %0, asl #6"
177             : "=&r*i"(result64_hi),
178                     "=&r*i"(result64_lo)
179                             : "r"(ra),
180                             "r"(rb));
181        return (result64_hi);
182
183    }
184
185
186
187    static inline int32 fxp_mac32_Q32(int32 L_add, const int32 a, const int32 b)
188{
189
190        int32 result64_hi;
191        int32 result64_lo;
192        register int32 ra = (int32)a;
193        register int32 rb = (int32)b;
194        register int32 rc = (int32)L_add;
195
196        asm volatile("smull %1, %0, %2, %3\n\t"
197                     "add %0, %0, %4"
198             : "=&r*i"(result64_hi),
199                     "=&r*i"(result64_lo)
200                             : "r"(ra),
201                             "r"(rb),
202                             "r"(rc));
203
204        return (result64_hi);
205    }
206
207    static inline int32 fxp_msb32_Q32(int32 L_sub, const int32 a, const int32 b)
208{
209        int32 result64_hi;
210        int32 result64_lo;
211        register int32 ra = (int32)a;
212        register int32 rb = (int32)b;
213        register int32 rc = (int32)L_sub;
214
215        asm volatile("smull %1, %0, %2, %3\n\t"
216                     "sub %0, %4, %0"
217             : "=&r*i"(result64_hi),
218                     "=&r*i"(result64_lo)
219                             : "r"(ra),
220                             "r"(rb),
221                             "r"(rc));
222
223
224        return (result64_hi);
225    }
226
227
228    __inline int32 pv_abs(int32 x)
229{
230        register int32 z;
231        register int32 y;
232        register int32 ra = x;
233        asm volatile(
234            "sub  %0, %2, %2, lsr #31\n\t"
235            "eor  %1, %0, %0, asr #31"
236    : "=&r*i"(z),
237            "=&r*i"(y)
238                    : "r"(ra));
239
240        return (y);
241    }
242
243
244#endif
245
246#ifdef __cplusplus
247}
248#endif
249
250
251#endif   /*  PV_MP3DEC_FXD_OP_ARM_GCC_H  */
252
253