1/* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 27/****************************************************************************** 28 29 @File dxva_cmdseq_msg.h 30 31 @Title Debug driver 32 33 @Platform </b>\n 34 35 @Description </b>\n This file contains the VA_CMDSEQ_MSG_H Definitions. 36 37******************************************************************************/ 38#if !defined (__VA_CMDSEQ_MSG_H__) 39#define __VA_CMDSEQ_MSG_H__ 40 41#ifdef __cplusplus 42extern "C" { 43#endif 44 45 /* Deblock parameters */ 46 typedef struct { 47 uint32_t handle; /* struct ttm_buffer_object * of REGIO */ 48 uint32_t buffer_size; 49 uint32_t ctxid; 50 51 uint32_t *pPicparams; 52 void *regio_kmap; /* virtual of regio */ 53 uint32_t pad[3]; 54 } DEBLOCKPARAMS; 55 56 /* Host BE OPP parameters */ 57 typedef struct { 58 uint32_t handle; /* struct ttm_buffer_object * of REGIO */ 59 uint32_t buffer_stride; 60 uint32_t buffer_size; 61 uint32_t picture_width_mb; 62 uint32_t size_mb; 63 } FRAME_INFO_PARAMS; 64 65 typedef struct { 66 union { 67 struct { 68uint32_t msg_size : 69 8; 70uint32_t msg_type : 71 8; 72uint32_t msg_fence : 73 16; 74 } bits; 75 uint32_t value; 76 } header; 77 union { 78 struct { 79uint32_t flags : 80 16; 81uint32_t slice_type : 82 8; 83uint32_t padding : 84 8; 85 } bits; 86 uint32_t value; 87 } flags; 88 uint32_t operating_mode; 89 union { 90 struct { 91uint32_t context : 92 8; 93uint32_t mmu_ptd : 94 24; 95 } bits; 96 uint32_t value; 97 } mmu_context; 98 union { 99 struct { 100uint32_t frame_height_mb : 101 16; 102uint32_t pic_width_mb : 103 16; 104 } bits; 105 uint32_t value; 106 } pic_size; 107 uint32_t address_a0; 108 uint32_t address_a1; 109 uint32_t mb_param_address; 110 uint32_t ext_stride_a; 111 uint32_t address_b0; 112 uint32_t address_b1; 113 uint32_t rotation_flags; 114 /* additional msg outside of IMG msg */ 115 uint32_t address_c0; 116 uint32_t address_c1; 117 } FW_VA_DEBLOCK_MSG; 118 119 /* OOLD message */ 120 typedef struct { 121 uint32_t pad[5]; 122 uint32_t SOURCE_LUMA_BUFFER_ADDRESS; 123 uint32_t SOURCE_CHROMA_BUFFER_ADDRESS; 124 uint32_t SOURCE_MB_PARAM_ADDRESS; 125 uint32_t TARGET_LUMA_BUFFER_ADDRESS; 126 uint32_t TARGET_CHROMA_BUFFER_ADDRESS; 127 } FW_VA_OOLD_MSG; 128 129struct fw_slice_header_extract_msg { 130 union { 131 struct { 132 uint32_t msg_size:8; 133 uint32_t msg_type:8; 134 uint32_t msg_fence:16; 135 } bits; 136 uint32_t value; 137 } header; 138 139 union { 140 struct { 141 uint32_t flags:16; 142 uint32_t res:16; 143 } bits; 144 uint32_t value; 145 } flags; 146 147 uint32_t src; 148 149 union { 150 struct { 151 uint32_t context:8; 152 uint32_t mmu_ptd:24; 153 } bits; 154 uint32_t value; 155 } mmu_context; 156 157 uint32_t dst; 158 uint32_t src_size; 159 uint32_t dst_size; 160 161 union { 162 struct { 163 uint32_t expected_pps_id:8; 164 uint32_t nalu_header_unit_type:5; 165 uint32_t nalu_header_ref_idc:2; 166 uint32_t nalu_header_reserved:1; 167 uint32_t continue_parse_flag:1; 168 uint32_t frame_mbs_only_flag:1; 169 uint32_t pic_order_present_flag:1; 170 uint32_t delta_pic_order_always_zero_flag:1; 171 uint32_t redundant_pic_cnt_present_flag:1; 172 uint32_t weighted_pred_flag:1; 173 uint32_t entropy_coding_mode_flag:1; 174 uint32_t deblocking_filter_control_present_flag:1; 175 uint32_t weighted_bipred_idc:2; 176 uint32_t residual_colour_transform_flag:1; 177 uint32_t chroma_format_idc:2; 178 uint32_t idr_flag:1; 179 uint32_t pic_order_cnt_type:2; 180 } bits; 181 uint32_t value; 182 } flag_bitfield; 183 184 union { 185 struct { 186 uint8_t num_slice_groups_minus1:3; 187 uint8_t num_ref_idc_l1_active_minus1:5; 188 uint8_t slice_group_map_type:3; 189 uint8_t num_ref_idc_l0_active_minus1:5; 190 uint8_t log2_slice_group_change_cycle:4; 191 uint8_t slice_header_bit_offset:4; 192 uint8_t log2_max_frame_num_minus4:4; 193 uint8_t log2_max_pic_order_cnt_lsb_minus4:4; 194 } bits; 195 uint32_t value; 196 } pic_param0; 197}; 198 199#define FW_VA_RENDER_SIZE (32) 200 201// FW_VA_RENDER MSG_SIZE 202#define FW_VA_RENDER_MSG_SIZE_ALIGNMENT (1) 203#define FW_VA_RENDER_MSG_SIZE_TYPE IMG_UINT8 204#define FW_VA_RENDER_MSG_SIZE_MASK (0xFF) 205#define FW_VA_RENDER_MSG_SIZE_LSBMASK (0xFF) 206#define FW_VA_RENDER_MSG_SIZE_OFFSET (0x0000) 207#define FW_VA_RENDER_MSG_SIZE_SHIFT (0) 208 209// FW_VA_RENDER ID 210#define FW_VA_RENDER_ID_ALIGNMENT (1) 211#define FW_VA_RENDER_ID_TYPE IMG_UINT8 212#define FW_VA_RENDER_ID_MASK (0xFF) 213#define FW_VA_RENDER_ID_LSBMASK (0xFF) 214#define FW_VA_RENDER_ID_OFFSET (0x0001) 215#define FW_VA_RENDER_ID_SHIFT (0) 216 217// FW_VA_RENDER BUFFER_SIZE 218#define FW_VA_RENDER_BUFFER_SIZE_ALIGNMENT (2) 219#define FW_VA_RENDER_BUFFER_SIZE_TYPE IMG_UINT16 220#define FW_VA_RENDER_BUFFER_SIZE_MASK (0x0FFF) 221#define FW_VA_RENDER_BUFFER_SIZE_LSBMASK (0x0FFF) 222#define FW_VA_RENDER_BUFFER_SIZE_OFFSET (0x0002) 223#define FW_VA_RENDER_BUFFER_SIZE_SHIFT (0) 224 225// FW_VA_RENDER MMUPTD 226#define FW_VA_RENDER_MMUPTD_ALIGNMENT (4) 227#define FW_VA_RENDER_MMUPTD_TYPE IMG_UINT32 228#define FW_VA_RENDER_MMUPTD_MASK (0xFFFFFFFF) 229#define FW_VA_RENDER_MMUPTD_LSBMASK (0xFFFFFFFF) 230#define FW_VA_RENDER_MMUPTD_OFFSET (0x0004) 231#define FW_VA_RENDER_MMUPTD_SHIFT (0) 232 233// FW_VA_RENDER LLDMA_ADDRESS 234#define FW_VA_RENDER_LLDMA_ADDRESS_ALIGNMENT (4) 235#define FW_VA_RENDER_LLDMA_ADDRESS_TYPE IMG_UINT32 236#define FW_VA_RENDER_LLDMA_ADDRESS_MASK (0xFFFFFFFF) 237#define FW_VA_RENDER_LLDMA_ADDRESS_LSBMASK (0xFFFFFFFF) 238#define FW_VA_RENDER_LLDMA_ADDRESS_OFFSET (0x0008) 239#define FW_VA_RENDER_LLDMA_ADDRESS_SHIFT (0) 240 241// FW_VA_RENDER CONTEXT 242#define FW_VA_RENDER_CONTEXT_ALIGNMENT (4) 243#define FW_VA_RENDER_CONTEXT_TYPE IMG_UINT32 244#define FW_VA_RENDER_CONTEXT_MASK (0xFFFFFFFF) 245#define FW_VA_RENDER_CONTEXT_LSBMASK (0xFFFFFFFF) 246#define FW_VA_RENDER_CONTEXT_OFFSET (0x000C) 247#define FW_VA_RENDER_CONTEXT_SHIFT (0) 248 249// FW_VA_RENDER FENCE_VALUE 250#define FW_VA_RENDER_FENCE_VALUE_ALIGNMENT (4) 251#define FW_VA_RENDER_FENCE_VALUE_TYPE IMG_UINT32 252#define FW_VA_RENDER_FENCE_VALUE_MASK (0xFFFFFFFF) 253#define FW_VA_RENDER_FENCE_VALUE_LSBMASK (0xFFFFFFFF) 254#define FW_VA_RENDER_FENCE_VALUE_OFFSET (0x0010) 255#define FW_VA_RENDER_FENCE_VALUE_SHIFT (0) 256 257// FW_VA_RENDER OPERATING_MODE 258#define FW_VA_RENDER_OPERATING_MODE_ALIGNMENT (4) 259#define FW_VA_RENDER_OPERATING_MODE_TYPE IMG_UINT32 260#define FW_VA_RENDER_OPERATING_MODE_MASK (0xFFFFFFFF) 261#define FW_VA_RENDER_OPERATING_MODE_LSBMASK (0xFFFFFFFF) 262#define FW_VA_RENDER_OPERATING_MODE_OFFSET (0x0014) 263#define FW_VA_RENDER_OPERATING_MODE_SHIFT (0) 264 265// FW_VA_RENDER FIRST_MB_IN_SLICE 266#define FW_VA_RENDER_FIRST_MB_IN_SLICE_ALIGNMENT (2) 267#define FW_VA_RENDER_FIRST_MB_IN_SLICE_TYPE IMG_UINT16 268#define FW_VA_RENDER_FIRST_MB_IN_SLICE_MASK (0xFFFF) 269#define FW_VA_RENDER_FIRST_MB_IN_SLICE_LSBMASK (0xFFFF) 270#define FW_VA_RENDER_FIRST_MB_IN_SLICE_OFFSET (0x0018) 271#define FW_VA_RENDER_FIRST_MB_IN_SLICE_SHIFT (0) 272 273// FW_VA_RENDER LAST_MB_IN_FRAME 274#define FW_VA_RENDER_LAST_MB_IN_FRAME_ALIGNMENT (2) 275#define FW_VA_RENDER_LAST_MB_IN_FRAME_TYPE IMG_UINT16 276#define FW_VA_RENDER_LAST_MB_IN_FRAME_MASK (0xFFFF) 277#define FW_VA_RENDER_LAST_MB_IN_FRAME_LSBMASK (0xFFFF) 278#define FW_VA_RENDER_LAST_MB_IN_FRAME_OFFSET (0x001A) 279#define FW_VA_RENDER_LAST_MB_IN_FRAME_SHIFT (0) 280 281// FW_VA_RENDER FLAGS 282#define FW_VA_RENDER_FLAGS_ALIGNMENT (4) 283#define FW_VA_RENDER_FLAGS_TYPE IMG_UINT32 284#define FW_VA_RENDER_FLAGS_MASK (0xFFFFFFFF) 285#define FW_VA_RENDER_FLAGS_LSBMASK (0xFFFFFFFF) 286#define FW_VA_RENDER_FLAGS_OFFSET (0x001C) 287#define FW_VA_RENDER_FLAGS_SHIFT (0) 288 289#define FW_DEVA_DECODE_SIZE (20) 290 291// FW_DEVA_DECODE MSG_ID 292#define FW_DEVA_DECODE_MSG_ID_ALIGNMENT (2) 293#define FW_DEVA_DECODE_MSG_ID_TYPE IMG_UINT16 294#define FW_DEVA_DECODE_MSG_ID_MASK (0xFFFF) 295#define FW_DEVA_DECODE_MSG_ID_LSBMASK (0xFFFF) 296#define FW_DEVA_DECODE_MSG_ID_OFFSET (0x0002) 297#define FW_DEVA_DECODE_MSG_ID_SHIFT (0) 298 299// FW_DEVA_DECODE ID 300#define FW_DEVA_DECODE_ID_ALIGNMENT (1) 301#define FW_DEVA_DECODE_ID_TYPE IMG_UINT8 302#define FW_DEVA_DECODE_ID_MASK (0xFF) 303#define FW_DEVA_DECODE_ID_LSBMASK (0xFF) 304#define FW_DEVA_DECODE_ID_OFFSET (0x0001) 305#define FW_DEVA_DECODE_ID_SHIFT (0) 306 307// FW_DEVA_DECODE MSG_SIZE 308#define FW_DEVA_DECODE_MSG_SIZE_ALIGNMENT (1) 309#define FW_DEVA_DECODE_MSG_SIZE_TYPE IMG_UINT8 310#define FW_DEVA_DECODE_MSG_SIZE_MASK (0xFF) 311#define FW_DEVA_DECODE_MSG_SIZE_LSBMASK (0xFF) 312#define FW_DEVA_DECODE_MSG_SIZE_OFFSET (0x0000) 313#define FW_DEVA_DECODE_MSG_SIZE_SHIFT (0) 314 315// FW_DEVA_DECODE FLAGS 316#define FW_DEVA_DECODE_FLAGS_ALIGNMENT (2) 317#define FW_DEVA_DECODE_FLAGS_TYPE IMG_UINT16 318#define FW_DEVA_DECODE_FLAGS_MASK (0xFFFF) 319#define FW_DEVA_DECODE_FLAGS_LSBMASK (0xFFFF) 320#define FW_DEVA_DECODE_FLAGS_OFFSET (0x0004) 321#define FW_DEVA_DECODE_FLAGS_SHIFT (0) 322 323// FW_DEVA_DECODE BUFFER_SIZE 324#define FW_DEVA_DECODE_BUFFER_SIZE_ALIGNMENT (2) 325#define FW_DEVA_DECODE_BUFFER_SIZE_TYPE IMG_UINT16 326#define FW_DEVA_DECODE_BUFFER_SIZE_MASK (0xFFFF) 327#define FW_DEVA_DECODE_BUFFER_SIZE_LSBMASK (0xFFFF) 328#define FW_DEVA_DECODE_BUFFER_SIZE_OFFSET (0x0006) 329#define FW_DEVA_DECODE_BUFFER_SIZE_SHIFT (0) 330 331// FW_DEVA_DECODE LLDMA_ADDRESS 332#define FW_DEVA_DECODE_LLDMA_ADDRESS_ALIGNMENT (4) 333#define FW_DEVA_DECODE_LLDMA_ADDRESS_TYPE IMG_UINT32 334#define FW_DEVA_DECODE_LLDMA_ADDRESS_MASK (0xFFFFFFFF) 335#define FW_DEVA_DECODE_LLDMA_ADDRESS_LSBMASK (0xFFFFFFFF) 336#define FW_DEVA_DECODE_LLDMA_ADDRESS_OFFSET (0x0008) 337#define FW_DEVA_DECODE_LLDMA_ADDRESS_SHIFT (0) 338 339// FW_DEVA_DECODE MMUPTD 340#define FW_DEVA_DECODE_MMUPTD_ALIGNMENT (4) 341#define FW_DEVA_DECODE_MMUPTD_TYPE IMG_UINT32 342#define FW_DEVA_DECODE_MMUPTD_MASK (0xFFFFFF00) 343#define FW_DEVA_DECODE_MMUPTD_LSBMASK (0x00FFFFFF) 344#define FW_DEVA_DECODE_MMUPTD_OFFSET (0x000C) 345#define FW_DEVA_DECODE_MMUPTD_SHIFT (8) 346 347// FW_DEVA_DECODE CONTEXT 348#define FW_DEVA_DECODE_CONTEXT_ALIGNMENT (1) 349#define FW_DEVA_DECODE_CONTEXT_TYPE IMG_UINT8 350#define FW_DEVA_DECODE_CONTEXT_MASK (0xFF) 351#define FW_DEVA_DECODE_CONTEXT_LSBMASK (0xFF) 352#define FW_DEVA_DECODE_CONTEXT_OFFSET (0x000C) 353 354#define FW_VA_DEBLOCK_SIZE (16 + 32) /* 32 bytes for DEBLOCKPARAMS */ 355#define FW_DEVA_DEBLOCK_SIZE (48) 356 357#define FW_DEVA_DECODE_CONTEXT_SHIFT (0) 358 359// FW_DEVA_DECODE OPERATING_MODE 360#define FW_DEVA_DECODE_OPERATING_MODE_ALIGNMENT (4) 361#define FW_DEVA_DECODE_OPERATING_MODE_TYPE IMG_UINT32 362#define FW_DEVA_DECODE_OPERATING_MODE_MASK (0xFFFFFFFF) 363#define FW_DEVA_DECODE_OPERATING_MODE_LSBMASK (0xFFFFFFFF) 364#define FW_DEVA_DECODE_OPERATING_MODE_OFFSET (0x0010) 365#define FW_DEVA_DECODE_OPERATING_MODE_SHIFT (0) 366 367// FW_VA_DEBLOCK MSG_SIZE 368#define FW_VA_DEBLOCK_MSG_SIZE_ALIGNMENT (1) 369#define FW_VA_DEBLOCK_MSG_SIZE_TYPE IMG_UINT8 370#define FW_VA_DEBLOCK_MSG_SIZE_MASK (0xFF) 371#define FW_VA_DEBLOCK_MSG_SIZE_LSBMASK (0xFF) 372#define FW_VA_DEBLOCK_MSG_SIZE_OFFSET (0x0000) 373#define FW_VA_DEBLOCK_MSG_SIZE_SHIFT (0) 374 375// FW_VA_DEBLOCK ID 376#define FW_VA_DEBLOCK_ID_ALIGNMENT (1) 377#define FW_VA_DEBLOCK_ID_TYPE IMG_UINT8 378#define FW_VA_DEBLOCK_ID_MASK (0xFF) 379#define FW_VA_DEBLOCK_ID_LSBMASK (0xFF) 380#define FW_VA_DEBLOCK_ID_OFFSET (0x0001) 381#define FW_VA_DEBLOCK_ID_SHIFT (0) 382 383// FW_VA_DEBLOCK FLAGS 384#define FW_VA_DEBLOCK_FLAGS_ALIGNMENT (2) 385#define FW_VA_DEBLOCK_FLAGS_TYPE IMG_UINT16 386#define FW_VA_DEBLOCK_FLAGS_MASK (0xFFFF) 387#define FW_VA_DEBLOCK_FLAGS_LSBMASK (0xFFFF) 388#define FW_VA_DEBLOCK_FLAGS_OFFSET (0x0002) 389#define FW_VA_DEBLOCK_FLAGS_SHIFT (0) 390 391// FW_VA_DEBLOCK CONTEXT 392#define FW_VA_DEBLOCK_CONTEXT_ALIGNMENT (4) 393#define FW_VA_DEBLOCK_CONTEXT_TYPE IMG_UINT32 394#define FW_VA_DEBLOCK_CONTEXT_MASK (0xFFFFFFFF) 395#define FW_VA_DEBLOCK_CONTEXT_LSBMASK (0xFFFFFFFF) 396#define FW_VA_DEBLOCK_CONTEXT_OFFSET (0x0004) 397#define FW_VA_DEBLOCK_CONTEXT_SHIFT (0) 398 399// FW_VA_DEBLOCK FENCE_VALUE 400#define FW_VA_DEBLOCK_FENCE_VALUE_ALIGNMENT (4) 401#define FW_VA_DEBLOCK_FENCE_VALUE_TYPE IMG_UINT32 402#define FW_VA_DEBLOCK_FENCE_VALUE_MASK (0xFFFFFFFF) 403#define FW_VA_DEBLOCK_FENCE_VALUE_LSBMASK (0xFFFFFFFF) 404#define FW_VA_DEBLOCK_FENCE_VALUE_OFFSET (0x0008) 405#define FW_VA_DEBLOCK_FENCE_VALUE_SHIFT (0) 406 407// FW_VA_DEBLOCK MMUPTD 408#define FW_VA_DEBLOCK_MMUPTD_ALIGNMENT (4) 409#define FW_VA_DEBLOCK_MMUPTD_TYPE IMG_UINT32 410#define FW_VA_DEBLOCK_MMUPTD_MASK (0xFFFFFFFF) 411#define FW_VA_DEBLOCK_MMUPTD_LSBMASK (0xFFFFFFFF) 412#define FW_VA_DEBLOCK_MMUPTD_OFFSET (0x000C) 413#define FW_VA_DEBLOCK_MMUPTD_SHIFT (0) 414 415#define FW_VA_OOLD_SIZE (40) 416 417// FW_VA_OOLD MSG_SIZE 418#define FW_VA_OOLD_MSG_SIZE_ALIGNMENT (1) 419#define FW_VA_OOLD_MSG_SIZE_TYPE IMG_UINT8 420#define FW_VA_OOLD_MSG_SIZE_MASK (0xFF) 421#define FW_VA_OOLD_MSG_SIZE_LSBMASK (0xFF) 422#define FW_VA_OOLD_MSG_SIZE_OFFSET (0x0000) 423#define FW_VA_OOLD_MSG_SIZE_SHIFT (0) 424 425// FW_VA_OOLD ID 426#define FW_VA_OOLD_ID_ALIGNMENT (1) 427#define FW_VA_OOLD_ID_TYPE IMG_UINT8 428#define FW_VA_OOLD_ID_MASK (0xFF) 429#define FW_VA_OOLD_ID_LSBMASK (0xFF) 430#define FW_VA_OOLD_ID_OFFSET (0x0001) 431#define FW_VA_OOLD_ID_SHIFT (0) 432 433// FW_VA_OOLD SLICE_FIELD_TYPE 434#define FW_VA_OOLD_SLICE_FIELD_TYPE_ALIGNMENT (1) 435#define FW_VA_OOLD_SLICE_FIELD_TYPE_TYPE IMG_UINT8 436#define FW_VA_OOLD_SLICE_FIELD_TYPE_MASK (0x03) 437#define FW_VA_OOLD_SLICE_FIELD_TYPE_LSBMASK (0x03) 438#define FW_VA_OOLD_SLICE_FIELD_TYPE_OFFSET (0x0002) 439#define FW_VA_OOLD_SLICE_FIELD_TYPE_SHIFT (0) 440 441// FW_VA_OOLD MMUPTD 442#define FW_VA_OOLD_MMUPTD_ALIGNMENT (4) 443#define FW_VA_OOLD_MMUPTD_TYPE IMG_UINT32 444#define FW_VA_OOLD_MMUPTD_MASK (0xFFFFFFFF) 445#define FW_VA_OOLD_MMUPTD_LSBMASK (0xFFFFFFFF) 446#define FW_VA_OOLD_MMUPTD_OFFSET (0x0004) 447#define FW_VA_OOLD_MMUPTD_SHIFT (0) 448 449// FW_VA_OOLD FENCE_VALUE 450#define FW_VA_OOLD_FENCE_VALUE_ALIGNMENT (4) 451#define FW_VA_OOLD_FENCE_VALUE_TYPE IMG_UINT32 452#define FW_VA_OOLD_FENCE_VALUE_MASK (0xFFFFFFFF) 453#define FW_VA_OOLD_FENCE_VALUE_LSBMASK (0xFFFFFFFF) 454#define FW_VA_OOLD_FENCE_VALUE_OFFSET (0x0008) 455#define FW_VA_OOLD_FENCE_VALUE_SHIFT (0) 456 457// FW_VA_OOLD OPERATING_MODE 458#define FW_VA_OOLD_OPERATING_MODE_ALIGNMENT (4) 459#define FW_VA_OOLD_OPERATING_MODE_TYPE IMG_UINT32 460#define FW_VA_OOLD_OPERATING_MODE_MASK (0xFFFFFFFF) 461#define FW_VA_OOLD_OPERATING_MODE_LSBMASK (0xFFFFFFFF) 462#define FW_VA_OOLD_OPERATING_MODE_OFFSET (0x000C) 463#define FW_VA_OOLD_OPERATING_MODE_SHIFT (0) 464 465// FW_VA_OOLD FRAME_HEIGHT_MBS 466#define FW_VA_OOLD_FRAME_HEIGHT_MBS_ALIGNMENT (2) 467#define FW_VA_OOLD_FRAME_HEIGHT_MBS_TYPE IMG_UINT16 468#define FW_VA_OOLD_FRAME_HEIGHT_MBS_MASK (0xFFFF) 469#define FW_VA_OOLD_FRAME_HEIGHT_MBS_LSBMASK (0xFFFF) 470#define FW_VA_OOLD_FRAME_HEIGHT_MBS_OFFSET (0x0010) 471#define FW_VA_OOLD_FRAME_HEIGHT_MBS_SHIFT (0) 472 473// FW_VA_OOLD PIC_WIDTH_MBS 474#define FW_VA_OOLD_PIC_WIDTH_MBS_ALIGNMENT (2) 475#define FW_VA_OOLD_PIC_WIDTH_MBS_TYPE IMG_UINT16 476#define FW_VA_OOLD_PIC_WIDTH_MBS_MASK (0xFFFF) 477#define FW_VA_OOLD_PIC_WIDTH_MBS_LSBMASK (0xFFFF) 478#define FW_VA_OOLD_PIC_WIDTH_MBS_OFFSET (0x0012) 479#define FW_VA_OOLD_PIC_WIDTH_MBS_SHIFT (0) 480 481// FW_VA_OOLD SOURCE_LUMA_BUFFER_ADDRESS 482#define FW_VA_OOLD_SOURCE_LUMA_BUFFER_ADDRESS_ALIGNMENT (4) 483#define FW_VA_OOLD_SOURCE_LUMA_BUFFER_ADDRESS_TYPE IMG_UINT32 484#define FW_VA_OOLD_SOURCE_LUMA_BUFFER_ADDRESS_MASK (0xFFFFFFFF) 485#define FW_VA_OOLD_SOURCE_LUMA_BUFFER_ADDRESS_LSBMASK (0xFFFFFFFF) 486#define FW_VA_OOLD_SOURCE_LUMA_BUFFER_ADDRESS_OFFSET (0x0014) 487#define FW_VA_OOLD_SOURCE_LUMA_BUFFER_ADDRESS_SHIFT (0) 488 489// FW_VA_OOLD SOURCE_CHROMA_BUFFER_ADDRESS 490#define FW_VA_OOLD_SOURCE_CHROMA_BUFFER_ADDRESS_ALIGNMENT (4) 491#define FW_VA_OOLD_SOURCE_CHROMA_BUFFER_ADDRESS_TYPE IMG_UINT32 492#define FW_VA_OOLD_SOURCE_CHROMA_BUFFER_ADDRESS_MASK (0xFFFFFFFF) 493#define FW_VA_OOLD_SOURCE_CHROMA_BUFFER_ADDRESS_LSBMASK (0xFFFFFFFF) 494#define FW_VA_OOLD_SOURCE_CHROMA_BUFFER_ADDRESS_OFFSET (0x0018) 495#define FW_VA_OOLD_SOURCE_CHROMA_BUFFER_ADDRESS_SHIFT (0) 496 497// FW_VA_OOLD SOURCE_MB_PARAM_ADDRESS 498#define FW_VA_OOLD_SOURCE_MB_PARAM_ADDRESS_ALIGNMENT (4) 499#define FW_VA_OOLD_SOURCE_MB_PARAM_ADDRESS_TYPE IMG_UINT32 500#define FW_VA_OOLD_SOURCE_MB_PARAM_ADDRESS_MASK (0xFFFFFFFF) 501#define FW_VA_OOLD_SOURCE_MB_PARAM_ADDRESS_LSBMASK (0xFFFFFFFF) 502#define FW_VA_OOLD_SOURCE_MB_PARAM_ADDRESS_OFFSET (0x001C) 503#define FW_VA_OOLD_SOURCE_MB_PARAM_ADDRESS_SHIFT (0) 504 505// FW_VA_OOLD TARGET_LUMA_BUFFER_ADDRESS 506#define FW_VA_OOLD_TARGET_LUMA_BUFFER_ADDRESS_ALIGNMENT (4) 507#define FW_VA_OOLD_TARGET_LUMA_BUFFER_ADDRESS_TYPE IMG_UINT32 508#define FW_VA_OOLD_TARGET_LUMA_BUFFER_ADDRESS_MASK (0xFFFFFFFF) 509#define FW_VA_OOLD_TARGET_LUMA_BUFFER_ADDRESS_LSBMASK (0xFFFFFFFF) 510#define FW_VA_OOLD_TARGET_LUMA_BUFFER_ADDRESS_OFFSET (0x0020) 511#define FW_VA_OOLD_TARGET_LUMA_BUFFER_ADDRESS_SHIFT (0) 512 513// FW_VA_OOLD TARGET_CHROMA_BUFFER_ADDRESS 514#define FW_VA_OOLD_TARGET_CHROMA_BUFFER_ADDRESS_ALIGNMENT (4) 515#define FW_VA_OOLD_TARGET_CHROMA_BUFFER_ADDRESS_TYPE IMG_UINT32 516#define FW_VA_OOLD_TARGET_CHROMA_BUFFER_ADDRESS_MASK (0xFFFFFFFF) 517#define FW_VA_OOLD_TARGET_CHROMA_BUFFER_ADDRESS_LSBMASK (0xFFFFFFFF) 518#define FW_VA_OOLD_TARGET_CHROMA_BUFFER_ADDRESS_OFFSET (0x0024) 519#define FW_VA_OOLD_TARGET_CHROMA_BUFFER_ADDRESS_SHIFT (0) 520 521#define FW_VA_CMD_COMPLETED_SIZE (12) 522 523// FW_VA_CMD_COMPLETED MSG_SIZE 524#define FW_VA_CMD_COMPLETED_MSG_SIZE_ALIGNMENT (1) 525#define FW_VA_CMD_COMPLETED_MSG_SIZE_TYPE IMG_UINT8 526#define FW_VA_CMD_COMPLETED_MSG_SIZE_MASK (0xFF) 527#define FW_VA_CMD_COMPLETED_MSG_SIZE_LSBMASK (0xFF) 528#define FW_VA_CMD_COMPLETED_MSG_SIZE_OFFSET (0x0000) 529#define FW_VA_CMD_COMPLETED_MSG_SIZE_SHIFT (0) 530 531// FW_VA_CMD_COMPLETED ID 532#define FW_VA_CMD_COMPLETED_ID_ALIGNMENT (1) 533#define FW_VA_CMD_COMPLETED_ID_TYPE IMG_UINT8 534#define FW_VA_CMD_COMPLETED_ID_MASK (0xFF) 535#define FW_VA_CMD_COMPLETED_ID_LSBMASK (0xFF) 536#define FW_VA_CMD_COMPLETED_ID_OFFSET (0x0001) 537#define FW_VA_CMD_COMPLETED_ID_SHIFT (0) 538 539// FW_VA_CMD_COMPLETED FENCE_VALUE 540#define FW_VA_CMD_COMPLETED_FENCE_VALUE_ALIGNMENT (4) 541#define FW_VA_CMD_COMPLETED_FENCE_VALUE_TYPE IMG_UINT32 542#define FW_VA_CMD_COMPLETED_FENCE_VALUE_MASK (0xFFFFFFFF) 543#define FW_VA_CMD_COMPLETED_FENCE_VALUE_LSBMASK (0xFFFFFFFF) 544#define FW_VA_CMD_COMPLETED_FENCE_VALUE_OFFSET (0x0004) 545#define FW_VA_CMD_COMPLETED_FENCE_VALUE_SHIFT (0) 546 547// FW_VA_CMD_COMPLETED FLAGS 548#define FW_VA_CMD_COMPLETED_FLAGS_ALIGNMENT (4) 549#define FW_VA_CMD_COMPLETED_FLAGS_TYPE IMG_UINT32 550#define FW_VA_CMD_COMPLETED_FLAGS_MASK (0xFFFFFFFF) 551#define FW_VA_CMD_COMPLETED_FLAGS_LSBMASK (0xFFFFFFFF) 552#define FW_VA_CMD_COMPLETED_FLAGS_OFFSET (0x0008) 553#define FW_VA_CMD_COMPLETED_FLAGS_SHIFT (0) 554 555#define FW_VA_CMD_FAILED_SIZE (12) 556 557// FW_VA_CMD_FAILED MSG_SIZE 558#define FW_VA_CMD_FAILED_MSG_SIZE_ALIGNMENT (1) 559#define FW_VA_CMD_FAILED_MSG_SIZE_TYPE IMG_UINT8 560#define FW_VA_CMD_FAILED_MSG_SIZE_MASK (0xFF) 561#define FW_VA_CMD_FAILED_MSG_SIZE_LSBMASK (0xFF) 562#define FW_VA_CMD_FAILED_MSG_SIZE_OFFSET (0x0000) 563#define FW_VA_CMD_FAILED_MSG_SIZE_SHIFT (0) 564 565// FW_VA_CMD_FAILED ID 566#define FW_VA_CMD_FAILED_ID_ALIGNMENT (1) 567#define FW_VA_CMD_FAILED_ID_TYPE IMG_UINT8 568#define FW_VA_CMD_FAILED_ID_MASK (0xFF) 569#define FW_VA_CMD_FAILED_ID_LSBMASK (0xFF) 570#define FW_VA_CMD_FAILED_ID_OFFSET (0x0001) 571#define FW_VA_CMD_FAILED_ID_SHIFT (0) 572 573// FW_VA_CMD_FAILED FLAGS 574#define FW_VA_CMD_FAILED_FLAGS_ALIGNMENT (2) 575#define FW_VA_CMD_FAILED_FLAGS_TYPE IMG_UINT16 576#define FW_VA_CMD_FAILED_FLAGS_MASK (0xFFFF) 577#define FW_VA_CMD_FAILED_FLAGS_LSBMASK (0xFFFF) 578#define FW_VA_CMD_FAILED_FLAGS_OFFSET (0x0002) 579#define FW_VA_CMD_FAILED_FLAGS_SHIFT (0) 580 581// FW_VA_CMD_FAILED FENCE_VALUE 582#define FW_VA_CMD_FAILED_FENCE_VALUE_ALIGNMENT (4) 583#define FW_VA_CMD_FAILED_FENCE_VALUE_TYPE IMG_UINT32 584#define FW_VA_CMD_FAILED_FENCE_VALUE_MASK (0xFFFFFFFF) 585#define FW_VA_CMD_FAILED_FENCE_VALUE_LSBMASK (0xFFFFFFFF) 586#define FW_VA_CMD_FAILED_FENCE_VALUE_OFFSET (0x0004) 587#define FW_VA_CMD_FAILED_FENCE_VALUE_SHIFT (0) 588 589// FW_VA_CMD_FAILED IRQSTATUS 590#define FW_VA_CMD_FAILED_IRQSTATUS_ALIGNMENT (4) 591#define FW_VA_CMD_FAILED_IRQSTATUS_TYPE IMG_UINT32 592#define FW_VA_CMD_FAILED_IRQSTATUS_MASK (0xFFFFFFFF) 593#define FW_VA_CMD_FAILED_IRQSTATUS_LSBMASK (0xFFFFFFFF) 594#define FW_VA_CMD_FAILED_IRQSTATUS_OFFSET (0x0008) 595#define FW_VA_CMD_FAILED_IRQSTATUS_SHIFT (0) 596 597#define FW_VA_DEBLOCK_REQUIRED_SIZE (8) 598 599// FW_VA_DEBLOCK_REQUIRED MSG_SIZE 600#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_ALIGNMENT (1) 601#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_TYPE IMG_UINT8 602#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_MASK (0xFF) 603#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_LSBMASK (0xFF) 604#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_OFFSET (0x0000) 605#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_SHIFT (0) 606 607// FW_VA_DEBLOCK_REQUIRED ID 608#define FW_VA_DEBLOCK_REQUIRED_ID_ALIGNMENT (1) 609#define FW_VA_DEBLOCK_REQUIRED_ID_TYPE IMG_UINT8 610#define FW_VA_DEBLOCK_REQUIRED_ID_MASK (0xFF) 611#define FW_VA_DEBLOCK_REQUIRED_ID_LSBMASK (0xFF) 612#define FW_VA_DEBLOCK_REQUIRED_ID_OFFSET (0x0001) 613#define FW_VA_DEBLOCK_REQUIRED_ID_SHIFT (0) 614 615// FW_VA_DEBLOCK_REQUIRED CONTEXT 616#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_ALIGNMENT (4) 617#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_TYPE IMG_UINT32 618#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_MASK (0xFFFFFFFF) 619#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_LSBMASK (0xFFFFFFFF) 620#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_OFFSET (0x0004) 621#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_SHIFT (0) 622 623#define FW_VA_HW_PANIC_SIZE (12) 624 625// FW_VA_HW_PANIC FLAGS 626#define FW_VA_HW_PANIC_FLAGS_ALIGNMENT (2) 627#define FW_VA_HW_PANIC_FLAGS_TYPE IMG_UINT16 628#define FW_VA_HW_PANIC_FLAGS_MASK (0xFFFF) 629#define FW_VA_HW_PANIC_FLAGS_LSBMASK (0xFFFF) 630#define FW_VA_HW_PANIC_FLAGS_OFFSET (0x0002) 631#define FW_VA_HW_PANIC_FLAGS_SHIFT (0) 632 633// FW_VA_HW_PANIC MSG_SIZE 634#define FW_VA_HW_PANIC_MSG_SIZE_ALIGNMENT (1) 635#define FW_VA_HW_PANIC_MSG_SIZE_TYPE IMG_UINT8 636#define FW_VA_HW_PANIC_MSG_SIZE_MASK (0xFF) 637#define FW_VA_HW_PANIC_MSG_SIZE_LSBMASK (0xFF) 638#define FW_VA_HW_PANIC_MSG_SIZE_OFFSET (0x0000) 639#define FW_VA_HW_PANIC_MSG_SIZE_SHIFT (0) 640 641// FW_VA_HW_PANIC ID 642#define FW_VA_HW_PANIC_ID_ALIGNMENT (1) 643#define FW_VA_HW_PANIC_ID_TYPE IMG_UINT8 644#define FW_VA_HW_PANIC_ID_MASK (0xFF) 645#define FW_VA_HW_PANIC_ID_LSBMASK (0xFF) 646#define FW_VA_HW_PANIC_ID_OFFSET (0x0001) 647#define FW_VA_HW_PANIC_ID_SHIFT (0) 648 649// FW_VA_HW_PANIC FENCE_VALUE 650#define FW_VA_HW_PANIC_FENCE_VALUE_ALIGNMENT (4) 651#define FW_VA_HW_PANIC_FENCE_VALUE_TYPE IMG_UINT32 652#define FW_VA_HW_PANIC_FENCE_VALUE_MASK (0xFFFFFFFF) 653#define FW_VA_HW_PANIC_FENCE_VALUE_LSBMASK (0xFFFFFFFF) 654#define FW_VA_HW_PANIC_FENCE_VALUE_OFFSET (0x0004) 655#define FW_VA_HW_PANIC_FENCE_VALUE_SHIFT (0) 656 657// FW_VA_HW_PANIC IRQSTATUS 658#define FW_VA_HW_PANIC_IRQSTATUS_ALIGNMENT (4) 659#define FW_VA_HW_PANIC_IRQSTATUS_TYPE IMG_UINT32 660#define FW_VA_HW_PANIC_IRQSTATUS_MASK (0xFFFFFFFF) 661#define FW_VA_HW_PANIC_IRQSTATUS_LSBMASK (0xFFFFFFFF) 662#define FW_VA_HW_PANIC_IRQSTATUS_OFFSET (0x0008) 663#define FW_VA_HW_PANIC_IRQSTATUS_SHIFT (0) 664 665#define FW_VA_HOST_BE_OPP_SIZE 48 666// FW_VA_HOST_BE_OPP CONTEXT 667#define FW_VA_HOST_BE_OPP_CONTEXT_ALIGNMENT (1) 668#define FW_VA_HOST_BE_OPP_CONTEXT_TYPE IMG_UINT8 669#define FW_VA_HOST_BE_OPP_CONTEXT_MASK (0xF) 670#define FW_VA_HOST_BE_OPP_CONTEXT_LSBMASK (0xF) 671#define FW_VA_HOST_BE_OPP_CONTEXT_OFFSET (0x000C) 672#define FW_VA_HOST_BE_OPP_CONTEXT_SHIFT (0) 673 674// FW_VA_HOST_BE_OPP FLAGS 675#define FW_VA_HOST_BE_OPP_FLAGS_ALIGNMENT (2) 676#define FW_VA_HOST_BE_OPP_FLAGS_TYPE IMG_UINT16 677#define FW_VA_HOST_BE_OPP_FLAGS_MASK (0xFFFF) 678#define FW_VA_HOST_BE_OPP_FLAGS_LSBMASK (0xFFFF) 679#define FW_VA_HOST_BE_OPP_FLAGS_OFFSET (0x0004) 680#define FW_VA_HOST_BE_OPP_FLAGS_SHIFT (0) 681 682#define FW_VA_FRAME_INFO_SIZE 24 /* 20 bytes for FRAME_INFO_PARAMS */ 683 684#ifdef __cplusplus 685} 686#endif 687 688#endif /* __VA_CMDSEQ_MSG_H__ */ 689