111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/*- 211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG> 311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * All rights reserved. 411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Redistribution and use in source and binary forms, with or without 611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * modification, are permitted provided that the following conditions 711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * are met: 811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 1. Redistributions of source code must retain the above copyright 911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * notice, this list of conditions and the following disclaimer. 1011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 2. Redistributions in binary form must reproduce the above copyright 1111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * notice, this list of conditions and the following disclaimer in the 1211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * documentation and/or other materials provided with the distribution. 1311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 1411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * SUCH DAMAGE. 2511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 2611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 2711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef _AMD64_FENV_H_ 2811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _AMD64_FENV_H_ 2911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 3011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#include <sys/types.h> 3111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 3211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert__BEGIN_DECLS 3311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 3411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* 3511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Each symbol representing a floating point exception expands to an integer 3611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * constant expression with values, such that bitwise-inclusive ORs of _all 3711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * combinations_ of the constants result in distinct values. 3811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 3911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * We use such values that allow direct bitwise operations on FPU/SSE registers. 4011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 4111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_INVALID 0x01 4211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_DENORMAL 0x02 4311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_DIVBYZERO 0x04 4411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_OVERFLOW 0x08 4511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_UNDERFLOW 0x10 4611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_INEXACT 0x20 4711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 4811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* 4911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * The following symbol is simply the bitwise-inclusive OR of all floating-point 5011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * exception constants defined above. 5111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 5211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_ALL_EXCEPT (FE_INVALID | FE_DENORMAL | FE_DIVBYZERO | \ 5311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT) 5411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 5511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* 5611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Each symbol representing the rounding direction, expands to an integer 5711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * constant expression whose value is distinct non-negative value. 5811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 5911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * We use such values that allow direct bitwise operations on FPU/SSE registers. 6011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 6111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_TONEAREST 0x000 6211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_DOWNWARD 0x400 6311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_UPWARD 0x800 6411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_TOWARDZERO 0xc00 6511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 6611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* 6711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * fenv_t represents the entire floating-point environment. 6811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 6911cd02dfb91661c65134cac258cf5924270e9d2Dan Alberttypedef struct { 7011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert struct { 7111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __uint32_t __control; /* Control word register */ 7211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __uint32_t __status; /* Status word register */ 7311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __uint32_t __tag; /* Tag word register */ 7411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __uint32_t __others[4]; /* EIP, Pointer Selector, etc */ 7511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert } __x87; 7611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __uint32_t __mxcsr; /* Control, status register */ 7711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} fenv_t; 7811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 7911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* 8011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * fexcept_t represents the floating-point status flags collectively, including 8111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * any status the implementation associates with the flags. 8211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 8311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * A floating-point status flag is a system variable whose value is set (but 8411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * never cleared) when a floating-point exception is raised, which occurs as a 8511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * side effect of exceptional floating-point arithmetic to provide auxiliary 8611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * information. 8711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 8811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * A floating-point control mode is a system variable whose value may be set by 8911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * the user to affect the subsequent behavior of floating-point arithmetic. 9011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 9111cd02dfb91661c65134cac258cf5924270e9d2Dan Alberttypedef __uint32_t fexcept_t; 9211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 9311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert__END_DECLS 9411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 9511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif /* !_AMD64_FENV_H_ */ 96