111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/*- 211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * All rights reserved. 411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Redistribution and use in source and binary forms, with or without 611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * modification, are permitted provided that the following conditions 711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * are met: 811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 1. Redistributions of source code must retain the above copyright 911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * notice, this list of conditions and the following disclaimer. 1011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 2. Redistributions in binary form must reproduce the above copyright 1111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * notice, this list of conditions and the following disclaimer in the 1211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * documentation and/or other materials provided with the distribution. 1311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 1411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * SUCH DAMAGE. 2511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 2611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ 2711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 2811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 2911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* 3011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert Rewritten for Android. 3111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert*/ 3211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 3311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* MIPS FPU floating point control register bits. 3411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 3511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 31-25 -> floating point conditions code bits set by FP compare 3611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * instructions 3711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 24 -> flush denormalized results to zero instead of 3811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * causing unimplemented operation exception. 3911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 23 -> Condition bit 4011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 22 -> In conjunction with FS detects denormalized 4111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * operands and replaces them internally with 0. 4211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 21 -> In conjunction with FS forces denormalized operands 4311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * to the closest normalized value. 4411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 20-18 -> reserved (read as 0, write with 0) 4511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 17 -> cause bit for unimplemented operation 4611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 16 -> cause bit for invalid exception 4711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 15 -> cause bit for division by zero exception 4811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 14 -> cause bit for overflow exception 4911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 13 -> cause bit for underflow exception 5011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 12 -> cause bit for inexact exception 5111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 11 -> enable exception for invalid exception 5211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 10 -> enable exception for division by zero exception 5311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 9 -> enable exception for overflow exception 5411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 8 -> enable exception for underflow exception 5511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 7 -> enable exception for inexact exception 5611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 6 -> flag invalid exception 5711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 5 -> flag division by zero exception 5811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 4 -> flag overflow exception 5911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 3 -> flag underflow exception 6011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 2 -> flag inexact exception 6111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 1-0 -> rounding control 6211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 6311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 6411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * Rounding Control: 6511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 00 - rounding to nearest (RN) 6611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 01 - rounding toward zero (RZ) 6711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 10 - rounding (up) toward plus infinity (RP) 6811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert * 11 - rounding (down)toward minus infinity (RM) 6911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert */ 7011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 7111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef _FENV_H_ 7211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _FENV_H_ 7311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 7411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#include <sys/types.h> 7511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 7611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert__BEGIN_DECLS 7711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 7811cd02dfb91661c65134cac258cf5924270e9d2Dan Alberttypedef __uint32_t fenv_t; 7911cd02dfb91661c65134cac258cf5924270e9d2Dan Alberttypedef __uint32_t fexcept_t; 8011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 8111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* Exception flags */ 8211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_INVALID 0x40 8311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_DIVBYZERO 0x20 8411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_OVERFLOW 0x10 8511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_UNDERFLOW 0x08 8611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_INEXACT 0x04 8711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 8811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 8911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _FCSR_CAUSE_SHIFT 10 9011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _ENABLE_SHIFT 5 9111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _FCSR_ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT) 9211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 9311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* Rounding modes */ 9411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_TONEAREST 0x0000 9511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_TOWARDZERO 0x0001 9611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_UPWARD 0x0002 9711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_DOWNWARD 0x0003 9811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _FCSR_RMODE_SHIFT 0 9911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _FCSR_RMASK 0x3 10011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* Default floating-point environment */ 10111cd02dfb91661c65134cac258cf5924270e9d2Dan Albertextern const fenv_t __fe_dfl_env; 10211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define FE_DFL_ENV (&__fe_dfl_env) 10311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 10411cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fegetenv(fenv_t* __envp) { 10511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t _fcsr = 0; 10611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifdef __mips_hard_float 10711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr)); 10811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 10911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *__envp = _fcsr; 11011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 11111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 11211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 11311cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fesetenv(const fenv_t* __envp) { 11411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t _fcsr = *__envp; 11511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifdef __mips_hard_float 11611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr)); 11711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 11811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 11911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 12011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 12111cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int feclearexcept(int __excepts) { 12211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fexcept_t __fcsr; 12311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__fcsr); 12411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __excepts &= FE_ALL_EXCEPT; 12511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __fcsr &= ~(__excepts | (__excepts << _FCSR_CAUSE_SHIFT)); 12611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&__fcsr); 12711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 12811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 12911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 13011cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) { 13111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fexcept_t __fcsr; 13211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__fcsr); 13311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *__flagp = __fcsr & __excepts & FE_ALL_EXCEPT; 13411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 13511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 13611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 13711cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) { 13811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fexcept_t __fcsr; 13911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__fcsr); 14011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert /* Ensure that flags are all legal */ 14111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __excepts &= FE_ALL_EXCEPT; 14211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __fcsr &= ~__excepts; 14311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __fcsr |= *__flagp & __excepts; 14411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&__fcsr); 14511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 14611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 14711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 14811cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int feraiseexcept(int __excepts) { 14911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fexcept_t __fcsr; 15011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__fcsr); 15111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert /* Ensure that flags are all legal */ 15211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __excepts &= FE_ALL_EXCEPT; 15311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert /* Cause bit needs to be set as well for generating the exception*/ 15411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __fcsr |= __excepts | (__excepts << _FCSR_CAUSE_SHIFT); 15511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&__fcsr); 15611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 15711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 15811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 15911cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fetestexcept(int __excepts) { 16011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fexcept_t __FCSR; 16111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__FCSR); 16211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return (__FCSR & __excepts & FE_ALL_EXCEPT); 16311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 16411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 16511cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fegetround(void) { 16611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t _fcsr; 16711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&_fcsr); 16811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return (_fcsr & _FCSR_RMASK); 16911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 17011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 17111cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fesetround(int __round) { 17211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t _fcsr; 17311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&_fcsr); 17411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert _fcsr &= ~_FCSR_RMASK; 17511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert _fcsr |= (__round & _FCSR_RMASK ) ; 17611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&_fcsr); 17711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 17811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 17911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 18011cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int feholdexcept(fenv_t* __envp) { 18111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t __env; 18211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__env); 18311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *__envp = __env; 18411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __env &= ~(FE_ALL_EXCEPT | _FCSR_ENABLE_MASK); 18511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&__env); 18611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 18711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 18811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 18911cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int feupdateenv(const fenv_t* __envp) { 19011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fexcept_t __fcsr; 19111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__fcsr); 19211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(__envp); 19311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert feraiseexcept(__fcsr & FE_ALL_EXCEPT); 19411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return 0; 19511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 19611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 19711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#if __BSD_VISIBLE 19811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 19911cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int feenableexcept(int __mask) { 20011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t __old_fcsr, __new_fcsr; 20111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__old_fcsr); 20211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __new_fcsr = __old_fcsr | (__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT; 20311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&__new_fcsr); 20411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT); 20511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 20611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 20711cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fedisableexcept(int __mask) { 20811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t __old_fcsr, __new_fcsr; 20911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__old_fcsr); 21011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert __new_fcsr = __old_fcsr & ~((__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT); 21111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fesetenv(&__new_fcsr); 21211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT); 21311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 21411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 21511cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstatic __inline int fegetexcept(void) { 21611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fenv_t __fcsr; 21711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert fegetenv(&__fcsr); 21811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert return ((__fcsr & _FCSR_ENABLE_MASK) >> _ENABLE_SHIFT); 21911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} 22011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 22111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif /* __BSD_VISIBLE */ 22211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 22311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert__END_DECLS 22411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 22511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif /* !_FENV_H_ */ 226