111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/**************************************************************************** 211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert **************************************************************************** 311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** This header was automatically generated from a Linux kernel header 511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** of the same name, to make information necessary for userspace to 611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** call into the kernel available to libc. It contains only constants, 711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** structures, and macros generated from the original header, and thus, 811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** contains no copyrightable information. 911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** To edit the content of this header, modify the corresponding 1111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** source file (e.g. under external/kernel-headers/original/) then 1211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** run bionic/libc/kernel/tools/update_all.py 1311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** Any manual change here will be lost the next time this script will 1511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** be run. You've been warned! 1611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert **************************************************************************** 1811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert ****************************************************************************/ 1911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef LINUX_PCI_REGS_H 2011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define LINUX_PCI_REGS_H 2111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STD_HEADER_SIZEOF 64 2211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VENDOR_ID 0x00 2311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_DEVICE_ID 0x02 2511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND 0x04 2611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_IO 0x1 2711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_MEMORY 0x2 2811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_MASTER 0x4 3011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_SPECIAL 0x8 3111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_INVALIDATE 0x10 3211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_VGA_PALETTE 0x20 3311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_PARITY 0x40 3511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_WAIT 0x80 3611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_SERR 0x100 3711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_FAST_BACK 0x200 3811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_INTX_DISABLE 0x400 4011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS 0x06 4111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_INTERRUPT 0x08 4211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_CAP_LIST 0x10 4311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_66MHZ 0x20 4511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_UDF 0x40 4611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_FAST_BACK 0x80 4711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_PARITY 0x100 4811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_MASK 0x600 5011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_FAST 0x000 5111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_MEDIUM 0x200 5211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_SLOW 0x400 5311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 5411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_SIG_TARGET_ABORT 0x800 5511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_REC_TARGET_ABORT 0x1000 5611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_REC_MASTER_ABORT 0x2000 5711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 5811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 5911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DETECTED_PARITY 0x8000 6011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CLASS_REVISION 0x08 6111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_REVISION_ID 0x08 6211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CLASS_PROG 0x09 6311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 6411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CLASS_DEVICE 0x0a 6511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CACHE_LINE_SIZE 0x0c 6611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LATENCY_TIMER 0x0d 6711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE 0x0e 6811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 6911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE_NORMAL 0 7011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE_BRIDGE 1 7111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE_CARDBUS 2 7211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST 0x0f 7311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 7411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST_CODE_MASK 0x0f 7511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST_START 0x40 7611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST_CAPABLE 0x80 7711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_0 0x10 7811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 7911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_1 0x14 8011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_2 0x18 8111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_3 0x1c 8211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_4 0x20 8311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 8411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_5 0x24 8511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_SPACE 0x01 8611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_SPACE_IO 0x01 8711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 8811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 8911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 9011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 9111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 9211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 9311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 9411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 9511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 9611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 9711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CARDBUS_CIS 0x28 9811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 9911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 10011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SUBSYSTEM_ID 0x2e 10111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS 0x30 10211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS_ENABLE 0x01 10311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 10411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 10511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAPABILITY_LIST 0x34 10611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_INTERRUPT_LINE 0x3c 10711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_INTERRUPT_PIN 0x3d 10811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 10911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MIN_GNT 0x3e 11011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MAX_LAT 0x3f 11111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRIMARY_BUS 0x18 11211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SECONDARY_BUS 0x19 11311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 11411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SUBORDINATE_BUS 0x1a 11511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SEC_LATENCY_TIMER 0x1b 11611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_BASE 0x1c 11711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_LIMIT 0x1d 11811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 11911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 12011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_TYPE_16 0x00 12111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_TYPE_32 0x01 12211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_MASK (~0x0fUL) 12311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 12411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_1K_RANGE_MASK (~0x03UL) 12511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SEC_STATUS 0x1e 12611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_BASE 0x20 12711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_LIMIT 0x22 12811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 12911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 13011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 13111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_MEMORY_BASE 0x24 13211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_MEMORY_LIMIT 0x26 13311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 13411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 13511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_TYPE_32 0x00 13611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_TYPE_64 0x01 13711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_MASK (~0x0fUL) 13811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 13911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_BASE_UPPER32 0x28 14011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_LIMIT_UPPER32 0x2c 14111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_BASE_UPPER16 0x30 14211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_LIMIT_UPPER16 0x32 14311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 14411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS1 0x38 14511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CONTROL 0x3e 14611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_PARITY 0x01 14711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_SERR 0x02 14811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 14911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_ISA 0x04 15011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_VGA 0x08 15111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 15211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_BUS_RESET 0x40 15311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 15411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_FAST_BACK 0x80 15511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_CAPABILITY_LIST 0x14 15611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SEC_STATUS 0x16 15711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_PRIMARY_BUS 0x18 15811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 15911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_CARD_BUS 0x19 16011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SUBORDINATE_BUS 0x1a 16111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_LATENCY_TIMER 0x1b 16211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_BASE_0 0x1c 16311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 16411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_LIMIT_0 0x20 16511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_BASE_1 0x24 16611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_LIMIT_1 0x28 16711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_0 0x2c 16811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 16911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_0_HI 0x2e 17011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_0 0x30 17111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_0_HI 0x32 17211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_1 0x34 17311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 17411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_1_HI 0x36 17511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_1 0x38 17611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_1_HI 0x3a 17711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_RANGE_MASK (~0x03UL) 17811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 17911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CONTROL 0x3e 18011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_PARITY 0x01 18111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_SERR 0x02 18211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_ISA 0x04 18311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 18411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_VGA 0x08 18511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 18611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 18711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 18811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 18911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 19011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 19111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 19211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 19311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 19411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SUBSYSTEM_ID 0x42 19511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_LEGACY_MODE_BASE 0x44 19611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_LIST_ID 0 19711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_PM 0x01 19811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 19911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_AGP 0x02 20011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_VPD 0x03 20111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SLOTID 0x04 20211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_MSI 0x05 20311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 20411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_CHSWP 0x06 20511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_PCIX 0x07 20611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_HT 0x08 20711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_VNDR 0x09 20811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 20911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_DBG 0x0A 21011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_CCRC 0x0B 21111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SHPC 0x0C 21211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SSVID 0x0D 21311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 21411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_AGP3 0x0E 21511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SECDEV 0x0F 21611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_EXP 0x10 21711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_MSIX 0x11 21811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 21911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SATA 0x12 22011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_AF 0x13 22111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_MAX PCI_CAP_ID_AF 22211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_LIST_NEXT 1 22311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_FLAGS 2 22511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_SIZEOF 4 22611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_PMC 2 22711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_VER_MASK 0x0007 22811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_CLOCK 0x0008 23011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_RESERVED 0x0010 23111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_DSI 0x0020 23211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_AUX_POWER 0x01C0 23311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 23411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_D1 0x0200 23511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_D2 0x0400 23611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME 0x0800 23711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_MASK 0xF800 23811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 23911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D0 0x0800 24011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D1 0x1000 24111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D2 0x2000 24211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D3 0x4000 24311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D3cold 0x8000 24511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_SHIFT 11 24611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL 4 24711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_STATE_MASK 0x0003 24811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 25011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_PME_ENABLE 0x0100 25111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 25211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 25311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 25411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_PME_STATUS 0x8000 25511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_PPB_EXTENSIONS 6 25611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_PPB_B2_B3 0x40 25711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_BPCC_ENABLE 0x80 25811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 25911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_DATA_REGISTER 7 26011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_SIZEOF 8 26111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_VERSION 2 26211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_RFU 3 26311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 26411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS 4 26511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RQ_MASK 0xff000000 26611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_SBA 0x0200 26711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_64BIT 0x0020 26811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 26911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_FW 0x0010 27011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RATE4 0x0004 27111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RATE2 0x0002 27211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RATE1 0x0001 27311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 27411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND 8 27511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 27611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_SBA 0x0200 27711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_AGP 0x0100 27811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 27911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_64BIT 0x0020 28011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_FW 0x0010 28111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RATE4 0x0004 28211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RATE2 0x0002 28311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 28411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RATE1 0x0001 28511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_SIZEOF 12 28611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_ADDR 2 28711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_ADDR_MASK 0x7fff 28811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 28911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_ADDR_F 0x8000 29011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_DATA 4 29111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_VPD_SIZEOF 8 29211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_ESR 2 29311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_ESR_NSLOTS 0x1f 29511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_ESR_FIC 0x20 29611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_CHASSIS_NR 3 29711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS 2 29811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_ENABLE 0x0001 30011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_QMASK 0x000e 30111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_QSIZE 0x0070 30211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_64BIT 0x0080 30311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 30411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_MASKBIT 0x0100 30511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_RFU 3 30611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_ADDRESS_LO 4 30711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_ADDRESS_HI 8 30811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 30911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_DATA_32 8 31011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_MASK_32 12 31111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_PENDING_32 16 31211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_DATA_64 12 31311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 31411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_MASK_64 16 31511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_PENDING_64 20 31611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_FLAGS 2 31711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_FLAGS_QSIZE 0x07FF 31811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 31911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_FLAGS_MASKALL 0x4000 32011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_FLAGS_ENABLE 0x8000 32111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_TABLE 4 32211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_TABLE_BIR 0x00000007 32311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 32411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 32511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_PBA 8 32611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_PBA_BIR 0x00000007 32711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_PBA_OFFSET 0xfffffff8 32811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 32911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_MSIX_SIZEOF 12 33011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_ENTRY_SIZE 16 33111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_ENTRY_LOWER_ADDR 0 33211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_ENTRY_UPPER_ADDR 4 33311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 33411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_ENTRY_DATA 8 33511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 33611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 33711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_CSR 2 33811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 33911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_DHA 0x01 34011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_EIM 0x02 34111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_PIE 0x04 34211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_LOO 0x08 34311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_PI 0x30 34511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_EXT 0x40 34611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_INS 0x80 34711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_LENGTH 2 34811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_CAP 3 35011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_CAP_TP 0x01 35111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_CAP_FLR 0x02 35211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_CTRL 4 35311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 35411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_CTRL_FLR 0x01 35511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_STATUS 5 35611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AF_STATUS_TP 0x01 35711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_AF_SIZEOF 6 35811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 35911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD 2 36011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_DPERR_E 0x0001 36111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_ERO 0x0002 36211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_READ_512 0x0000 36311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_READ_1K 0x0004 36511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_READ_2K 0x0008 36611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_READ_4K 0x000c 36711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_MAX_READ 0x000c 36811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_1 0x0000 37011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_2 0x0010 37111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_3 0x0020 37211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_4 0x0030 37311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_8 0x0040 37511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_12 0x0050 37611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_16 0x0060 37711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_SPLIT_32 0x0070 37811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_MAX_SPLIT 0x0070 38011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 38111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS 4 38211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_DEVFN 0x000000ff 38311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_BUS 0x0000ff00 38511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_64BIT 0x00010000 38611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_133MHZ 0x00020000 38711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_SPL_DISC 0x00040000 38811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_UNX_SPL 0x00080000 39011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_COMPLEX 0x00100000 39111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_MAX_READ 0x00600000 39211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_MAX_SPLIT 0x03800000 39311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_MAX_CUM 0x1c000000 39511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_SPL_ERR 0x20000000 39611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_266MHZ 0x40000000 39711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_533MHZ 0x80000000 39811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_ECC_CSR 8 40011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_PCIX_SIZEOF_V0 8 40111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_PCIX_SIZEOF_V1 24 40211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 40311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 40411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_BRIDGE_SSTATUS 2 40511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_64BIT 0x0001 40611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_133MHZ 0x0002 40711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_FREQ 0x03c0 40811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 40911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_VERS 0x3000 41011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_V1 0x1000 41111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_V2 0x2000 41211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_266MHZ 0x4000 41311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 41411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_SSTATUS_533MHZ 0x8000 41511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_BRIDGE_STATUS 4 41611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SSVID_VENDOR_ID 4 41711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SSVID_DEVICE_ID 6 41811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 41911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS 2 42011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_VERS 0x000f 42111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_TYPE 0x00f0 42211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_ENDPOINT 0x0 42311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 42411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_LEG_END 0x1 42511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_ROOT_PORT 0x4 42611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_UPSTREAM 0x5 42711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_DOWNSTREAM 0x6 42811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 42911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 43011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 43111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_RC_END 0x9 43211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_RC_EC 0xa 43311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 43411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_SLOT 0x0100 43511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_IRQ 0x3e00 43611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP 4 43711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 43811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 43911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 44011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 44111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_L0S 0x000001c0 44211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_L1 0x00000e00 44311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 44511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 44611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 44711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_RBER 0x00008000 44811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 45011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 45111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_FLR 0x10000000 45211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL 8 45311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 45411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_CERE 0x0001 45511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_NFERE 0x0002 45611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_FERE 0x0004 45711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_URRE 0x0008 45811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 45911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 46011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 46111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 46211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_PHANTOM 0x0200 46311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 46411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_AUX_PME 0x0400 46511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 46611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_READRQ 0x7000 46711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 46811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 46911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA 10 47011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_CED 0x0001 47111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_NFED 0x0002 47211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_FED 0x0004 47311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 47411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_URD 0x0008 47511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_AUXPD 0x0010 47611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_TRPND 0x0020 47711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP 12 47811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 47911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_SLS 0x0000000f 48011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 48111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 48211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_MLW 0x000003f0 48311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 48411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 48511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_L0SEL 0x00007000 48611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_L1EL 0x00038000 48711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_CLKPM 0x00040000 48811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 48911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_SDERC 0x00080000 49011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 49111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_LBNC 0x00200000 49211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP_PN 0xff000000 49311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL 16 49511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_ASPMC 0x0003 49611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 49711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 49811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_RCB 0x0008 50011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_LD 0x0010 50111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_RL 0x0020 50211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_CCC 0x0040 50311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 50411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_ES 0x0080 50511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 50611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_HAWD 0x0200 50711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_LBMIE 0x0400 50811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 50911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL_LABIE 0x0800 51011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA 18 51111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_CLS 0x000f 51211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 51311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 51511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 51611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_NLW 0x03f0 51711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_NLW_X1 0x0010 51811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_NLW_X2 0x0020 52011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_NLW_X4 0x0040 52111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_NLW_X8 0x0080 52211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_NLW_SHIFT 4 52311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 52411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_LT 0x0800 52511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_SLC 0x1000 52611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_DLLLA 0x2000 52711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_LBMS 0x4000 52811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 52911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA_LABS 0x8000 53011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 53111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP 20 53211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_ABP 0x00000001 53311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 53411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_PCP 0x00000002 53511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_MRLSP 0x00000004 53611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_AIP 0x00000008 53711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_PIP 0x00000010 53811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 53911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_HPS 0x00000020 54011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_HPC 0x00000040 54111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_SPLV 0x00007f80 54211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_SPLS 0x00018000 54311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_EIP 0x00020000 54511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_NCCS 0x00040000 54611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP_PSN 0xfff80000 54711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL 24 54811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_ABPE 0x0001 55011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PFDE 0x0002 55111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_MRLSCE 0x0004 55211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PDCE 0x0008 55311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 55411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_CCIE 0x0010 55511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_HPIE 0x0020 55611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_AIC 0x00c0 55711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 55811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 55911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 56011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 56111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PIC 0x0300 56211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 56311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 56511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 56611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PCC 0x0400 56711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PWR_ON 0x0000 56811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 57011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_EIC 0x0800 57111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL_DLLSCE 0x1000 57211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA 26 57311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 57411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_ABP 0x0001 57511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_PFD 0x0002 57611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_MRLSC 0x0004 57711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_PDC 0x0008 57811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 57911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_CC 0x0010 58011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_MRLSS 0x0020 58111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_PDS 0x0040 58211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_EIS 0x0080 58311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 58411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA_DLLSC 0x0100 58511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL 28 58611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_SECEE 0x0001 58711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_SENFEE 0x0002 58811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 58911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_SEFEE 0x0004 59011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_PMEIE 0x0008 59111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_CRSSVE 0x0010 59211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCAP 30 59311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTSTA 32 59511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTSTA_PME 0x00010000 59611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTSTA_PENDING 0x00020000 59711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP2 36 59811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP2_ARI 0x00000020 60011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP2_LTR 0x00000800 60111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 60211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 60311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 60511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2 40 60611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 60711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_ARI 0x0020 60811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 61011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 61111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 61211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 61311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 61411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 61511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 61611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA2 42 61711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 61811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 61911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP2 44 62011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 62111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 62211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 62311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 62411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 62511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL2 48 62611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA2 50 62711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP2 52 62811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 62911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL2 56 63011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA2 58 63111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 63211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 63311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 63411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 63511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_ERR 0x01 63611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_VC 0x02 63711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_DSN 0x03 63811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 63911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_PWR 0x04 64011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_RCLD 0x05 64111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_RCILC 0x06 64211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_RCEC 0x07 64311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_MFVC 0x08 64511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_VC9 0x09 64611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_RCRB 0x0A 64711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_VNDR 0x0B 64811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_CAC 0x0C 65011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_ACS 0x0D 65111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_ARI 0x0E 65211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_ATS 0x0F 65311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_SRIOV 0x10 65511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_MRIOV 0x11 65611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_MCAST 0x12 65711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_PRI 0x13 65811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_AMD_XXX 0x14 66011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_REBAR 0x15 66111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_DPA 0x16 66211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_TPH 0x17 66311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 66411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_LTR 0x18 66511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_SECPCI 0x19 66611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_PMUX 0x1A 66711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_PASID 0x1B 66811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 66911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID 67011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_DSN_SIZEOF 12 67111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 67211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNCOR_STATUS 4 67311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_TRAIN 0x00000001 67511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_DLP 0x00000010 67611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_SURPDN 0x00000020 67711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_POISON_TLP 0x00001000 67811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_FCP 0x00002000 68011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_COMP_TIME 0x00004000 68111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_COMP_ABORT 0x00008000 68211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_UNX_COMP 0x00010000 68311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 68411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_RX_OVER 0x00020000 68511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_MALF_TLP 0x00040000 68611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_ECRC 0x00080000 68711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_UNSUP 0x00100000 68811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 68911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_ACSV 0x00200000 69011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_INTN 0x00400000 69111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_MCBTLP 0x00800000 69211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_ATOMEG 0x01000000 69311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_TLPPRE 0x02000000 69511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNCOR_MASK 8 69611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNCOR_SEVER 12 69711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_STATUS 16 69811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_RCVR 0x00000001 70011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_BAD_TLP 0x00000040 70111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_BAD_DLLP 0x00000080 70211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_REP_ROLL 0x00000100 70311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 70411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_REP_TIMER 0x00001000 70511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_ADV_NFAT 0x00002000 70611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_INTERNAL 0x00004000 70711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_LOG_OVER 0x00008000 70811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 70911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_MASK 20 71011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP 24 71111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_FEP(x) ((x) & 31) 71211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_GENC 0x00000020 71311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 71411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_GENE 0x00000040 71511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 71611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 71711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_HEADER_LOG 28 71811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 71911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_COMMAND 44 72011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 72111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 72211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 72311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 72411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_STATUS 48 72511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_COR_RCV 0x00000001 72611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 72711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 72811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 72911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 73011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 73111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 73211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 73311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 73411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_ERR_SRC 52 73511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_CAP1 4 73611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP1_EVCC 0x00000007 73711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP1_LPEVCC 0x00000070 73811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 73911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 74011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_CAP2 8 74111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP2_32_PHASE 0x00000002 74211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP2_64_PHASE 0x00000004 74311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP2_128_PHASE 0x00000008 74511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_CAP2_ARB_OFF 0xff000000 74611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_CTRL 12 74711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 74811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_STATUS 14 75011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_STATUS_TABLE 0x00000001 75111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP 16 75211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP_32_PHASE 0x00000002 75311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 75411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP_64_PHASE 0x00000004 75511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP_128_PHASE 0x00000008 75611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 75711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP_256_PHASE 0x00000020 75811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 75911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 76011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CTRL 20 76111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 76211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 76311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 76411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CTRL_ID 0x07000000 76511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CTRL_ENABLE 0x80000000 76611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_STATUS 26 76711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_STATUS_TABLE 0x00000001 76811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 76911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_STATUS_NEGO 0x00000002 77011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_VC_BASE_SIZEOF 0x10 77111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 77211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DSR 4 77311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 77411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA 8 77511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 77611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 77711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 77811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 77911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 78011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 78111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 78211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_CAP 12 78311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 78511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_PWR_SIZEOF 16 78611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VNDR_HEADER 4 78711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 78811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 79011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 79111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_3BIT_CAP_MASK 0xE0 79211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_SLAVE 0x00 79311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_HOST 0x20 79511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_5BIT_CAP_MASK 0xF8 79611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_IRQ 0x80 79711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_REMAPPING_40 0xA0 79811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_REMAPPING_64 0xA2 80011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_UNITID_CLUMP 0x90 80111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_EXTCONF 0x98 80211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_MSI_MAPPING 0xA8 80311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_FLAGS 0x02 80511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_FLAGS_ENABLE 0x1 80611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_FLAGS_FIXED 0x2 80711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 80811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_ADDR_LO 0x04 81011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_ADDR_LO_MASK 0xFFF00000 81111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_MSI_ADDR_HI 0x08 81211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 81311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_VCSET 0xB8 81511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_ERROR_RETRY 0xC0 81611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_GEN3 0xD0 81711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAPTYPE_PM 0xE0 81811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAP_SIZEOF_LONG 28 82011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define HT_CAP_SIZEOF_SHORT 24 82111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CAP 0x04 82211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CAP_MFVC 0x0001 82311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CAP_ACS 0x0002 82511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 82611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CTRL 0x06 82711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CTRL_MFVC 0x0001 82811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CTRL_ACS 0x0002 83011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 83111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ARI_SIZEOF 8 83211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_CAP 0x04 83311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 83511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_MAX_QDEP 32 83611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_CTRL 0x06 83711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_CTRL_ENABLE 0x8000 83811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 84011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ATS_MIN_STU 12 84111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ATS_SIZEOF 8 84211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_CTRL 0x04 84311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_CTRL_ENABLE 0x01 84511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_CTRL_RESET 0x02 84611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_STATUS 0x06 84711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_STATUS_RF 0x001 84811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_STATUS_UPRGI 0x002 85011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_STATUS_STOPPED 0x100 85111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_MAX_REQ 0x08 85211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRI_ALLOC_REQ 0x0c 85311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_PRI_SIZEOF 16 85511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CAP 0x04 85611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CAP_EXEC 0x02 85711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CAP_PRIV 0x04 85811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CTRL 0x06 86011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CTRL_ENABLE 0x01 86111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CTRL_EXEC 0x02 86211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PASID_CTRL_PRIV 0x04 86311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_PASID_SIZEOF 8 86511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CAP 0x04 86611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CAP_VFM 0x01 86711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 86811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CTRL 0x08 87011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CTRL_VFE 0x01 87111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CTRL_VFM 0x02 87211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CTRL_INTR 0x04 87311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CTRL_MSE 0x08 87511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_CTRL_ARI 0x10 87611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_STATUS 0x0a 87711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_STATUS_VFM 0x01 87811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_INITIAL_VF 0x0c 88011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_TOTAL_VF 0x0e 88111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_NUM_VF 0x10 88211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_FUNC_LINK 0x12 88311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VF_OFFSET 0x14 88511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VF_STRIDE 0x16 88611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VF_DID 0x1a 88711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_SUP_PGSIZE 0x1c 88811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_SYS_PGSIZE 0x20 89011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_BAR 0x24 89111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_NUM_BARS 6 89211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM 0x3c 89311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 89511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 89611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM_UA 0x0 89711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM_MI 0x1 89811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM_MO 0x2 90011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SRIOV_VFM_AV 0x3 90111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_SRIOV_SIZEOF 64 90211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LTR_MAX_SNOOP_LAT 0x4 90311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 90511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LTR_VALUE_MASK 0x000003ff 90611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LTR_SCALE_MASK 0x00001c00 90711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LTR_SCALE_SHIFT 10 90811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_LTR_SIZEOF 8 91011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_CAP 0x04 91111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_SV 0x01 91211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_TB 0x02 91311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 91411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_RR 0x04 91511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_CR 0x08 91611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_UF 0x10 91711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_EC 0x20 91811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 91911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_DT 0x40 92011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_EGRESS_BITS 0x05 92111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_CTRL 0x06 92211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ACS_EGRESS_CTL_V 0x08 92311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 92411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VSEC_HDR 4 92511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VSEC_HDR_LEN_SHIFT 20 92611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SATA_REGS 4 92711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SATA_REGS_MASK 0xF 92811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 92911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SATA_REGS_INLINE 0xF 93011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SATA_SIZEOF_SHORT 8 93111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SATA_SIZEOF_LONG 16 93211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_REBAR_CTRL 8 93311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 93411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 93511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_REBAR_CTRL_NBAR_SHIFT 5 93611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_DPA_CAP 4 93711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 93811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 93911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_DPA_BASE_SIZEOF 16 94011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_CAP 4 94111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_CAP_LOC_MASK 0x600 94211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_LOC_NONE 0x000 94311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_LOC_CAP 0x200 94511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_LOC_MSIX 0x400 94611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_CAP_ST_MASK 0x07FF0000 94711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_CAP_ST_SHIFT 16 94811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_TPH_BASE_SIZEOF 12 95011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 951