111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/**************************************************************************** 211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert **************************************************************************** 311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** This header was automatically generated from a Linux kernel header 511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** of the same name, to make information necessary for userspace to 611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** call into the kernel available to libc. It contains only constants, 711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** structures, and macros generated from the original header, and thus, 811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** contains no copyrightable information. 911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** To edit the content of this header, modify the corresponding 1111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** source file (e.g. under external/kernel-headers/original/) then 1211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** run bionic/libc/kernel/tools/update_all.py 1311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** Any manual change here will be lost the next time this script will 1511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** be run. You've been warned! 1611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert **************************************************************************** 1811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert ****************************************************************************/ 1911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef _AU1000_H_ 2011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define _AU1000_H_ 2111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef _LANGUAGE_ASSEMBLY 2211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#include <linux/delay.h> 2311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#include <linux/types.h> 2511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#include <linux/io.h> 2611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#include <linux/irq.h> 2711cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstruct au1xxx_irqmap { 2811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 2911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert int im_irq; 3011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert int im_type; 3111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert int im_request; 3211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert}; 3311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 3511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STCFG0 0xB4001000 3611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STTIME0 0xB4001004 3711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STADDR0 0xB4001008 3811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 3911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STCFG1 0xB4001010 4011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STTIME1 0xB4001014 4111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STADDR1 0xB4001018 4211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STCFG2 0xB4001020 4311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STTIME2 0xB4001024 4511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STADDR2 0xB4001028 4611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STCFG3 0xB4001030 4711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STTIME3 0xB4001034 4811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 4911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MEM_STADDR3 0xB4001038 5011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG0RD 0xB0400040 5111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG0SET 0xB0400040 5211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG0CLR 0xB0400044 5311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 5411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG1RD 0xB0400048 5511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG1SET 0xB0400048 5611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG1CLR 0xB040004C 5711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG2RD 0xB0400050 5811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 5911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG2SET 0xB0400050 6011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_CFG2CLR 0xB0400054 6111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_REQ0INT 0xB0400054 6211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_SRCRD 0xB0400058 6311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 6411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_SRCSET 0xB0400058 6511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_SRCCLR 0xB040005C 6611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_REQ1INT 0xB040005C 6711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_ASSIGNRD 0xB0400060 6811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 6911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_ASSIGNSET 0xB0400060 7011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_ASSIGNCLR 0xB0400064 7111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_WAKERD 0xB0400068 7211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_WAKESET 0xB0400068 7311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 7411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_WAKECLR 0xB040006C 7511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_MASKRD 0xB0400070 7611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_MASKSET 0xB0400070 7711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_MASKCLR 0xB0400074 7811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 7911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_RISINGRD 0xB0400078 8011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_RISINGCLR 0xB0400078 8111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_FALLINGRD 0xB040007C 8211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_FALLINGCLR 0xB040007C 8311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 8411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC0_TESTBIT 0xB0400080 8511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG0RD 0xB1800040 8611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG0SET 0xB1800040 8711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG0CLR 0xB1800044 8811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 8911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG1RD 0xB1800048 9011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG1SET 0xB1800048 9111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG1CLR 0xB180004C 9211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG2RD 0xB1800050 9311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 9411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG2SET 0xB1800050 9511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_CFG2CLR 0xB1800054 9611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_REQ0INT 0xB1800054 9711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_SRCRD 0xB1800058 9811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 9911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_SRCSET 0xB1800058 10011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_SRCCLR 0xB180005C 10111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_REQ1INT 0xB180005C 10211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_ASSIGNRD 0xB1800060 10311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 10411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_ASSIGNSET 0xB1800060 10511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_ASSIGNCLR 0xB1800064 10611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_WAKERD 0xB1800068 10711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_WAKESET 0xB1800068 10811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 10911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_WAKECLR 0xB180006C 11011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_MASKRD 0xB1800070 11111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_MASKSET 0xB1800070 11211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_MASKCLR 0xB1800074 11311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 11411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_RISINGRD 0xB1800078 11511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_RISINGCLR 0xB1800078 11611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_FALLINGRD 0xB180007C 11711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_FALLINGCLR 0xB180007C 11811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 11911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IC1_TESTBIT 0xB1800080 12011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_DISABLED 0x0 12111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_RISE_EDGE 0x1 12211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_FALL_EDGE 0x2 12311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 12411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_RISE_AND_FALL_EDGE 0x3 12511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_HIGH_LEVEL 0x5 12611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_LOW_LEVEL 0x6 12711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 12811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 12911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 13011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 13111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) 13211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 13311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 13411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 13511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define INTX 0xFF 13611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_BASE 0xB1900000 13711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 13811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 13911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_E1S (1 << 23) 14011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_T1S (1 << 20) 14111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_M21 (1 << 19) 14211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_M11 (1 << 18) 14311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 14411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_M01 (1 << 17) 14511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_C1S (1 << 16) 14611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_BP (1 << 14) 14711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_EN1 (1 << 13) 14811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 14911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_BT1 (1 << 12) 15011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_EN0 (1 << 11) 15111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_BT0 (1 << 10) 15211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_E0 (1 << 8) 15311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 15411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_E0S (1 << 7) 15511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_32S (1 << 5) 15611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_T0S (1 << 4) 15711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_M20 (1 << 3) 15811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 15911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_M10 (1 << 2) 16011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_M00 (1 << 1) 16111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CNTRL_C0S (1 << 0) 16211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TOYTRIM (SYS_BASE + 0) 16311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 16411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TOYWRITE (SYS_BASE + 4) 16511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TOYMATCH0 (SYS_BASE + 8) 16611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 16711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 16811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 16911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TOYREAD (SYS_BASE + 0x40) 17011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_RTCTRIM (SYS_BASE + 0x44) 17111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_RTCWRITE (SYS_BASE + 0x48) 17211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 17311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 17411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 17511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 17611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_RTCREAD (SYS_BASE + 0x58) 17711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_DATA 0xB1000000 17811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 17911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_DATA_MASK 0xffffff 18011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG 0xB1000004 18111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_XU (1 << 25) 18211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_XO (1 << 24) 18311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 18411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_RU (1 << 23) 18511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_RO (1 << 22) 18611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_TR (1 << 21) 18711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_TE (1 << 20) 18811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 18911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_TF (1 << 19) 19011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_RR (1 << 18) 19111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_RE (1 << 17) 19211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_RF (1 << 16) 19311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 19411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_PD (1 << 11) 19511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_LB (1 << 10) 19611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_IC (1 << 9) 19711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_FM_BIT 7 19811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 19911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 20011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 20111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 20211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 20311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 20411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_TN (1 << 6) 20511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_RN (1 << 5) 20611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_SZ_BIT 0 20711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 20811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 20911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONTROL 0xB1000008 21011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONTROL_D (1 << 1) 21111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define I2S_CONTROL_CE (1 << 0) 21211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef USB_OHCI_LEN 21311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 21411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USB_OHCI_LEN 0x00100000 21511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 21611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP0RD 0xB0200000 21711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP0WR 0xB0200004 21811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 21911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP2WR 0xB0200008 22011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP3WR 0xB020000C 22111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP4RD 0xB0200010 22211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP5RD 0xB0200014 22311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_INTEN 0xB0200018 22511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_INTSTAT 0xB020001C 22611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_INT_SOF (1 << 12) 22711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_INT_HF_BIT 6 22811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 23011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_INT_CMPLT_BIT 0 23111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 23211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_CONFIG 0xB0200020 23311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 23411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP0CS 0xB0200024 23511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP2CS 0xB0200028 23611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP3CS 0xB020002C 23711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP4CS 0xB0200030 23811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 23911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP5CS 0xB0200034 24011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_SU (1 << 14) 24111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_NAK (1 << 13) 24211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_ACK (1 << 12) 24311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_BUSY (1 << 11) 24511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_TSIZE_BIT 1 24611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 24711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CS_STALL (1 << 0) 24811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP0RDSTAT 0xB0200040 25011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP0WRSTAT 0xB0200044 25111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP2WRSTAT 0xB0200048 25211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP3WRSTAT 0xB020004C 25311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 25411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP4RDSTAT 0xB0200050 25511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_EP5RDSTAT 0xB0200054 25611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_FSTAT_FLUSH (1 << 6) 25711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_FSTAT_UF (1 << 5) 25811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 25911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_FSTAT_OF (1 << 4) 26011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_FSTAT_FCNT_BIT 0 26111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 26211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBD_ENABLE 0xB0200058 26311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 26411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_ENABLE (1 << 1) 26511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define USBDEV_CE (1 << 0) 26611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_CONTROL 0x0 26711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_ENABLE (1 << 2) 26811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 26911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_ENABLE (1 << 3) 27011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_DEF_CHECK (1 << 5) 27111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_SET_BL(X) (((X) & 0x3) << 6) 27211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_AUTO_PAD (1 << 8) 27311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 27411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_DISABLE_RETRY (1 << 10) 27511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_DISABLE_BCAST (1 << 11) 27611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_LATE_COL (1 << 12) 27711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_HASH_MODE (1 << 13) 27811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 27911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_HASH_ONLY (1 << 15) 28011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_PASS_ALL (1 << 16) 28111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_INVERSE_FILTER (1 << 17) 28211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_PROMISCUOUS (1 << 18) 28311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 28411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_PASS_ALL_MULTI (1 << 19) 28511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_FULL_DUPLEX (1 << 20) 28611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_NORMAL_MODE 0 28711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_INT_LOOPBACK (1 << 21) 28811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 28911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EXT_LOOPBACK (1 << 22) 29011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_DISABLE_RX_OWN (1 << 23) 29111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_BIG_ENDIAN (1 << 30) 29211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_ALL (1 << 31) 29311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_ADDRESS_HIGH 0x4 29511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_ADDRESS_LOW 0x8 29611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MCAST_HIGH 0xC 29711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MCAST_LOW 0x10 29811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MII_CNTRL 0x14 30011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MII_BUSY (1 << 0) 30111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MII_READ 0 30211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MII_WRITE (1 << 1) 30311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 30411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 30511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 30611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_MII_DATA 0x18 30711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_FLOW_CNTRL 0x1C 30811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 30911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_FLOW_CNTRL_BUSY (1 << 0) 31011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_FLOW_CNTRL_ENABLE (1 << 1) 31111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_PASS_CONTROL (1 << 2) 31211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 31311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 31411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_VLAN1_TAG 0x20 31511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_VLAN2_TAG 0x24 31611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EN_CLOCK_ENABLE (1 << 0) 31711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EN_RESET0 (1 << 1) 31811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 31911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EN_TOSS (0 << 2) 32011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EN_CACHEABLE (1 << 3) 32111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EN_RESET1 (1 << 4) 32211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_EN_RESET2 (1 << 5) 32311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 32411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_DMA_RESET (1 << 6) 32511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC0_TX_DMA_ADDR 0xB4004000 32611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC1_TX_DMA_ADDR 0xB4004200 32711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF0_STATUS 0x0 32811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 32911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_FRAME_ABORTED (1 << 0) 33011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_JAB_TIMEOUT (1 << 1) 33111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_NO_CARRIER (1 << 2) 33211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_LOSS_CARRIER (1 << 3) 33311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 33411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_EXC_DEF (1 << 4) 33511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_LATE_COLL_ABORT (1 << 5) 33611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_EXC_COLL (1 << 6) 33711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_UNDERRUN (1 << 7) 33811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 33911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_DEFERRED (1 << 8) 34011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_LATE_COLL (1 << 9) 34111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_COLL_CNT_MASK (0xF << 10) 34211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_PKT_RETRY (1 << 31) 34311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF0_ADDR 0x4 34511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_DMA_ENABLE (1 << 0) 34611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_T_DONE (1 << 1) 34711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 34811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF0_LEN 0x8 35011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF1_STATUS 0x10 35111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF1_ADDR 0x14 35211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF1_LEN 0x18 35311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 35411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF2_STATUS 0x20 35511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF2_ADDR 0x24 35611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF2_LEN 0x28 35711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF3_STATUS 0x30 35811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 35911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF3_ADDR 0x34 36011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_TX_BUFF3_LEN 0x38 36111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC0_RX_DMA_ADDR 0xB4004100 36211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC1_RX_DMA_ADDR 0xB4004300 36311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF0_STATUS 0x0 36511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_FRAME_LEN_MASK 0x3fff 36611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_WDOG_TIMER (1 << 14) 36711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_RUNT (1 << 15) 36811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_OVERLEN (1 << 16) 37011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_COLL (1 << 17) 37111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_ETHER (1 << 18) 37211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_MII_ERROR (1 << 19) 37311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_DRIBBLING (1 << 20) 37511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_CRC_ERROR (1 << 21) 37611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_VLAN1 (1 << 22) 37711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_VLAN2 (1 << 23) 37811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_LEN_ERROR (1 << 24) 38011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_CNTRL_FRAME (1 << 25) 38111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_U_CNTRL_FRAME (1 << 26) 38211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_MCAST_FRAME (1 << 27) 38311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_BCAST_FRAME (1 << 28) 38511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_FILTER_FAIL (1 << 29) 38611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_PACKET_FILTER (1 << 30) 38711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_MISSED_FRAME (1 << 31) 38811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 39011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF0_ADDR 0x4 39111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_DMA_ENABLE (1 << 0) 39211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_T_DONE (1 << 1) 39311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 39511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 39611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF1_STATUS 0x10 39711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF1_ADDR 0x14 39811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF2_STATUS 0x20 40011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF2_ADDR 0x24 40111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF3_STATUS 0x30 40211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define MAC_RX_BUFF3_ADDR 0x34 40311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 40411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_BASE UART0_ADDR 40511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_DEBUG_BASE UART3_ADDR 40611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_RX 0 40711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_TX 4 40811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 40911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IER 8 41011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR 0xC 41111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR 0x10 41211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR 0x14 41311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 41411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MCR 0x18 41511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR 0x1C 41611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR 0x20 41711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_CLK 0x28 41811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 41911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MOD_CNTRL 0x100 42011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_ENABLE_FIFO 0x01 42111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_CLEAR_RCVR 0x02 42211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_CLEAR_XMIT 0x04 42311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 42411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_DMA_SELECT 0x08 42511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_TRIGGER_MASK 0xF0 42611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_R_TRIGGER_1 0x00 42711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_R_TRIGGER_4 0x40 42811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 42911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_R_TRIGGER_8 0x80 43011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_R_TRIGGER_14 0xA0 43111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_T_TRIGGER_0 0x00 43211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_T_TRIGGER_4 0x10 43311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 43411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_T_TRIGGER_8 0x20 43511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_FCR_T_TRIGGER_12 0x30 43611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_SBC 0x40 43711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_SPAR 0x20 43811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 43911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_EPAR 0x10 44011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_PARITY 0x08 44111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_STOP 0x04 44211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_WLEN5 0x00 44311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_WLEN6 0x01 44511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_WLEN7 0x02 44611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LCR_WLEN8 0x03 44711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_TEMT 0x40 44811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_THRE 0x20 45011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_BI 0x10 45111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_FE 0x08 45211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_PE 0x04 45311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 45411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_OE 0x02 45511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_LSR_DR 0x01 45611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR_NO_INT 0x01 45711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR_ID 0x06 45811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 45911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR_MSI 0x00 46011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR_THRI 0x02 46111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR_RDI 0x04 46211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IIR_RLSI 0x06 46311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 46411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IER_MSI 0x08 46511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IER_RLSI 0x04 46611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IER_THRI 0x02 46711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_IER_RDI 0x01 46811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 46911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MCR_LOOP 0x10 47011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MCR_OUT2 0x08 47111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MCR_OUT1 0x04 47211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MCR_RTS 0x02 47311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 47411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MCR_DTR 0x01 47511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_DCD 0x80 47611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_RI 0x40 47711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_DSR 0x20 47811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 47911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_CTS 0x10 48011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_DDCD 0x08 48111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_TERI 0x04 48211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_DDSR 0x02 48311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 48411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_DCTS 0x01 48511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define UART_MSR_ANY_DELTA 0x0F 48611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_STATUS 0xB1600000 48711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_BF (1 << 4) 48811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 48911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_OF (1 << 3) 49011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_UF (1 << 2) 49111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_D (1 << 1) 49211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_B (1 << 0) 49311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_INT 0xB1600004 49511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INT_OI (1 << 3) 49611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INT_UI (1 << 2) 49711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INT_DI (1 << 1) 49811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_INT_ENABLE 0xB1600008 50011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INTE_OIE (1 << 3) 50111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INTE_UIE (1 << 2) 50211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INTE_DIE (1 << 1) 50311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 50411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_CONFIG 0xB1600020 50511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_AO (1 << 24) 50611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DO (1 << 23) 50711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_ALEN_BIT 20 50811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 50911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_ALEN_MASK (0x7 << 20) 51011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DLEN_BIT 16 51111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DLEN_MASK (0x7 << 16) 51211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DD (1 << 11) 51311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_AD (1 << 10) 51511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_BM_BIT 8 51611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_BM_MASK (0x3 << 8) 51711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_CE (1 << 7) 51811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DP (1 << 6) 52011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DL (1 << 5) 52111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_EP (1 << 4) 52211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_ADATA 0xB1600024 52311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 52411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_AD_D (1 << 24) 52511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_AD_ADDR_BIT 16 52611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_AD_ADDR_MASK (0xff << 16) 52711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_AD_DATA_BIT 0 52811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 52911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_AD_DATA_MASK (0xfff << 0) 53011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_CLKDIV 0xB1600028 53111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI0_CONTROL 0xB1600100 53211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONTROL_CD (1 << 1) 53311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 53411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONTROL_E (1 << 0) 53511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_STATUS 0xB1680000 53611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_INT 0xB1680004 53711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_INT_ENABLE 0xB1680008 53811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 53911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_CONFIG 0xB1680020 54011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_ADATA 0xB1680024 54111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_CLKDIV 0xB1680028 54211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI1_ENABLE 0xB1680100 54311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_BF (1 << 4) 54511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_OF (1 << 3) 54611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_UF (1 << 2) 54711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_D (1 << 1) 54811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_STATUS_B (1 << 0) 55011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INT_OI (1 << 3) 55111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INT_UI (1 << 2) 55211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INT_DI (1 << 1) 55311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 55411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INTEN_OIE (1 << 3) 55511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INTEN_UIE (1 << 2) 55611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_INTEN_DIE (1 << 1) 55711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_AO (1 << 24) 55811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 55911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DO (1 << 23) 56011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_ALEN (7 << 20) 56111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DLEN (15 << 16) 56211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DD (1 << 11) 56311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_AD (1 << 10) 56511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_BM (3 << 8) 56611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_CE (1 << 7) 56711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DP (1 << 6) 56811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DL (1 << 5) 57011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_EP (1 << 4) 57111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) 57211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) 57311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 57411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_BM_HI (0 << 8) 57511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_BM_LO (1 << 8) 57611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_CONFIG_BM_CY (2 << 8) 57711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_ADATA_D (1 << 24) 57811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 57911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_ADATA_ADDR (0xFF << 16) 58011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_ADATA_DATA 0x0FFF 58111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_ADATA_ADDR_N(N) (N << 16) 58211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_ENABLE_CD (1 << 1) 58311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 58411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SSI_ENABLE_E (1 << 0) 58511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IRDA_BASE 0xB0300000 58611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 58711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 58811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 58911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 59011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RING_SIZE (IRDA_BASE + 0x0C) 59111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RING_PROMPT (IRDA_BASE + 0x10) 59211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 59311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_INT_CLEAR (IRDA_BASE + 0x18) 59511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_CONFIG_1 (IRDA_BASE + 0x20) 59611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RX_INVERT_LED (1 << 0) 59711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_TX_INVERT_LED (1 << 1) 59811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_ST (1 << 2) 60011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_SF (1 << 3) 60111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_SIR (1 << 4) 60211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_MIR (1 << 5) 60311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_FIR (1 << 6) 60511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_16CRC (1 << 7) 60611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_TD (1 << 8) 60711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RX_ALL (1 << 9) 60811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_DMA_ENABLE (1 << 10) 61011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RX_ENABLE (1 << 11) 61111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_TX_ENABLE (1 << 12) 61211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_LOOPBACK (1 << 14) 61311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 61411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 61511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_SIR_FLAGS (IRDA_BASE + 0x24) 61611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_ENABLE (IRDA_BASE + 0x28) 61711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RX_STATUS (1 << 9) 61811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 61911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_TX_STATUS (1 << 10) 62011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) 62111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) 62211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) 62311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 62411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) 62511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_CONFIG_2 (IRDA_BASE + 0x3C) 62611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_MODE_INV (1 << 0) 62711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_ONE_PIN (1 << 1) 62811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 62911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) 63011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PINFUNC 0xB190002C 63111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_USB (1 << 15) 63211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_U3 (1 << 14) 63311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 63411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_U2 (1 << 13) 63511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_U1 (1 << 12) 63611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_SRC (1 << 11) 63711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_CK5 (1 << 10) 63811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 63911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_CK4 (1 << 9) 64011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_IRF (1 << 8) 64111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_UR3 (1 << 7) 64211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_I2D (1 << 6) 64311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_I2S (1 << 5) 64511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_NI2 (1 << 4) 64611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_U0 (1 << 3) 64711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_RD (1 << 2) 64811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_A97 (1 << 1) 65011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_S0 (1 << 0) 65111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PC (1 << 18) 65211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_LCD (1 << 17) 65311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_CS (1 << 16) 65511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_EX0 (1 << 9) 65611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC2_MASK (7 << 17) 65711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC2_AC97 0 65811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC2_SPI 0 66011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC2_I2S (1 << 17) 66111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC2_SMBUS (3 << 17) 66211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC2_GPIO (7 << 17) 66311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 66411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC3_MASK (7 << 20) 66511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC3_AC97 0 66611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC3_SPI 0 66711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC3_I2S (1 << 20) 66811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 66911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC3_SMBUS (3 << 20) 67011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC3_GPIO (7 << 20) 67111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_PSC1_S1 (1 << 1) 67211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 67311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TRIOUTRD 0xB1900100 67511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_TRIOUTCLR 0xB1900100 67611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_OUTPUTRD 0xB1900108 67711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_OUTPUTSET 0xB1900108 67811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_OUTPUTCLR 0xB190010C 68011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PINSTATERD 0xB1900110 68111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_PININPUTEN 0xB1900110 68211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define GPIO2_BASE 0xB1700000 68311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 68411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define GPIO2_DIR (GPIO2_BASE + 0) 68511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define GPIO2_OUTPUT (GPIO2_BASE + 8) 68611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 68711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 68811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 68911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define GPIO2_ENABLE (GPIO2_BASE + 0x14) 69011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_SCRATCH0 0xB1900018 69111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_SCRATCH1 0xB190001C 69211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_WAKEMSK 0xB1900034 69311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_ENDIAN 0xB1900038 69511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_POWERCTRL 0xB190003C 69611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_WAKESRC 0xB190005C 69711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_SLPPWR 0xB1900078 69811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_SLEEP 0xB190007C 70011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FREQCTRL0 0xB1900020 70111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV2_BIT 22 70211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 70311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 70411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FE2 (1 << 21) 70511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FS2 (1 << 20) 70611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV1_BIT 12 70711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 70811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 70911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FE1 (1 << 11) 71011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FS1 (1 << 10) 71111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV0_BIT 2 71211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 71311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 71411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FE0 (1 << 1) 71511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FS0 (1 << 0) 71611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FREQCTRL1 0xB1900024 71711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV5_BIT 22 71811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 71911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 72011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FE5 (1 << 21) 72111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FS5 (1 << 20) 72211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV4_BIT 12 72311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 72411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 72511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FE4 (1 << 11) 72611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FS4 (1 << 10) 72711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV3_BIT 2 72811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 72911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 73011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FE3 (1 << 1) 73111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_FC_FS3 (1 << 0) 73211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CLKSRC 0xB1900028 73311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 73411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_ME1_BIT 27 73511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) 73611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_DE1 (1 << 26) 73711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_CE1 (1 << 25) 73811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 73911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_ME0_BIT 22 74011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) 74111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_DE0 (1 << 21) 74211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_CE0 (1 << 20) 74311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MI2_BIT 17 74511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) 74611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_DI2 (1 << 16) 74711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_CI2 (1 << 15) 74811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUH_BIT 12 75011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) 75111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_DUH (1 << 11) 75211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_CUH (1 << 10) 75311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 75411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUD_BIT 7 75511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) 75611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_DUD (1 << 6) 75711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_CUD (1 << 5) 75811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 75911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MIR_BIT 2 76011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) 76111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_DIR (1 << 1) 76211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_CIR (1 << 0) 76311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 76411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_AUX 0x1 76511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_FQ0 0x2 76611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_FQ1 0x3 76711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_FQ2 0x4 76811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 76911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_FQ3 0x5 77011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_FQ4 0x6 77111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CS_MUX_FQ5 0x7 77211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_CPUPLL 0xB1900060 77311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 77411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SYS_AUXPLL 0xB1900064 77511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_CONFIG 0xB0000000 77611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RECV_SLOTS_BIT 13 77711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 77811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 77911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_XMIT_SLOTS_BIT 3 78011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 78111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_SG (1 << 2) 78211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_SYNC (1 << 1) 78311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RESET (1 << 0) 78511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_STATUS 0xB0000004 78611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_XU (1 << 11) 78711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_XO (1 << 10) 78811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RU (1 << 9) 79011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RO (1 << 8) 79111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_READY (1 << 7) 79211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_CP (1 << 6) 79311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_TR (1 << 5) 79511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_TE (1 << 4) 79611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_TF (1 << 3) 79711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RR (1 << 2) 79811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RE (1 << 1) 80011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RF (1 << 0) 80111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_DATA 0xB0000008 80211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_CMD 0xB000000C 80311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_WD_BIT 16 80511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_READ (1 << 7) 80611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_INDEX_MASK 0x7f 80711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_CNTRL 0xB0000010 80811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_RS (1 << 1) 81011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define AC97C_CE (1 << 0) 81111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SD0_XMIT_FIFO 0xB0600000 81211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SD0_RECV_FIFO 0xB0600004 81311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SD1_XMIT_FIFO 0xB0680000 81511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define SD1_RECV_FIFO 0xB0680004 81611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IOPORT_RESOURCE_START 0x10000000 81711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IOPORT_RESOURCE_END 0xffffffff 81811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IOMEM_RESOURCE_START 0x10000000 82011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define IOMEM_RESOURCE_END 0xffffffff 82111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_START 0 82211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_END 0 82311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEM_START 0 82511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEM_END 0 82611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_FIRST_DEVFN 0 82711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LAST_DEVFN 0 82811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef _LANGUAGE_ASSEMBLY 83011cd02dfb91661c65134cac258cf5924270e9d2Dan Alberttypedef volatile struct { 83111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 toytrim; 83211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 toywrite; 83311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 toymatch0; 83511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 toymatch1; 83611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 toymatch2; 83711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 cntrctrl; 83811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 scratch0; 84011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 scratch1; 84111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 freqctrl0; 84211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 freqctrl1; 84311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 clksrc; 84511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 pinfunc; 84611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved0; 84711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 wakemsk; 84811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 endian; 85011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 powerctrl; 85111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 toyread; 85211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 rtctrim; 85311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 rtcwrite; 85511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 rtcmatch0; 85611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 rtcmatch1; 85711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 rtcmatch2; 85811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 rtcread; 86011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 wakesrc; 86111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 cpupll; 86211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 auxpll; 86311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved1; 86511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved2; 86611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved3; 86711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved4; 86811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 slppwr; 87011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 sleep; 87111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved5[32]; 87211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 trioutrd; 87311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define trioutclr trioutrd 87511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 reserved6; 87611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 outputrd; 87711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define outputset outputrd 87811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 outputclr; 88011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert u32 pinstaterd; 88111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define pininputen pinstaterd 88211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert} AU1X00_SYS; 88311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 88511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef _LANGUAGE_ASSEMBLY 88611cd02dfb91661c65134cac258cf5924270e9d2Dan Albertstruct cpu_spec { 88711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert unsigned int prid_mask; 88811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert unsigned int prid_value; 89011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert char *cpu_name; 89111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert unsigned char cpu_od; 89211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert unsigned char cpu_bclk; 89311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert unsigned char cpu_pll_wo; 89511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert}; 89611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 89711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 89811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899