111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert/**************************************************************************** 211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert **************************************************************************** 311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** This header was automatically generated from a Linux kernel header 511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** of the same name, to make information necessary for userspace to 611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** call into the kernel available to libc. It contains only constants, 711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** structures, and macros generated from the original header, and thus, 811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** contains no copyrightable information. 911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert *** 1011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert **************************************************************************** 1111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert ****************************************************************************/ 1211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#ifndef LINUX_PCI_REGS_H 1311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define LINUX_PCI_REGS_H 1411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 1511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VENDOR_ID 0x00 1611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_DEVICE_ID 0x02 1711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND 0x04 1811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_IO 0x1 1911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_MEMORY 0x2 2011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_MASTER 0x4 2111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_SPECIAL 0x8 2211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_INVALIDATE 0x10 2311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_VGA_PALETTE 0x20 2411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_PARITY 0x40 2511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_WAIT 0x80 2611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_SERR 0x100 2711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_FAST_BACK 0x200 2811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_COMMAND_INTX_DISABLE 0x400 2911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 3011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS 0x06 3111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_CAP_LIST 0x10 3211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_66MHZ 0x20 3311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_UDF 0x40 3411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_FAST_BACK 0x80 3511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_PARITY 0x100 3611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_MASK 0x600 3711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_FAST 0x000 3811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_MEDIUM 0x200 3911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DEVSEL_SLOW 0x400 4011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_SIG_TARGET_ABORT 0x800 4111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_REC_TARGET_ABORT 0x1000 4211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_REC_MASTER_ABORT 0x2000 4311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 4411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_STATUS_DETECTED_PARITY 0x8000 4511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 4611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CLASS_REVISION 0x08 4711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_REVISION_ID 0x08 4811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CLASS_PROG 0x09 4911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CLASS_DEVICE 0x0a 5011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 5111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CACHE_LINE_SIZE 0x0c 5211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_LATENCY_TIMER 0x0d 5311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE 0x0e 5411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE_NORMAL 0 5511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE_BRIDGE 1 5611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_HEADER_TYPE_CARDBUS 2 5711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 5811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST 0x0f 5911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST_CODE_MASK 0x0f 6011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST_START 0x40 6111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BIST_CAPABLE 0x80 6211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 6311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_0 0x10 6411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_1 0x14 6511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_2 0x18 6611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_3 0x1c 6711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_4 0x20 6811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_5 0x24 6911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_SPACE 0x01 7011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_SPACE_IO 0x01 7111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 7211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 7311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 7411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 7511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 7611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 7711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 7811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 7911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 8011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CARDBUS_CIS 0x28 8111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 8211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SUBSYSTEM_ID 0x2e 8311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS 0x30 8411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS_ENABLE 0x01 8511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 8611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 8711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAPABILITY_LIST 0x34 8811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 8911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_INTERRUPT_LINE 0x3c 9011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_INTERRUPT_PIN 0x3d 9111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MIN_GNT 0x3e 9211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MAX_LAT 0x3f 9311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 9411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PRIMARY_BUS 0x18 9511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SECONDARY_BUS 0x19 9611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SUBORDINATE_BUS 0x1a 9711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SEC_LATENCY_TIMER 0x1b 9811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_BASE 0x1c 9911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_LIMIT 0x1d 10011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 10111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_TYPE_16 0x00 10211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_TYPE_32 0x01 10311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_RANGE_MASK (~0x0fUL) 10411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SEC_STATUS 0x1e 10511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_BASE 0x20 10611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_LIMIT 0x22 10711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 10811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 10911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_MEMORY_BASE 0x24 11011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_MEMORY_LIMIT 0x26 11111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 11211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_TYPE_32 0x00 11311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_TYPE_64 0x01 11411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_RANGE_MASK (~0x0fUL) 11511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_BASE_UPPER32 0x28 11611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PREF_LIMIT_UPPER32 0x2c 11711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_BASE_UPPER16 0x30 11811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_IO_LIMIT_UPPER16 0x32 11911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 12011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ROM_ADDRESS1 0x38 12111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 12211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CONTROL 0x3e 12311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_PARITY 0x01 12411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_SERR 0x02 12511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_NO_ISA 0x04 12611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_VGA 0x08 12711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 12811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_BUS_RESET 0x40 12911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_BRIDGE_CTL_FAST_BACK 0x80 13011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 13111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_CAPABILITY_LIST 0x14 13211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 13311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SEC_STATUS 0x16 13411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_PRIMARY_BUS 0x18 13511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_CARD_BUS 0x19 13611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SUBORDINATE_BUS 0x1a 13711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_LATENCY_TIMER 0x1b 13811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_BASE_0 0x1c 13911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_LIMIT_0 0x20 14011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_BASE_1 0x24 14111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_MEMORY_LIMIT_1 0x28 14211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_0 0x2c 14311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_0_HI 0x2e 14411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_0 0x30 14511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_0_HI 0x32 14611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_1 0x34 14711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_BASE_1_HI 0x36 14811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_1 0x38 14911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_LIMIT_1_HI 0x3a 15011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_IO_RANGE_MASK (~0x03UL) 15111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 15211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CONTROL 0x3e 15311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_PARITY 0x01 15411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_SERR 0x02 15511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_ISA 0x04 15611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_VGA 0x08 15711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 15811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 15911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 16011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 16111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 16211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 16311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 16411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_SUBSYSTEM_ID 0x42 16511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CB_LEGACY_MODE_BASE 0x44 16611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 16711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_LIST_ID 0 16811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_PM 0x01 16911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_AGP 0x02 17011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_VPD 0x03 17111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SLOTID 0x04 17211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_MSI 0x05 17311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_CHSWP 0x06 17411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_PCIX 0x07 17511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_HT_IRQCONF 0x08 17611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_VNDR 0x09 17711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_SHPC 0x0C 17811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_EXP 0x10 17911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_ID_MSIX 0x11 18011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_LIST_NEXT 1 18111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_FLAGS 2 18211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CAP_SIZEOF 4 18311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 18411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_PMC 2 18511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_VER_MASK 0x0007 18611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_CLOCK 0x0008 18711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_RESERVED 0x0010 18811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_DSI 0x0020 18911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_AUX_POWER 0x01C0 19011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_D1 0x0200 19111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_D2 0x0400 19211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME 0x0800 19311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_MASK 0xF800 19411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D0 0x0800 19511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D1 0x1000 19611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D2 0x2000 19711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D3 0x4000 19811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CAP_PME_D3cold 0x8000 19911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL 4 20011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_STATE_MASK 0x0003 20111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 20211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_PME_ENABLE 0x0100 20311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 20411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 20511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_CTRL_PME_STATUS 0x8000 20611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_PPB_EXTENSIONS 6 20711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_PPB_B2_B3 0x40 20811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_BPCC_ENABLE 0x80 20911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_DATA_REGISTER 7 21011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PM_SIZEOF 8 21111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 21211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_VERSION 2 21311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_RFU 3 21411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS 4 21511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RQ_MASK 0xff000000 21611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_SBA 0x0200 21711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_64BIT 0x0020 21811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_FW 0x0010 21911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RATE4 0x0004 22011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RATE2 0x0002 22111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_STATUS_RATE1 0x0001 22211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND 8 22311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 22411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_SBA 0x0200 22511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_AGP 0x0100 22611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_64BIT 0x0020 22711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_FW 0x0010 22811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RATE4 0x0004 22911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RATE2 0x0002 23011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_COMMAND_RATE1 0x0001 23111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_AGP_SIZEOF 12 23211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 23311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_ADDR 2 23411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_ADDR_MASK 0x7fff 23511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_ADDR_F 0x8000 23611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VPD_DATA 4 23711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 23811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_ESR 2 23911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_ESR_NSLOTS 0x1f 24011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_ESR_FIC 0x20 24111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_SID_CHASSIS_NR 3 24211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 24311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS 2 24411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_64BIT 0x80 24511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_QSIZE 0x70 24611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_QMASK 0x0e 24711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_ENABLE 0x01 24811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_FLAGS_MASKBIT 0x100 24911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_RFU 3 25011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_ADDRESS_LO 4 25111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_ADDRESS_HI 8 25211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_DATA_32 8 25311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_DATA_64 12 25411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_MSI_MASK_BIT 16 25511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 25611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_CSR 2 25711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_DHA 0x01 25811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_EIM 0x02 25911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_PIE 0x04 26011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_LOO 0x08 26111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_PI 0x30 26211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_EXT 0x40 26311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_CHSWP_INS 0x80 26411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 26511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD 2 26611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_DPERR_E 0x0001 26711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_ERO 0x0002 26811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_MAX_READ 0x000c 26911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_MAX_SPLIT 0x0070 27011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 27111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS 4 27211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_DEVFN 0x000000ff 27311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_BUS 0x0000ff00 27411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_64BIT 0x00010000 27511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_133MHZ 0x00020000 27611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_SPL_DISC 0x00040000 27711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_UNX_SPL 0x00080000 27811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_COMPLEX 0x00100000 27911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_MAX_READ 0x00600000 28011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_MAX_SPLIT 0x03800000 28111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_MAX_CUM 0x1c000000 28211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_SPL_ERR 0x20000000 28311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_266MHZ 0x40000000 28411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_X_STATUS_533MHZ 0x80000000 28511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 28611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS 2 28711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_VERS 0x000f 28811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_TYPE 0x00f0 28911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_ENDPOINT 0x0 29011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_LEG_END 0x1 29111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_ROOT_PORT 0x4 29211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_UPSTREAM 0x5 29311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_DOWNSTREAM 0x6 29411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 29511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_SLOT 0x0100 29611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_FLAGS_IRQ 0x3e00 29711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP 4 29811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PAYLOAD 0x07 29911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PHANTOM 0x18 30011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_EXT_TAG 0x20 30111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_L0S 0x1c0 30211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_L1 0xe00 30311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 30411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_ATN_IND 0x2000 30511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PWR_IND 0x4000 30611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 30711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 30811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL 8 30911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_CERE 0x0001 31011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_NFERE 0x0002 31111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_FERE 0x0004 31211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_URRE 0x0008 31311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 31411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 31511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 31611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_PHANTOM 0x0200 31711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_AUX_PME 0x0400 31811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 31911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVCTL_READRQ 0x7000 32011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA 10 32111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_CED 0x01 32211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_NFED 0x02 32311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_FED 0x04 32411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_URD 0x08 32511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_AUXPD 0x10 32611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_DEVSTA_TRPND 0x20 32711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCAP 12 32811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKCTL 16 32911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_LNKSTA 18 33011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCAP 20 33111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTCTL 24 33211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_SLTSTA 26 33311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL 28 33411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_SECEE 0x01 33511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_SENFEE 0x02 33611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_SEFEE 0x04 33711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_PMEIE 0x08 33811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCTL_CRSSVE 0x10 33911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTCAP 30 34011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXP_RTSTA 32 34111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 34211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 34311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 34411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 34511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 34611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_ERR 1 34711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_VC 2 34811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_DSN 3 34911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_EXT_CAP_ID_PWR 4 35011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 35111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNCOR_STATUS 4 35211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_TRAIN 0x00000001 35311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_DLP 0x00000010 35411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_POISON_TLP 0x00001000 35511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_FCP 0x00002000 35611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_COMP_TIME 0x00004000 35711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_COMP_ABORT 0x00008000 35811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_UNX_COMP 0x00010000 35911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_RX_OVER 0x00020000 36011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_MALF_TLP 0x00040000 36111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_ECRC 0x00080000 36211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNC_UNSUP 0x00100000 36311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNCOR_MASK 8 36411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 36511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_UNCOR_SEVER 12 36611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 36711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_STATUS 16 36811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_RCVR 0x00000001 36911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_BAD_TLP 0x00000040 37011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_BAD_DLLP 0x00000080 37111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_REP_ROLL 0x00000100 37211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_REP_TIMER 0x00001000 37311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_COR_MASK 20 37411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 37511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP 24 37611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_FEP(x) ((x) & 31) 37711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_GENC 0x00000020 37811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_GENE 0x00000040 37911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 38011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 38111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_HEADER_LOG 28 38211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_COMMAND 44 38311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 38411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 38511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 38611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 38711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 38811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 38911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_STATUS 48 39011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_COR_RCV 0x00000001 39111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 39211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 39311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 39411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 39511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 39611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 39711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 39811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 39911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 40011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_COR_SRC 52 40111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_ERR_ROOT_SRC 54 40211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 40311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_REG1 4 40411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_REG2 8 40511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_CTRL 12 40611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_PORT_STATUS 14 40711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CAP 16 40811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_CTRL 20 40911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_VC_RES_STATUS 26 41011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 41111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DSR 4 41211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA 8 41311cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 41411cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 41511cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 41611cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 41711cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 41811cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 41911cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_CAP 12 42011cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 42111cd02dfb91661c65134cac258cf5924270e9d2Dan Albert 42211cd02dfb91661c65134cac258cf5924270e9d2Dan Albert#endif 423