| de2d8694e25a814696358e95141f4b1aa4d8847e |
|
20-Sep-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r275480
Bug: http://b/31320715
This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.
Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)
Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f3ef5332fa3f4d5ec72c178a2b19dac363a19383 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
|
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 59d3ae6cdc4316ad338cd848251f33a236ccb36c |
|
15-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add addrspacecast instruction.
Patch by Michele Scandale!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d4f5a615674aaabeee4e444e708d1fa00a41495e |
|
09-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[Stackmap] Materialize the jump address within the patchpoint noop slide.
This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.
Differential Revision: http://llvm-reviews.chandlerc.com/D2074
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f9d2d2dc89f0c2d39f597038ee723fb9c9af91da |
|
12-Sep-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: implemented extractelement with variable index.
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 69c474ffa8a4b0186067e39d338a165d4165af2b |
|
02-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b6ac30a15591a8dab3cff3f0891d7e1ca9476826 |
|
30-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, Y), -1)). Fixes PR17038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4edfa2278aa34876abffe67bfb66c0f92bd597a5 |
|
29-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: added extend and truncate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8ba76daba09e79b10c4aad8f4298433c6dafa6d5 |
|
21-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: Added SHIFT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ff79bc6e189f4d38021bba6a99d1d9e1af999df3 |
|
18-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Make more of the lowering helpers static. Also use MVT instead of EVT in a couple places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 35e194fbadb5b89406b176e44e67f78b514b0cb1 |
|
14-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Make more helper methods into static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 158ec07008961c3cb506ebafd7c0201ca2001a33 |
|
14-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Make some helper methods static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4d36bd80e68b8245ba4fcf26d33dbf35da3e2002 |
|
13-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: Added CMP and BLEND instructions.
Lowering for SETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fac4a4eb7dfbfc90ae1d5c7d6c39a2d89a33c30e |
|
11-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.
Added a test for shuffles using VPERM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 72feef14f16d138114040e486fb2c1ef7a9358e0 |
|
08-Aug-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Fix the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 207600d2cfa2b06bfeb0c1670f198f1aa1a1aa58 |
|
07-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512 set: Added BROADCAST instructions
with lowering logic and a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d113448c1dd5f40522c3c02db96e87a9eb59eaf4 |
|
06-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:
define i64 @test1(i64 %val) {
%in = trunc i64 %val to i32
tail call i32 @ret32(i32 returned %in)
ret i64 %val
}
define i64 @test2(i64 %val) {
tail call i32 @ret32(i32 returned undef)
ret i32 42
}
should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.
For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
call.
Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).
This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.
Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 13e6e9171f79a481d7f814aad958460dfd867c71 |
|
05-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.
Added intrinsics and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 75311b7b4dbb284e7539c0c62331387f3c4cd1ec |
|
04-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }
before:
_test:
ucomisd %xmm0, %xmm1
ja LBB0_2
movaps %xmm3, %xmm2
LBB0_2:
movaps %xmm2, %xmm0
after:
_test:
cmpltsd %xmm1, %xmm0
andpd %xmm0, %xmm2
andnpd %xmm3, %xmm0
orpd %xmm2, %xmm0
Small speedup on Benchmarks/SmallPT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8395251c0a1f16531e7f4d11a766a4a1e3d25520 |
|
31-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
|
09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a5e5ba611f787f518fd3f7349343f8c4ae863fc2 |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 13bbe1f52e8d57151e2730db49094e1c62a4c793 |
|
05-Apr-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the target options specified on a function to reset the back-end.
During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c26392aa5d9c2dbca2909d6874d181455f8aeb8f |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f8fd883fd368316ad3738dad6c15b1b8f3850f88 |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add XTEST codegen support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
|
01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d6f19c716378bce0acc3cbfc9dc9297468f046a0 |
|
15-Feb-2013 |
Eli Bendersky <eliben@google.com> |
The operand listing is very much outdated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4aee1bb2223e59efb814a694edaecd07a3418da0 |
|
28-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b84b4236343727ab1cd9c1cb4e3e3a43fa69c6c2 |
|
21-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make helper method static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d713c0f7f1556f1ff74b3e953be5d35b614cc081 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Capitalize lowerTRUNCATE so that it matches the other lower functions in this file despite it not matching coding standards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 26827f3dc5fc2e614fb2409e5371de6132eaa8a7 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make LowerVSETCC a static function and use MVT instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f84b7500ce489d2e4039348ed30bf584f0b61973 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Make some helper methods static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 00a312c478771941bc3e98cfbe6728465c769807 |
|
20-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Capitalize LowerVectorIntExtend to be consistent with all the other lower functions in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 13f8cf55d43980e73d6cbb8f4894607709daa311 |
|
09-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Efficient lowering of vector sdiv when the divisor is a splatted power of two constant.
PR 14848. The lowered sequence is based on the existing sequence the target-independent
DAG Combiner creates for the scalar case.
Patch by Zvi Rackover.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
|
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e503319874f57ab4a0354521b03a71cf8e07b866 |
|
04-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
LoopVectorizer:
1. Add code to estimate register pressure.
2. Add code to select the unroll factor based on register pressure.
3. Add bits to TargetTransformInfo to provide the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 82860f63e1678077fe665c21179b9df47fd313bb |
|
03-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a subtype parameter to VTTI::getShuffleCost
In order to cost subvector insertion and extraction, we need to know
the type of the subvector being extracted.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ae34b4280ebde6217706902e8a27bb858765a61c |
|
28-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: initial checkin for code that estimates the cost of special shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0509db27386f5cafffd364618365ecda741cf0bd |
|
28-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1a330af3b54aada0b2028cf6793d90c9e2974567 |
|
27-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 739c7a83e16e7daaf22cfa4ae84e8d1cc0260941 |
|
21-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics
This is very mechanical, no functionality change. Preparation for PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 042a9a2666690d0170964df3d0b042b7bc4651d5 |
|
21-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a missing "virtual" keyword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f5637c399711e37287e01f9d9ca9ce7cd2f3d14f |
|
21-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Improve the X86 cost model for loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e5c65911a659e49320d214bf0702793ad37b5ed5 |
|
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0340557fb830e3669c4c48a2cd99d7703bdda452 |
|
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b926afcc5b99030fecf496d15cffdd1315fd0ead |
|
17-Dec-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add ANDN to isDefConvertible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 388fc6a988b56a50efff57893a4df14b4d04e1cd |
|
15-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Add a couple of target-specific dag combines that turn VSELECTS into psubus if possible.
We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases
if y is a constant. DAGCombiner canonicalizes those so we first have to undo the
canonicalization for those cases. The pattern occurs in gzip when the loop
vectorizer is enabled. Part of PR14613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7d34267df63e23be1957f738de783c145febb7af |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 61f4dfe3693bf68b20748d82ac4dd9bf2f356699 |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 47fd10f2fc45d280308b77ed4eda16f3c9c88248 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
Accordingly, add bitsLT (and similar) to MVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bade0345d190427a08b2b947bc94f4d8ca5d7717 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
|
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5518a1355b8b09bf92419b65ea4e4854734b0ebc |
|
09-Dec-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
- Re-enable population count loop idiom recognization
- fix a bug which cause sigfault.
- add two testing cases which was causing crash
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7065a2bcec3b775da12cf8fbcd6fa972d5f2afeb |
|
08-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the patches adding a popcount loop idiom recognition pass.
There are still bugs in this pass, as well as other issues that are
being worked on, but the bugs are crashers that occur pretty easily in
the wild. Test cases have been sent to the original commit's review
thread.
This reverts the commits:
r169671: Fix a logic error.
r169604: Move the popcnt tests to an X86 subdirectory.
r168931: Initial commit adding the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2766a47310b05228e9bbc536d9f3a593fc31cd12 |
|
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace r169459 with something safer. Rather than having computeMaskedBits to
understand target implementation of any_extend / extload, just generate
zero_extend in place of any_extend for liveouts when the target knows the
zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8a7186dbc2df4879f511b2ae6f2bce25ad37d965 |
|
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
%tmp2 = load i16* %ptr, align 2
br label %bb2
bb2:
%tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
%cmp = icmp ult i16 %tmp3, 24
br i1 %cmp, label %bb3, label %exit
bb3:
call void @bar() nounwind
br label %exit
exit:
ret void
}
This compiles to the followings before:
push {lr}
mov r2, #0
cmp r1, #99
bhi LBB0_2
@ BB#1: @ %bb1
ldrh r2, [r0]
LBB0_2: @ %bb2
uxth r0, r2
cmp r0, #23
bhi LBB0_4
@ BB#3: @ %bb3
bl _bar
LBB0_4: @ %exit
pop {lr}
bx lr
The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 226e0e6264dc15ea8f26261a813eae3c17987b3b |
|
05-Dec-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Simplified BLEND pattern matching for shuffles.
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a1514e24cc24b050f53a12650e047799358833a1 |
|
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 84fca61ca5fba5c33a799d9133750b6832ddef7e |
|
29-Nov-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
rdar://12100355 (part 1)
This revision attempts to recognize following population-count pattern:
while(a) { c++; ... ; a &= a - 1; ... },
where <c> and <a>could be used multiple times in the loop body.
TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent
instruction sequence, which need to be improved in the following commits.
Reviewed by Nadav, really appreciate!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2da3691d6d025221c901fe6d9e7e2e77f3c9c2e0 |
|
11-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Move some helper methods to being static functions in the implementation file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5ed5c37d7fd4bc1a132ee5a6dd5b698202b92871 |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Removed unimplemented method declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8aae8ddb929cf2b528fb755ed5206d69c0d34e08 |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper functions static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9c7ae01f390b3d7c0fab562e69aba253d28a6dfb |
|
10-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
|
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b042868c01925dae3a1032890f591f1da78b19d3 |
|
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Cost Model: add tables for some avx type-conversion hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7ae3bcca4502f79fdadbfbbb0e68c5e14cc699fa |
|
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: Add tables for the common x86 compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b4b04c3fa0a5da15424de7818e9f72811495c65b |
|
03-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
X86 CostModel: Add support for a some of the common arithmetic instructions for SSE4, AVX and AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0c31e43ff3565f6b801793c916ba102050bcc128 |
|
03-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a stub for the x86 cost model impl. Implement a basic cost rule for inserting/extracting from XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c5c970ee852e345ded08cdfc33c4621ca76211b1 |
|
31-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Clean up redundant SP register maintained in X86 TLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4c74a956b2621bb7bb1df0b2f7571060eb095464 |
|
30-Oct-2012 |
Manman Ren <mren@apple.com> |
X86 MMX: optimize transfer from mmx to i32
We used to generate a store (movq) + a load.
Now we use movd.
rdar://9946746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a7554630e9e8967104f4183be3dfebf79ba0b1e5 |
|
23-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add custom UINT_TO_FP from v4i8/v4i16/v8i8/v8i16 to v4f32/v8f32
- Replace v4i8/v8i8 -> v8f32 DAG combine with custom lowering to reduce
DAG combine overhead.
- Extend the support to v4i16/v8i16 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d9d09600ee7ffa5e8fcaf13fa5b37c144831e6c6 |
|
23-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| facace808cc5f83067a05c4c319f98fd75336f47 |
|
19-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Lower BUILD_VECTOR to SHUFFLE + INSERT_VECTOR_ELT for X86
- If INSERT_VECTOR_ELT is supported (above SSE2, either by custom
sequence of legal insn), transform BUILD_VECTOR into SHUFFLE +
INSERT_VECTOR_ELT if most of elements could be built from SHUFFLE with few
(so far 1) elements being inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bedcbd433dbbba303df0ced76bec02b01b7b8f4d |
|
16-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Support v8f32 to v8i8/vi816 conversion through custom lowering
- Add custom FP_TO_SINT on v8i16 (and v8i8 which is legalized as v8i16 due to
vector element-wise widening) to reduce DAG combiner and its overhead added
in X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6c0e04c823cf4034214b050e338c99a401edd2ac |
|
16-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add __builtin_setjmp/_longjmp supprt in X86 backend
- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also
used as a light-weight replacement of setjmp/longjmp which are used to
implementation continuation, user-level threading, and etc. The support added
in this patch ONLY addresses this usage and is NOT intended to support SjLj
exception handling as zero-cost DWARF exception handling is used by default
in X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 44c2d61b6703469a95fcd2d5397c5d09a67e75c1 |
|
10-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add support for FP_ROUND from v2f64 to v2f32
- Due to the current matching vector elements constraints in
ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from
v2f32) is scalarized. Add a customized v2f32 widening to convert it
into a target-specific X86ISD::VFPROUND to work around this
constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9d796db3e746c31dbdb605510c53b3da98d71b38 |
|
10-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add alternative support for FP_ROUND from v2f32 to v2f64
- Due to the current matching vector elements constraints in ISD::FP_EXTEND,
rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening
to convert it into a target-specific X86ISD::VFPEXT to work around this
constraints. This patch also reverts a previous attempt to fix this issue by
recovering the scalarized ISD::FP_EXTEND pattern and thus significantly
reduces the overhead of supporting non-power-2 vector FP extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e5e8f7656a3b37c4c0c7936f78fa2586f06fbb9a |
|
25-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add missing i64 max/min/umax/umin on 32-bit target
- Turn on atomic6432.ll and add specific test case as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b1cacc74232164a9d80ee65d20e0095b25eb74d8 |
|
25-Sep-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix an illegal tailcall opt where the callee returns a double via xmm while caller returns x86_fp80 via st0. rdar://12229511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b118a073d7434727a4ea5a5762f54e54e72bef4f |
|
20-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Re-work X86 code generation of atomic ops with spin-loop
- Rewrite/merge pseudo-atomic instruction emitters to address the
following issue:
* Reduce one unnecessary load in spin-loop
previously the spin-loop looks like
thisMBB:
newMBB:
ld t1 = [bitinstr.addr]
op t2 = t1, [bitinstr.val]
not t3 = t2 (if Invert)
mov EAX = t1
lcs dest = [bitinstr.addr], t3 [EAX is implicit]
bz newMBB
fallthrough -->nextMBB
the 'ld' at the beginning of newMBB should be lift out of the loop
as lcs (or CMPXCHG on x86) will load the current memory value into
EAX. This loop is refined as:
thisMBB:
EAX = LOAD [MI.addr]
mainMBB:
t1 = OP [MI.val], EAX
LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
JNE mainMBB
sinkMBB:
* Remove immopc as, so far, all pseudo-atomic instructions has
all-register form only, there is no immedidate operand.
* Remove unnecessary attributes/modifiers in pseudo-atomic instruction
td
* Fix issues in PR13458
- Add comprehensive tests on atomic ops on various data types.
NOTE: Some of them are turned off due to missing functionality.
- Revise tests due to the new spin-loop generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f966e4e5b344e02ddd026a628db7079b62df60e6 |
|
13-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Add wider vector/integer support for PR12312
- Enhance the fix to PR12312 to support wider integer, such as 256-bit
integer. If more than 1 fully evaluated vectors are found, POR them
first followed by the final PTEST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 55b24054843e611e1b364e8175c7dedba8d11c86 |
|
11-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Make a bunch of lowering helper functions static instead of member functions. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d60cb11afd709b9f84c58d8335cbc08ad912b236 |
|
19-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
When unsafe math is used, we can use commutative FMAX and FMIN. In some cases
this allows for better code generation.
Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.
For example:
movaps %xmm0, %xmm1
movsd LC(%rip), %xmm0
minsd %xmm1, %xmm0
becomes:
minsd LC(%rip), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c087870c470b033a190aa08269095441816963e4 |
|
17-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to reduce to only a single call to it thus allowing it to be inlined by the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7091b2451d46ae7e85188d1c5d7a43d775346ee0 |
|
14-Aug-2012 |
Michael Liao <michael.liao@intel.com> |
fix PR11334
- FP_EXTEND only support extending from vectors with matching elements.
This results in the scalarization of extending to v2f64 from v2f32,
which will be legalized to v4f32 not matching with v2f64.
- add X86-specific VFPEXT supproting extending from v4f32 to v2f64.
- add BUILD_VECTOR lowering helper to recover back the original
extending from v4f32 to v2f64.
- test case is enhanced to include different vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bccc8ce9b8f3bd5403a034e75ba2d1c80a5a89fa |
|
13-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4feb647283db0ea4660941d3ac4202947b1ce196 |
|
06-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3 |
|
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1503aba4a036f5394c7983417bc1e64613b2fc77 |
|
01-Aug-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added FMA functionality to X86 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2127c9b93a5fd5f04ffaced84bde0696bd57fce6 |
|
19-Jul-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 70e10d3fe4c5df189348f64fce56254a5a32b51c |
|
17-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
This is another case where instcombine demanded bits optimization created
large immediates. Add dag combine logic to recover in case the large
immediates doesn't fit in cmp immediate operand field.
int foo(unsigned long l) {
return (l>> 47) == 1;
}
we produce
%shr.mask = and i64 %l, -140737488355328
%cmp = icmp eq i64 %shr.mask, 140737488355328
%conv = zext i1 %cmp to i32
ret i32 %conv
which codegens to
movq $0xffff800000000000,%rax
andq %rdi,%rax
movq $0x0000800000000000,%rcx
cmpq %rcx,%rax
sete %al
movzbl %al,%eax
ret
TargetLowering::SimplifySetCC would transform
(X & -256) == 256 -> (X >> 8) == 1
if the immediate fails the isLegalICmpImmediate() test. For x86,
that's immediates which are not a signed 32-bit immediate.
Based on a patch by Eli Friedman.
PR10328
rdar://9758774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b9bee0499553358e64c34cfcbd32380ac7fb452e |
|
12-Jul-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add intrinsics for Ivy Bridge's rdrand instruction.
The rdrand/cmov sequence is the same that is emitted by both
GCC and ICC.
Fixes PR13284.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2a5dc43bd97487ea33a1af4e686661ad90f192ad |
|
09-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f0234fcbc9be9798c10dedc3e3c134b7afbc6511 |
|
01-Jun-2012 |
Hans Wennborg <hans@hanshq.net> |
Implement the local-dynamic TLS model for x86 (PR3985)
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
|
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 17c836c4b51a14f07a5d5442cf2e984474a8f57d |
|
27-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8325c11d473a340217fa0de648ba8f733f2d626e |
|
16-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge vpermps/vpermd and vpermpd/vpermq SD nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 73c504af9d86a426532ee32c5d07a4b872794675 |
|
15-Apr-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added VPERM optimization for AVX2 shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 42fc29e7176ff51d649eccf82c836510fde4438f |
|
14-Apr-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ~*x & y.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e611378a6e45fcb4a039d8c0089cd8fed2d311dc |
|
11-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Reapply 154396 after fixing a test.
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a1390516548b7abee4f1eb305afecdca5733ee30 |
|
10-Apr-2012 |
Eric Christopher <echristo@apple.com> |
Temporarily revert this patch to see if it brings the buildbots back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 50e64cfe6e250dbe2528fc5bda75c68b04a8bc49 |
|
10-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bf010eb9110009d745382bf15131fbe556562ffe |
|
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a long standing tail call optimization bug. When a libcall is emitted
legalizer always use the DAG entry node. This is wrong when the libcall is
emitted as a tail call since it effectively folds the return node. If
the return node's input chain is not the entry (i.e. call, load, or store)
use that as the tail call input chain.
PR12419
rdar://9770785
rdar://11195178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 154819dd6f60d0d1d1c75a22e8902c5125fad49b |
|
09-Apr-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix a bug in the lowering of broadcasts: ConstantPools need to use the target pointer type.
Move NormalizeVectorShuffle and LowerVectorBroadcast into X86TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9a68fdc7f8211a9330537d44e3406d79fc5562af |
|
25-Feb-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 lowering for i386-*-win32 targets. Patch by Joe Groff.
[Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems:
Clang raised a warning, and X86 LowerOperation would assert out for
fptoui f64 to i32 because it improperly lowered to an illegal
BUILD_PAIR. Here's a patch that addresses these issues. Let me know if
any other changes are necessary. Thanks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1a2d061ec08b86ba91d7009b6ffcf08d5bac3f42 |
|
24-Feb-2012 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Add WIN_FTOL_* psudo-instructions to model the unique calling convention
used by the Win32 _ftol2 runtime function. Patch by Joe Groff!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5aaffa84703debaba17650c5ca9eae9a49844cf1 |
|
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make a bunch of X86ISelLowering shuffle functions static now that they are no longer needed by isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5b209e84f498b0e98d7f92123eac50a651aa01e1 |
|
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| dcabc7bca9b81c384d307cbb7d28b29451e263f2 |
|
02-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimization for SIGN_EXTEND operation on AVX.
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3ae98150e3e3c4770644a33cf38fe42a582509bb |
|
01-Feb-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Optimization for "truncate" operation on AVX.
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 86c7c583a36e54ea13f2ee31d622090b4fe9c184 |
|
30-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1906d32e55224b7481cd9e5726bd5e14b55f5cc1 |
|
23-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 67609fd0eb05a49cc4636d507398034393dcf302 |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ed2e13d66709d41a26b96e2a02b6f2797ff2e7b7 |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6a32b6f0c088e4d2972cf5d208c54f42c2c52f85 |
|
22-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unused X86 ISD node type defines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1a7700a3fac132b89fa8d577fe90c20a95a5494e |
|
19-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 435d0bd09d34d0a9df2418b121c845841b0b5e11 |
|
08-Jan-2012 |
Victor Umansky <victor.umansky@intel.com> |
Reverted commit #147601 upon Evan's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 19d8559019b75edfd7f5b05ffa266bc278127854 |
|
05-Jan-2012 |
Victor Umansky <victor.umansky@intel.com> |
Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX.
Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX)
Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b3982da7d219edb24795d7e01513cc55fcd7bd16 |
|
01-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Merge X86 SHUFPS and SHUFPD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| acc068e873a1a2afa1edef20452722d97eec8f71 |
|
24-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:
(sizeof(x)*8 - 1) ^ __builtin_clz(x)
Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.
The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.
Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.
These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ab44d3cf49886f14018db9e67fffc58d9c67cbfb |
|
17-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove an unused X86ISD node type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 94438ba53828ed866d1d18ba94faabf4253cf194 |
|
16-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d93e4c34963e83befbe67370fa39b66530b5e193 |
|
11-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 34671b812a9855623fd9a02e5e2b2cb95a13ba2f |
|
06-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge floating point and integer UNPCK X86ISD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ec24e61ab0a22f58fedac374ef0df3e69d9a2587 |
|
30-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge VPERM2F128/VPERM2I128 ISD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 316cd2a2c57037ecca93bb20d939b89dad4c5243 |
|
30-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 70b883b3a723b1d0af538c0b78cd45139597d216 |
|
28-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 38034c568c5f006b5bfe57d6777f5479282ed511 |
|
26-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 06cb680779597c35e6b6399dea6f10276273970b |
|
26-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 705f2431a086bbe662bca0035938e774378de3ec |
|
24-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f475a55bd41a2fc047e74c38014564e8e6b678f0 |
|
24-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6fa583d78701390079db0cc4d944823af06023c6 |
|
21-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6347e8662cea47065ed7092d75322076fc3e57f8 |
|
21-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 54f952afac04cb1e944f4fa0c1cd494e291bef20 |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3113384a346709f1c3578c4ff2bd15c920dc02a6 |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 15701f8969fcb36899a75ca2df6fdcbc52141106 |
|
27-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Rename NonScalarIntSafe to something more appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b4c945716f232ee07ec6fd3e1146175801fa1278 |
|
21-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 54a11176f6a5e07e243f1d87ba19ac3f4681976b |
|
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 ANDN instruction. Including instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 17470bee5fd18bb2eae7825dae535c060a34ee7d |
|
22-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fbad25e12073e2cbe192b2c4cc4f0bbb26148c9c |
|
11-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
CR fixes per Bruno's request.
Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8ffad56f8eb41c73ecf40d1aa473819eb6915c12 |
|
09-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ffe3e7da849a10cdbe8ee4e5b5e243fc48ca0ffd |
|
08-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add X86-SSE4 codegen support for vector-select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5c984df26b0391fec853f76722df7b2bb2c9ee4c |
|
06-Sep-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix comment. Noticed by Duncan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4a544a79bd735967f1d33fe675ae4566dbd17813 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 151ab3e2f7b69d2b46fdc25cbad9d43f4a827ef1 |
|
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Adds support for variable sized allocas. For a variable sized alloca,
code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d07b7ec77203d4dbaf426786912a700cc07f0142 |
|
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Adds a SelectionDAG node X86SegAlloca which will be custom lowered
from DYNAMIC_STACKALLOC.
Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added. They
will be custom emitted to inject the actual stack handling code.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 43f51aeca8367ea35adad963c00bd2bc5b8d1391 |
|
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 13894fa135d33151072ddf5e80abe4540ec2afcd |
|
24-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0e6d230abdbf6ba67a2676c118431a4df8fb15dd |
|
17-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 53cae1362dca8aa312c3e36c10b106ea7d349f93 |
|
12-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9065d4b65f3bd57888d1ea8a2cdb2745a970165d |
|
29-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Cleanup PALIGNR handling and remove the old palign pattern fragment.
Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 14648468011c92a4210f8118721d58c25043daf8 |
|
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| cea34e41fa3bde8a7271c725abc6bb79c31377c9 |
|
27-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The vpermilps and vpermilpd have different behaviour regarding the
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4ea496846a84918c5e5cdd67ae43d6e2b0a110ea |
|
27-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Recognize unpckh* masks and match 256-bit versions. The new versions are
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9123c6fea0e07304094230cd8d44af0984ea5c66 |
|
26-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More movsldup/movshdup cleanup. Rewrite the mask matching function and add
support for 256-bit versions (but no instruction selection yet, coming next).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6683efb4cdb12785d19100e69f597156e434b9f4 |
|
22-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
-Inspected a AVX code block added by someone in early Feb. This was never used
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.
- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.
- Fix a fragile test and make it more useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 65b74e1d00eef81b596b4c207fba069aa1eb8214 |
|
21-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d0f3ef807ee4210b97a7a6bc4231e89403145b83 |
|
14-Jul-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
[VECTOR-SELECT]
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c1af4772f1f71a955c7c9cfbabba98a2a2c109e4 |
|
13-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The target specific node PANDN name is misleading. That happens because
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d176af8cf3e3b3fb39385798e25e55449933648c |
|
29-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Use getRegForInlineAsmConstraint instead of custom defining regclasses
via vectors.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ef41ff618f2537539b538e6c7bf471c753391f92 |
|
23-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetOptions.h dependency from X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 471e4224809f51652c71f319532697a879a75a0d |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f99a4b82a4ff0383138ccaf9e22511eb786168fb |
|
07-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Followup to 132458, omit unnecessary stack copy when x87 input is a
load. rdar://problem/6373334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 865f09334f67edb2000fb38c6c3c28283b88b3bf |
|
04-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Reapply 132424 with fixes. This fixes PR10068.
rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
|
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 251b4a04057a8397791ad3924377888fe4f8a2ad |
|
02-Jun-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 132424 to fix PR10068.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ec880283b3682982c750c9b78f6a9b4777e21883 |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Recommit 132404 with fixes. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4abc5fea9c6c3b329fec58840999db06e108e535 |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Revert 132404 to appease a buildbot. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 10ff0bbdfbeb6f7485979744d16daea4795d45b2 |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
Add support for x86 CMPEQSS and friends. These instructions do a
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs. Only profitable when the user wants a materialized 0
or 1 at runtime. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4fd0dee3bfe8a35bbb62c9e9dea511cbc06cec2d |
|
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
FGETSIGN support for x86, using movmskps/pd. Will be enabled with a
patch to TargetLowering.cpp. rdar://problem/5660695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2aa0f23e1cb5afc96981ecc057980d1958c0be72 |
|
26-May-2011 |
Stuart Hastings <stuart@apple.com> |
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| aa4e6afc9be330770e0b5d41e79aa26c3115bcca |
|
26-May-2011 |
Stuart Hastings <stuart@apple.com> |
Correctly handle a one-word struct passed byval on x86_64.
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b8e0d3412c8319a19f37c1d7000b786c8975bd61 |
|
17-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Clean up the mess created by r131467+r131469.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6db2c2fe216637f4120899c7734a8600c64af0e8 |
|
17-May-2011 |
Stuart Hastings <stuart@apple.com> |
Revert 131467 due to buildbot complaint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 504421e327a5af90dbb42f33086b6db6f6738477 |
|
17-May-2011 |
Stuart Hastings <stuart@apple.com> |
Fix an obscure issue in X86_64 parameter passing: if a tiny byval is
passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4301222525b565028850030835b8db9ce6d153db |
|
11-May-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
|
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 485fafc8406db8552ba5e3ff871a6ee32694ad90 |
|
21-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7a90e04fc76392972bd8bd0ddee5c934c22c1393 |
|
19-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ae16d6b9722dd6ff4a606308e3a14d200f3a903f |
|
19-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7bbf0ee97c77f7712154648a44ac6eeb57886462 |
|
17-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move more logic into getTypeForExtArgOrReturn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 44579680111b807613703ab401db3b8c0148e36c |
|
17-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ebe8173941238cfbabadb1c63bca7fb7dcf2adbe |
|
16-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
|
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 95771afbfd604ad003fa3723cac66c9370fed55d |
|
25-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fbf05d32b45478696df16277b5c363ef2b9bb7c9 |
|
23-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] General VUNPCKL codegen support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ccacdc1952d022108d51b1c8270eb85b2b862c9d |
|
04-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] Support VSINSERTF128 with more patterns and appropriate
infrastructure. This makes lowering 256-bit vectors to 128-bit
vectors simple when 256-bit vector support is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c38a03eeca3a506577b2d5a29629a81a0cefff03 |
|
03-Feb-2011 |
David Greene <greened@obbligato.org> |
[AVX] VEXTRACTF128 support. This commit includes patterns for
matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines
to examine and translate index values. VINSERTF128 comes next. With
these two in place we can begin supporting more AVX operations as
INSERT/EXTRACT can be used as a fallback when 256-bit support is not
available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| cfe33c46aa50f04adb0431243e7d25f79b719ac6 |
|
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR. Eventually this
will get matched to VINSERTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 91585098eff1f0acdefa2667e091742b60dcbf15 |
|
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 672fb6225b381b4dcb2e88fccb79d928eaabf82c |
|
20-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Implement feedback from Bruno on making pblendvb an x86-specific ISD node in addition to being an intrinsic, and convert
lowering to use it. Hopefully the pattern fragment is doing the right thing with XMM0, looks correct in testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5b85654844d673939bd1ceba66cd1f5022fd7c0d |
|
20-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which
their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.
We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.
With the previous series of changes, this causes no changes in the testsuite, woo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c19d1c3ba2b216f0f91d71cf6fc2e983fc995854 |
|
19-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
improve the setcc -> setcc_carry optimization to happen more
consistently by moving it out of lowering into dag combine.
Add some missing patterns for matching away extended versions of setcc_c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b65c175d32510d32aa556d1db5e6782b411d192c |
|
17-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Add support for matching psign & plendvb to the x86 target
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b20e0b1fddfd9099e12b84a71fbc8ccff5a12b10 |
|
05-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3d2125c9dbac695c93f42c0f59fd040e413fd711 |
|
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable sibling call optimization of libcalls which are expanded during
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 82be220092cfb9d432c5a6da1bd5e8c56dc21d4d |
|
30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Fix some cleanups from my last patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 228232b2821f8e7f9c0b874ad733414bda183db6 |
|
30-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite mwait and monitor support and custom lower arguments.
Fixes PR8573.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5bf7c534cf057a52f30624743841fadd241c4dbb |
|
27-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Lower TLS_addr32 and TLS_addr64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
|
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 59d2dad59ebba1d82e5b72f78b7a5b2c873445d7 |
|
20-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics,
so don't claim they are. They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory. This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this). Add some nasty checking to try
to catch this kind of thing in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 142b531e024c7b814df74951b378b9e3e11d0d42 |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
move the pic base symbol stuff up to MachineFunction
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4fd0ea01660d7e447f072a1032abf0d7537821bf |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
simplify getPICBaseSymbol a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4590766580ff94e3a7fa95cda7b602b23f14843e |
|
31-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
Factorize the duplicated logic for choosing the right argument
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 44ab89eb376af838d1123293a79975aede501464 |
|
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e9c253e0bc01fd50bf788efb62093a5fa6ef5849 |
|
21-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6e56b18e575228a4f7318297155fe6ba2502a39b |
|
21-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 320afb8c818b5cd5b9d4fcd0dba83ba3384ed4b4 |
|
12-Oct-2010 |
Dan Gohman <gohman@apple.com> |
Initial va_arg support for x86-64. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0488fb649a56b7fc89a5814df5308813f9e5a85d |
|
01-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Massive rewrite of MMX:
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f93b90c5dfe98958eb43715a6e674565ab162502 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 492a43e6f64997a0ab26ef047dced193931fda85 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the last 4 X86ISD nodes that should have memoperands to have them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2156b79c493751f165d445535f8b598b4769b3e8 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
can access the stack due to how it is generated though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0729093cd7e15ed6469e50b74f0edd7f205b50ff |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
used with stack slots, but hey, lets be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8864155a35eb59fbebfd1822aaf224128b5c5d23 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give VZEXT_LOAD a memory operand, it now works with segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 93c4a5bef780e43552d3b9d702756d3acb7801d2 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bc146b0a4dcee601459eee943b4133d3cf63f1dd |
|
21-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| eac6e1d0c748afc3d1496be0753ffbe5f5a4279b |
|
13-Sep-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Added skeleton for inline asm multiple alternative constraint support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 56098f5d26ed05401bd889960deffa72eb7bbce9 |
|
01-Sep-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f2db5b48d0a4f0800e83d8c3cd6dc5ad6a551bd6 |
|
31-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bf8154a4395bf941f57f6453503a850cb9805a64 |
|
21-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3157ef1c13376f669a32bc152f2c3000480cedd3 |
|
21-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This is the first step towards refactoring the x86 vector shuffle code. The
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 045573ce21282ee7d1c58e57d00a77ede8c732da |
|
11-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX matching patterns to Packed Bit Test intrinsics.
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bdcb5afb77547337ba148ce24d5e1046c0b25ced |
|
28-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches.
For:
define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
%shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2
}
We get:
_shl: ## @shl
pslld $23, %xmm1
paddd LCPI0_0, %xmm1
cvttps2dq %xmm1, %xmm1
pmulld %xmm1, %xmm0
ret
Instead of:
_shl: ## @shl
pshufd $3, %xmm0, %xmm2
movd %xmm2, %eax
pshufd $3, %xmm1, %xmm2
movd %xmm2, %ecx
shll %cl, %eax
movd %eax, %xmm2
pshufd $1, %xmm0, %xmm3
movd %xmm3, %eax
pshufd $1, %xmm1, %xmm3
movd %xmm3, %ecx
shll %cl, %eax
movd %eax, %xmm3
punpckldq %xmm2, %xmm3
movd %xmm0, %eax
movd %xmm1, %ecx
shll %cl, %eax
movd %eax, %xmm2
movhlps %xmm0, %xmm0
movd %xmm0, %eax
movhlps %xmm1, %xmm1
movd %xmm1, %ecx
shll %cl, %eax
movd %eax, %xmm0
punpckldq %xmm0, %xmm2
movdqa %xmm2, %xmm0
punpckldq %xmm3, %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| dee81010eb4f932b76dd3f64eacba13b55d2d105 |
|
26-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
On x86, f32 / f64 nodes share the same registers as 128-bit vector values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 70017e44cdba1946cc478ce1856a3e855a767e28 |
|
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9a9d275dc7897dfba7f41ce1b3770ca27ac149e8 |
|
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Custom lower the memory barrier instructions and add support
for lowering without sse2. Add a couple of new testcases.
Fixes a few libgomp tests and latent bugs. Remove a few todos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| dab4dac2a0b145be9bee4c25a5f5a502ab441f51 |
|
21-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Pulling out previous patch, must've run the tests in
the wrong directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 87f41370a827a1674640e8e1ef3af454679f16c9 |
|
21-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Lower MEMBARRIER on x86 and support processors without SSE2.
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b5378ea12e2171e6150df57c6ddc1039c4c48d3f |
|
15-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use TargetOpcode::COPY instead of X86-native register copy instructions when
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 84023e0fbefc406a4c611d3d64a10df5d3a97dd7 |
|
10-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 02266e29f9250d74c5ec720aff23add3410ae920 |
|
09-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r107947 into '.':
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bf87e2491789d6ff788629e22e93d0c1ca02ae85 |
|
09-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f59514152511694d46ca8b8d2db466d256ab5759 |
|
08-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f423a69839c4810b890f8a8b09fb8cfbd6bf0139 |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Add X86FastISel support for return statements. This entails refactoring
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a4160c3434b08288d1f79f1acbe453d1b9610b22 |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c9af33c6854afe7b082af2d892ec5f05dfa383c7 |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
SelectBasicBlock doesn't needs its BasicBlock argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f7a0c7bf8bc8318ed28d889c9a56437ab3e91385 |
|
06-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Fix up -fstack-protector on linux to use the segment
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
|
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 30ef0e5658b0b8b04437f73f74162d5d72923f29 |
|
03-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Add first pass at darwin tls compiler support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7d07b48b26370153246de179efe5548365d31054 |
|
21-May-2010 |
Dale Johannesen <dalej@apple.com> |
Fix i64->f64 conversion, x86-64, -no-sse. A bit
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ff7a562751604a9fe13efc75bd59622244b54d35 |
|
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 419e4f92635cfaa409282691437aff99062e4e0b |
|
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Remove the TargetLowering::getSubtarget() virtual function, which
was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 552f09a0d716a73dc70efd66384146e73ee63a3e |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Promoting 16-bit cmp / test aren't free. Don't do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 962021bc7f6721c20c7dfe8ca809e2d98b1c554a |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f822e733aff93b34e6cd85b2f92d86e71fe67f87 |
|
25-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Stop abusing EmitInstrWithCustomInserter for target-dependent
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2808ccb77515d049bfeb44fdf1228ccf9f034f2f |
|
23-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix X86ISD::CMP i16 to i32 promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f81eca0ab908fdcf98ae0efaa75acccc8ba40dc2 |
|
22-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5528e7bcb1209094a68bbf6d1efeefc3ca34774f |
|
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e5b51ac7708402473f0a558f4aac74fab63d4f7e |
|
17-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
More work to allow dag combiner to promote 16-bit ops to 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 37f32ee7ffe77d7c2bc1b185802e98979612f041 |
|
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 64b7bf71e84094193b40ab81aa7dacad921ecbea |
|
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2520864773dcb73d76d297605f4bc41c0cf3fa39 |
|
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Factor out EH landing pad code into a separate function, and constify
a bunch of stuff to support it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c3b0c341e731b27b550ee9dcded9c17232b296b8 |
|
08-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ed3a8067a60ecf2c215e77327a57904c3ebc3355 |
|
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
unthread MMI from FastISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d850ac79b57e6e0bf68ee93a94d0b3dcd9f6ca35 |
|
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fastisel doesn't need DwarfWriter, remove some tendricles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
|
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f28f8bc40eedc6304ab25dd8bed486fa08f51f70 |
|
02-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correctly lower memset / memcpy of undef. It should be a nop. PR6767.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1d8f83d0a00e912c55ec0974eba6122666cc6fa1 |
|
02-Apr-2010 |
Eric Christopher <echristo@apple.com> |
Revert r100143.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 42642d06c915a26af1400de6ce6a53c333e5c247 |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments about DstAlign and SrcAlign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 94107ba9ceaa199f8e5c03912511b0619c84226d |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Avoid using floating point stores to implement memset unless the value is zero.
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 255f20f7f76e4ca1ac1c73294852cb6fcb18c77d |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix sdisel memcpy, memset, memmove lowering:
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 100f090adde26005b9f1eca96871dff52825b27b |
|
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
|
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 86afec7730e719600952bc9019f25e85289032a9 |
|
25-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reapply Kevin's change 94440, now that Chris has fixed the limitation on
opcode values fitting in one byte (svn r99494).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 014dc4e7202f88fdd9c255837bf125f891f2f6b6 |
|
25-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Speculatively revert this to see if it fixes buildbot failures.
--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 760c2f34d94d01ddce47634e69bd77a3625899bf |
|
24-Mar-2010 |
Kevin Enderby <enderby@apple.com> |
Added the Advanced Encryption Standard (AES) Instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a375d471378b1674a9d77d180a0b05ea8c90cb4b |
|
15-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid sibcall optimization if either caller or callee is using sret semantics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a257095ebb29fd223be2fdbf86d542c5bdfe05f0 |
|
11-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Remove getWidenVectorType, which is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 043f3c2a0e286dcfd4cc5a16bf006e3c45929516 |
|
06-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Lower dynamic stack allocation on mingw32 to separate instruction.
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8f2b4cc07161b56e56d6615761ea4ba08dc0e7d3 |
|
23-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
X86InstrInfoSSE.td declares PINSRW as having type v8i16,
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes. This fixes an x86 testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4dd162f3945636cbe6123682619e994f75a62d00 |
|
12-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleanup stdcall / fastcall name mangling.
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b17124553d569c6f09347f2cbe072eab445d30c4 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Perform trivial tail call optimization for callees with "C" ABI. These are done
even when -tailcallopt is not specified and it does not require changing ABI.
First case is the most trivial one. Perform tail call optimization when both
the caller and callee do not return values and when the callee does not take
any input arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2a531673b95639174da449402f6609e7d5a14d2d |
|
26-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ddc419c581ac827045d614099adaa60765ce1ebe |
|
26-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 589c6f620e8dcf3d59af1ae0e15372c934647c82 |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Move getJTISymbol from MachineJumpTableInfo to MachineFunction,
which is more convenient, and change getPICJumpTableRelocBaseExpr
to take a MachineFunction to match.
Next, move the X86 code that create a PICBase symbol to
X86TargetLowering::getPICBaseSymbol from
X86MCInstLower::GetPICBaseSymbol, which was an asmprinter specific
library. This eliminates a 'gross hack', and allows us to
implement X86ISelLowering::getPICJumpTableRelocBaseExpr which now
calls it.
This in turn allows us to eliminate the
X86AsmPrinter::printPICJumpTableSetLabel method, which was the
only overload of printPICJumpTableSetLabel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c64daabb70a2e0cb115f78b0c1548e65c0d527ff |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
implement X86 @GOTOFF jump table entries with the new EK_Custom32
jump table entry kind, instead of overloading
AsmPrinter::printPICJumpTableEntry.
This has a pretty horrible and inefficient FIXME around how @GOTOFF
is currently smashed into the mcsymbol name, but otherwise this is
much cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5e1df8d1f71f1a8a534b8b5929a7dd670fe010c6 |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
in 32-bit pic mode for targets with a GOT, x86 emits jump table
entries with @GOTOFF whih is EK_GPRel32BlockAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| eb38ebf15c326a5bb45ca9da6329cdf19ad6df95 |
|
24-Jan-2010 |
Mon P Wang <wangmp@apple.com> |
Improved widening loads by adding support for wider loads if
the alignment allows. Fixed a bug where we didn't use a
vector load/store for PR5626.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ad9c0a3d8bf625d169596547f893b9ec8b953e26 |
|
15-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c363094e04df621d41ca570eb2a7bf8826bb8c1a |
|
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0b10b91465e69c4ae3649115486e1eb56b8be878 |
|
08-Nov-2009 |
Nate Begeman <natebegeman@mac.com> |
x86 vector shuffle cleanup/fixes:
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b4997aeab74934ffa6fc0409afc4d8704245e372 |
|
07-Nov-2009 |
Kenneth Uildriks <kennethuil@gmail.com> |
Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f705adbe5ecd156de3f5a3017ddf4017e3890777 |
|
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Initial x86 support for BlockAddresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a1eaa3c52b75d4fe2bcd4f7c52e56c405ee91d3c |
|
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a second ValueType argument to isFPImmLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| eb2f969a4ddfb0bc8fdcb5bce3b52e53abff321d |
|
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a09008bf6ddb61910212c31db1d714182882681e |
|
19-Oct-2009 |
Nate Begeman <natebegeman@mac.com> |
Add support for matching shuffle patterns with palignr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 431f775bab2c1ca144e3c9c6b1e3c0767bfacc33 |
|
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix funky comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
|
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e220c4b3d97bbdc9f6e8cf040942514612349c41 |
|
18-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Add support for using the FLAGS result of or, xor, and and instructions
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
|
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 52600972832cb4ae8f4c63802f3764cbfbcb203d |
|
02-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
refactor select 'sched insertion' out to its own method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c69d74a5d41a6c5e92f9d947f2fa181f48626ca5 |
|
31-Aug-2009 |
Duncan Sands <baldrick@free.fr> |
Revert commit 80428. It completely broke exception
handling on x86-32 linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9b35a09e7e5b1aa26588e3852fe00a42b4f383ba |
|
29-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- Add target lowering methods to get the preferred format for the FDE and LSDA
encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
size. This is in line with how GCC does things. And it has the benefit of
working for Darwin in 64-bit mode now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b120ab4057fc66ce11ee1f108af9dbbeafa3fed9 |
|
19-Aug-2009 |
Eric Christopher <echristo@apple.com> |
Implement sse4.2 string/text processing instructions:
Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| af5663405834ca7cf4a847f2efa2d624ce99b1d8 |
|
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reapply r79127. It was fixed by d0k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f865ea85bd9d3e04aa795ee03cfc8db339f8c9b9 |
|
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 088880cb192fb6dd5b1bf85af62023c5ca3da38f |
|
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change allowsUnalignedMemoryAccesses to take type argument since some targets
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d6708eade079c30b0790789a00a8d737d84f52b7 |
|
15-Aug-2009 |
Dan Gohman <gohman@apple.com> |
On x86-64, for a varargs function, don't store the xmm registers to
the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b5e01724057e6eabc45da75df3037af4ad29248c |
|
06-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Better handle kernel code model. Also, generalize the things and fix one
subtle bug with small code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
|
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a9c1dd7820d0444802d42e5761e36c6e60e404d6 |
|
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 37b7387da90ffd42d28ad0f08fca00b684294b2c |
|
30-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch.
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 71c6753d03d1bb27d0cf997285c425d631e5807b |
|
29-Jul-2009 |
Eric Christopher <echristo@apple.com> |
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower
to ptest instruction plus setcc. Revamp ptest instruction. Add test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b8105651527670cb456eb46dd4346bacd3905361 |
|
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Copy ExpandInlineAsm to TargetLowering from TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 951bf7d74f12b6dacfb2691c90603916b9bfd93f |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
change a few methods to be static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 578efa920abd218ba75a0fb3c9b8398f4c0a774b |
|
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 874ae251c317788391f9c3f113957802d390a063 |
|
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4150d83abe90a5da4ddf86433b7bf4329acfa57c |
|
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.
Most targets will still produce a Flag-setting target-dependent
version when selection is done. X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted. All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly. The
same can be done on other targets.
The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8b944d39b356135676459152385f05c496951f6c |
|
28-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl $65536, 8(%rax)
=>
orb $1, 10(%rax)
Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 948e95a381bf6771639703643ef75e0115b35f53 |
|
23-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit
systems instead of attempting to promote them to a 64-bit SINT_TO_FP or
FP_TO_SINT. This is in preparation for removing the type legalization
code from LegalizeDAG: once type legalization is gone from LegalizeDAG,
it won't be able to handle the i64 operand/result correctly.
This isn't quite ideal, but I don't think any other operation for any
target ends up in this situation, so treating this case specially seems
reasonable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5a5ca1519e04310f585197c20e7ae584b7f2d11f |
|
29-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
Implement review feedback for vector shuffle work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9008ca6b6b4f638cfafccb593cbc5b1d3f5ab877 |
|
27-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 15684b29552393553524171bff1913e750f390f8 |
|
24-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b706d29f9c5ed3ed9acc82f7ab46205ba56b92dc |
|
24-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 094fad37b90946c91a09eb9270a0dbe800f49d87 |
|
08-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 97121ba2afb8d566ff1bf5c4e8fc5d4077940a7f |
|
08-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 044b5344c4a97b3c709a05b9c5f9296656477652 |
|
08-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 |
|
07-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 73f24c9f0d9afd1fd65d544f2b7b7b7c77fc2238 |
|
30-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bddc442a00c2216834499f10c12d023f1751104c |
|
26-Mar-2009 |
Bill Wendling <isanbard@gmail.com> |
Doxygen-ify comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2004eb6272d4787b9e08a83230fe022cbaf4deb0 |
|
23-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Correct some comments. Operand numbers start at 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2b9f4349086247c58ed0bcd17c7d11b14b14f52b |
|
12-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
improve comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3112581441cd22ac955b1af2d08effe3bab975da |
|
07-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Arithmetic instructions don't set EFLAGS bits OF and CF bits
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 076aee32e86bc4a0c096262b3261923f25220dc6 |
|
04-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 29582d1223d2cd851e136bfe39c508930c4b5592 |
|
04-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Revert r66004 for now; it's causing a variety of test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 12bbc52aa7ad84a944f14757f7f6d77b9fa3188f |
|
04-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
result from add, sub, inc, and dec instructions in simple cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b9a47b824f6c8ef3989a796018bf974c09cd243f |
|
23-Feb-2009 |
Nate Begeman <natebegeman@mac.com> |
Generate better code for v8i16 shuffles on SSE2
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
cleanups.
New tests that test the above.
Examples:
New:
_shuf2:
pextrw $7, %xmm0, %eax
punpcklqdq %xmm1, %xmm0
pshuflw $128, %xmm0, %xmm0
pinsrw $2, %eax, %xmm0
Old:
_shuf2:
pextrw $2, %xmm0, %eax
pextrw $7, %xmm0, %ecx
pinsrw $2, %ecx, %xmm0
pinsrw $3, %eax, %xmm0
movd %xmm1, %eax
pinsrw $4, %eax, %xmm0
ret
=========
New:
_shuf4:
punpcklqdq %xmm1, %xmm0
pshufb LCPI1_0, %xmm0
Old:
_shuf4:
pextrw $3, %xmm0, %eax
movsd %xmm1, %xmm0
pextrw $3, %xmm1, %ecx
pinsrw $4, %ecx, %xmm0
pinsrw $5, %eax, %xmm0
========
New:
_shuf1:
pushl %ebx
pushl %edi
pushl %esi
pextrw $1, %xmm0, %eax
rolw $8, %ax
movd %xmm0, %ecx
rolw $8, %cx
pextrw $5, %xmm0, %edx
pextrw $4, %xmm0, %esi
pextrw $3, %xmm0, %edi
pextrw $2, %xmm0, %ebx
movaps %xmm0, %xmm1
pinsrw $0, %ecx, %xmm1
pinsrw $1, %eax, %xmm1
rolw $8, %bx
pinsrw $2, %ebx, %xmm1
rolw $8, %di
pinsrw $3, %edi, %xmm1
rolw $8, %si
pinsrw $4, %esi, %xmm1
rolw $8, %dx
pinsrw $5, %edx, %xmm1
pextrw $7, %xmm0, %eax
rolw $8, %ax
movaps %xmm1, %xmm0
pinsrw $7, %eax, %xmm0
popl %esi
popl %edi
popl %ebx
ret
Old:
_shuf1:
subl $252, %esp
movaps %xmm0, (%esp)
movaps %xmm0, 16(%esp)
movaps %xmm0, 32(%esp)
movaps %xmm0, 48(%esp)
movaps %xmm0, 64(%esp)
movaps %xmm0, 80(%esp)
movaps %xmm0, 96(%esp)
movaps %xmm0, 224(%esp)
movaps %xmm0, 208(%esp)
movaps %xmm0, 192(%esp)
movaps %xmm0, 176(%esp)
movaps %xmm0, 160(%esp)
movaps %xmm0, 144(%esp)
movaps %xmm0, 128(%esp)
movaps %xmm0, 112(%esp)
movzbl 14(%esp), %eax
movd %eax, %xmm1
movzbl 22(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 42(%esp), %eax
movd %eax, %xmm1
movzbl 50(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm1, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 77(%esp), %eax
movd %eax, %xmm1
movzbl 84(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 104(%esp), %eax
movd %eax, %xmm1
punpcklbw %xmm1, %xmm0
punpcklbw %xmm2, %xmm0
movaps %xmm0, %xmm1
punpcklbw %xmm3, %xmm1
movzbl 127(%esp), %eax
movd %eax, %xmm0
movzbl 135(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 155(%esp), %eax
movd %eax, %xmm0
movzbl 163(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm0, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 188(%esp), %eax
movd %eax, %xmm0
movzbl 197(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 217(%esp), %eax
movd %eax, %xmm4
movzbl 225(%esp), %eax
movd %eax, %xmm0
punpcklbw %xmm4, %xmm0
punpcklbw %xmm2, %xmm0
punpcklbw %xmm3, %xmm0
punpcklbw %xmm1, %xmm0
addl $252, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
|
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| eacf2dc4bb64b5be2ab33339e81b526aa76adfbb |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Need this file too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ace1610df5fe22519d82cd7418a772e46ebd965b |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
DebugLoc propagation. 2/3 through file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9b9948507474acd3c5941ad7d33a37cb066803ad |
|
24-Jan-2009 |
Nate Begeman <natebegeman@mac.com> |
Fix an indent and a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8b8a6368437abea4e4adb9afab455727f2da6624 |
|
17-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Implement a special algorithm for converting uint_to_fp for i32 values on
X86. This code:
void f() {
uint32_t x;
float y = (float)x;
}
used to be:
movl %eax, -8(%ebp)
movl [2^52 double], -4(%ebp)
movsd -8(%ebp), %xmm0
subsd [2^52 double], %xmm0
cvtsd2ss %xmm0, %xmm0
Is now:
movsd [2^52 double], %xmm0
movsd %xmm0, %xmm1
movd %ecx, %xmm2
orps %xmm2, %xmm1
subsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm0
This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c13cf130c45c5675ea879e1c5454298dfbe5e02f |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make getWidenVectorType const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 83489bb7700c69b7a4a8da59365c42d3f5c8129b |
|
13-Jan-2009 |
Devang Patel <dpatel@apple.com> |
Use DebugInfo interface to lower dbg_* intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
|
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c7a37d4ff2ee8ffb93ba97e9393ff582f0e79a9a |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add instruction patterns and encodings for the x86 bt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| af9b952627d8fa10412b8cf7319d3e334446547f |
|
18-Dec-2008 |
Mon P Wang <wangmp@apple.com> |
Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d350e02e19e1b79c3fd6dc70ee3c01ab75c631c1 |
|
12-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
- Use patterns instead of creating completely new instruction matching patterns,
which are identical to the original patterns.
- Change the multiply with overflow so that we distinguish between signed and
unsigned multiplication. Currently, unsigned multiplication with overflow
isn't working!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ab55ebda1c2254f98b06e770bc2dae7d05a4a366 |
|
12-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Redo the arithmetic with overflow architecture. I was changing the semantics of
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.
Similar for SUB and MUL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 74c376529101acbe141a256d0bf23a44eb454c84 |
|
09-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Add sub/mul overflow intrinsics. This currently doesn't have a
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 61edeb5ed26d970cfc08ee71081d5095df4b59bb |
|
02-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Second stab at target-dependent lowering of everyone's favorite nodes: [SU]ADDO
- LowerXADDO lowers [SU]ADDO into an ADD with an implicit EFLAGS define. The
EFLAGS are fed into a SETCC node which has the conditional COND_O or COND_C,
depending on the type of ADDO requested.
- LowerBRCOND now recognizes if it's coming from a SETCC node with COND_O or
COND_C set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 41ea7e7eb3a6a269f2bfed0bdc191ea046d18e5e |
|
24-Nov-2008 |
Bill Wendling <isanbard@gmail.com> |
- Make lowering of "add with overflow" customizable by back-ends.
- Mark "add with overflow" as having a custom lowering for X86. Give it a null
lowering representation for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0c39719bfc7d0b3e61fbd55e1115184a1d5f6ae7 |
|
30-Oct-2008 |
Mon P Wang <wangmp@apple.com> |
Add initial support for vector widening. Logic is set to widen for X86.
One will only see an effect if legalizetype is not active. Will move
support to LegalizeType soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1c15bf58a3700d40a6a88ac0ce14a2c99f111483 |
|
21-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add an SSE2 algorithm for uint64->f64 conversion.
The same one Apple gcc uses, faster. Also gets the
extreme case in gcc.c-torture/execute/ieee/rbug.c
correct which we weren't before; this is not
sufficient to get the test to pass though, there
is another bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6520e20e4fb31f2e65e25c38b372b19d33a83df4 |
|
18-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| dd5b58ad7be78be90390074f0df138778af5c895 |
|
15-Oct-2008 |
Dan Gohman <gohman@apple.com> |
FastISel support for exception-handling constructs.
- Move the EH landing-pad code and adjust it so that it works
with FastISel as well as with SDISel.
- Add FastISel support for @llvm.eh.exception and
@llvm.eh.selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 880ae364ba4ed3d63542a2ef934980c70e8bb9d7 |
|
04-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Make atomic Swap work, 64-bit on x86-32.
Make it all work in non-pic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 48c1bc2ace6481d3272ab5c18e1f19352c563be8 |
|
02-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Handle some 64-bit atomics on x86-32, some of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6158d8492cc021bb47caee6d4755135ef1d855a4 |
|
01-Oct-2008 |
Bill Wendling <isanbard@gmail.com> |
Implement the -fno-builtin option in the front-end, not in the back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6f287b22d2e57600b4cd5dc209d0d869e7736c0b |
|
30-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 71d1bf55a27017fceef25554e02021a3bc47cdb4 |
|
30-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Remove misuse of ReplaceNodeResults for atomics with
valid types. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0b457f0c3a7e21b1fb9ac8b9f8e404e1312b6a60 |
|
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
|
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d57dd5f4e6740520820bc0fca42a540e31c27a73 |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Arrange for FastISel code to have access to the MachineModuleInfo
object. This will be needed to support debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bdd |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0586d91bb3e516d5826826522d9a90ed6ef74d86 |
|
10-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Add X86FastISel support for static allocas, and refences
to static allocas. As part of this change, refactor the
address mode code for laods and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bff66b0c6c8266a6f9ba6c9bd5d2541a4d4c6ec9 |
|
09-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Replace explicit pointer-size constants to TargetData query.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3df24e667f04a7003342b534310919abc9c87418 |
|
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Create HandlePHINodesInSuccessorBlocksFast, a version of
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b388eb82fb4a95e2f6d54163dfcf962b8032bae8 |
|
03-Sep-2008 |
Ted Kremenek <kremenek@apple.com> |
Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c3f44b0d636ff9a6d706ea9ac17ae77c8fa8aeff |
|
03-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bb466331e7e50d03497ce40ee344870236fd9c32 |
|
20-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify FastISel's constructor argument list, make the FastISel
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d9f3c480a7bc0969b08ace68af7dcde40f6caff1 |
|
19-Aug-2008 |
Dan Gohman <gohman@apple.com> |
The X86 target will soon have an implementation of createFastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 140be2dfb76928cb660b7de23f8310d76ca794b5 |
|
19-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add support for 8 and 16 bit forms of __sync
builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 30a0de94e7a5cbdcd277a93e543b0788efa78ddc |
|
17-Jul-2008 |
Nate Begeman <natebegeman@mac.com> |
SSE codegen for vsetcc nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
|
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 28873106309db515d58889a4c4fa3e0a92d1b60e |
|
25-Jun-2008 |
Mon P Wang <wangmp@apple.com> |
Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 507a58ac9b20ddcea2e56a014be26b8f8cc0ecb8 |
|
14-Jun-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
add missing atomic intrinsic from gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f26ffe987cf3643a7bd66bd9f97c34605ba7d08e |
|
29-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0ef8de30fa8dd317c8b45711fe144d39e51ecfa4 |
|
16-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix typos and comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f0df03134e698ea84e9cc1c28a853f83c02560d5 |
|
15-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 |
|
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c2616e43fd980505d3b29b92473d047f878f6708 |
|
12-May-2008 |
Nate Begeman <natebegeman@mac.com> |
Initial X86 codegen support for VSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ad4196b44ae714a6b95e238d9d96303df74b0429 |
|
12-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 9018e836fe4ef55a9bcf2cc02a6a3a4ef455115f |
|
10-May-2008 |
Dan Gohman <gohman@apple.com> |
For now, abort when an ISD::VAARG is encountered on x86-64, rather
than silently generate invalid code.
llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d880b97257c7f8ec4e94948874cb87c865d9f96f |
|
09-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle a few more cases of folding load i64 into xmm and zero top bits.
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7e2ff77ef05c23db6b9c82bc7a4110e170d7f94c |
|
08-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 63307c335aa08b0d6a75f81d64d79af7e90eb78b |
|
05-May-2008 |
Mon P Wang <wangmp@apple.com> |
Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
|
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1f13c686df75ddbbe15b208606ece4846d7479a8 |
|
28-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5e764233f398b6929b67701672a5e78fec20ce2e |
|
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 302cd54299f09bc9c8f600df4be142e687acc924 |
|
16-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Remove X86_64SRet; it isn't used anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 29e4bdbf27c5f03b12dd2bc41d9ccb0d5f3dfdf4 |
|
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4b5324ad2cbf774c9c6ed02ea0fcc864f2f5f885 |
|
12-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
This patch corrects the handling of byval arguments for tailcall
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).
Should fix the following problems:
Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).
Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
|
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7d8143f0ef35fccc98a624525b4517eb790e2d14 |
|
09-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Make isVectorClearMaskLegal's operand list const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 920c37afc5896201ec014041cbd270289baa25c0 |
|
21-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
remove Evan's "ugly hack" that sorta attempted to get
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4fe3073cfb5273a3655aef0c8d50c96882f26882 |
|
19-Mar-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Don't loose incoming argument registers. Fix documentation style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8e6da15e54125db38c0ae32f7a6b2273c792c588 |
|
10-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
copyfromreg/copytoreg instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
|
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| afb23f48a4f5f76b4a0fca870ae5a28c27dde028 |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
rename FP_SETRESULT -> FP_SET_ST0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6fa2f9c63688ff240d58c80bc0e433bb27a53c85 |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6fd599fa6916bd9438dbea7994cf2437bdf4ab8c |
|
05-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d19189e9905e14a4001a8ca6fc4effb6a3f88e45 |
|
05-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
64bit CAS on 32bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 26ed8697d4733f4ad588ef117ec4387560770ad0 |
|
01-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
all but CAS working on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 258bb1b8e8a6c1cb3be8cb8fd9366386563f06ce |
|
26-Feb-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Refactor according to Evan's and Anton's suggestions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 865c68188a72604a15c8b9b08df89d4775c7c764 |
|
26-Feb-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Change the lowering of arguments for tail call optimized
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| efec751a1b786724862ceff52748df94873a807e |
|
19-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 14d12caf1d2de9618818646d12b30d647a860817 |
|
11-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Enable SSE4 codegen and pattern matching.
Add some notes to the README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1a0248690aaa9f7baaf1247e5f65a1c0c9e3783c |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
with the real FLT_ROUNDS (defined in <float.h>).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
|
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0d9e976ad2c5479f3d67f8cb09a5908cfc29985c |
|
29-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
Status: This only works for direct calls, and only the caller side is done. Disabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ba2a0b960ea4c73d0f81557f63ae2ea126e08905 |
|
29-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Handle 'X' constraint in asm's better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 29286502628867b31872ead2f2527592480f0970 |
|
24-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Let each target decide byval alignment. For X86, it's 4-byte unless the aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3d66185ff8b276183fa8e9ce3d7ebb1d9ce88f74 |
|
18-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
make a method public
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 78631168d1179415c466620ec99ec626d4a35956 |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
make it more clear that this predicate only applies to scalar FP types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1956d1567671ef083efc19c001f5c1d121542aa6 |
|
16-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
introduce a isTypeInSSEReg predicate, which allows us to simplify
some code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| da68d30d24f3f25444793c6d8c3c5a614e523eaa |
|
15-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 66fac79b899904ddd82e5ee354a6d370d80230f6 |
|
15-Jan-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed
as well as PPC codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 86737665b81550fdb575f7d8cc5decc801a7813d |
|
05-Jan-2008 |
Gordon Henriksen <gordonhenriksen@mac.com> |
Refactoring the x86 and x86-64 calling convention implementations,
unifying the copied algorithms and saving over 500 LOC. There should
be no functionality change, but please test on your favorite x86
target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 18efe269b12624d74c0af6104e88864d6a932344 |
|
14-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implement ctlz and cttz with bsr and bsf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 27a6c7380fa4dfc8e1837a8dd67967d063b26544 |
|
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 45b22fa9f1f085d7971cce6db4f11b353e1646c6 |
|
16-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement codegen for flt_rounds on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| cc41586b9d79532172b37e1f44a9077da4b73fc9 |
|
09-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f1ba1cad387dc52f3c2c5afc665edf9caad00992 |
|
06-Nov-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3c3ddb3a856e44c603cb8cf8f52ff9c0f06ff14a |
|
29-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enable more fold (sext (load x)) -> (sext (truncate (sextload x)))
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2bd122c4d934a70e031dc0ca5171719bac66c2c9 |
|
26-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c85e1716f0e45e4c18a9ef2fbe431a51ac3a4252 |
|
11-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6d60cac029c5eda877a982cd6a0281380932c512 |
|
09-Oct-2007 |
Dan Gohman <gohman@apple.com> |
LowerIntegerDivOrRem no longer exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 525178cdbf00720ea8bce297a7d65b0cca0ab439 |
|
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e5f6204cd5d2306379bf8954e280ad35619a38b5 |
|
29-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enabling new condition code modeling scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 068317bfa37ec52ae25f3b2fa3194bea3e7c6027 |
|
28-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Refactor the memcpy lowering for the x86 target.
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b94fc1bcb204aeae98df0274ca9bb84e98f880f7 |
|
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a37c9f7506af622b9f29a35466b33c650c75e9f7 |
|
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
When both x/y and x%y are needed (x and y both scalar integer), compute
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0488db9b99fcfca407e859ef5cccf40dea23de16 |
|
25-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f1fc3a8fa6d4e81e30c08983d786c640acb2591c |
|
23-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Fix PR 1681. When X86 target uses +sse -sse2,
keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7d6ff3a25d9be6fae7ad95837ba8f1a8738947b6 |
|
17-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
X86ISD::TEST is dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7effac5475c9057dd1c384d33f41d518ff387207 |
|
14-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for functions with byval arguments on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1b5dcc34b701639f94008658a2042abc43b9b910 |
|
31-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Initial support for calling functions with byval arguments on x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 48884cd80b52be1528618f2e9b3425ac24e7b5ca |
|
25-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a2780e11ef0b757f0e5851bcf76c28c2f07dd379 |
|
15-Aug-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed
hard to catch bugs with retaddr lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 61e729e2e9517ab2d8887bab86fb377900fa1081 |
|
02-Aug-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b116fac90f9b54142ac511a30b4d45b54d3508ba |
|
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Trampoline codegen support for X86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d300622ebacde5bffb5b5e58142323e505df9dbe |
|
27-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Re-apply 40504, but with a fix for the segfault it caused in oggenc:
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3e22947d9acef08486c59349702cfb77ef734fbf |
|
27-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Reverting 40504 for now. It's breaking oggenc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d3283832aa4a4df96194157bc3e368c43569dde2 |
|
26-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
x86 target, replacing them with the new alignment attributes on memory
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
|
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2038252c6a36efd18cc0bef216fa2c5bb9236617 |
|
10-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
|
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2f9bb1a0a47622d959ec0cee25a7346c55066817 |
|
24-Apr-2007 |
Bill Wendling <isanbard@gmail.com> |
Support for the special case of a vector with the canonical form:
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b3a0417cad8b625acc3033bd5e24afb9ffd0b084 |
|
20-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 57fc00d5cf47343ba762493b8781ca0b14489c35 |
|
17-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| eb8c74ddf26a29bec68cd18454f6963e9ddca63e |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b445d0cbb9b299ba8ec7be2494e35c501b6d3a93 |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead target hooks, subsumed by isLegalAddressingMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c9addb74883fef318140272768422656a694341f |
|
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
|
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| fa4bce2b76c8557cfd0794beef86efe5fb0087fa |
|
21-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a8a155e77f6216d762f218bedd326c5c3bb08f99 |
|
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ae6421935bd3f2e48346fd16a21297ed1a28fd32 |
|
03-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2db39b865e689681d39948691e06531dc4f3356c |
|
28-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
remove fastcc (not fastcall) support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 54e3efde4636dade74f95ede039091bf52ca1585 |
|
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
add an accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 09c75a43722e2aa00df4e31af35d97a6f598c28c |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
pass the calling convention into Lower*CallTo, instead of using ad-hoc flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 3085e1511750b7d69bf5f1831696e0d178bdb5b1 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
factor a bunch of code out of LowerCCCCallTo into a new LowerCallResult
function. This function now uses GetRetValueLocs to determine *where*
the result values are located and concerns itself with *how* to pull the
values out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| cb18656734c374737f27c10750a3b532ac41ab26 |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
simplify result value lowering by splitting the selection of *where* to return
registers out from the logic of *how* to return them.
This changes X86-64 to mark EAX live out when returning a 32-bit value,
where before it marked RAX liveout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
|
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
|
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 73d6cf12adfd915897cce7e1ba9de00f962502d5 |
|
05-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- FCOPYSIGN custom lowering bug. Clear the sign bit of operand 0 first before
or'ing in the sign bit of operand 1.
- Tweaking: rather than left shift the sign bit, fp_extend operand 1 first
before taking its sign bit if its type is smaller than that of operand 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 68c47cba3589b2fc079bab0836d1ae6fc3a6278d |
|
05-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
With SSE2, expand FCOPYSIGN to a series of SSE bitwise operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0085a28d13f86b09ba0c83e8dce81de3ba15ca2d |
|
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use a different wrapper node for RIP-relative GV, etc.
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 8ca29326e19201075f6dc95781560ea9ad41ecec |
|
10-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Don't dag combine floating point select to max and min intrinsics. Those
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.
This fixes PR996.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6e56e2c602084bd7ab4af54e3c1a8700a9320f97 |
|
07-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 22aaf1d61c6a752d66f7ee10a7a5d99c7160e007 |
|
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
allow the address of a global to be used with the "i" constraint when in
-static mode. This implements PR882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f686d9b71f0aa99578dac9a4dd50b57ece6945fa |
|
27-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7fbe9723e32ff35c4ad765c88209ef9321475a1b |
|
20-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Implement branch analysis/xform hooks required by the branch folding pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 91897778690a7d683497ba3f4040ebf09345f08a |
|
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6458f1807d32e3625a192526c665a365f5886365 |
|
29-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
update comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f824868ed9d2cc756a797f6dbd67732f75e31cd6 |
|
21-Sep-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Adding codegeneration for StdCall & FastCall calling conventions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 734503be5965237e7eed978837ff280a9fadf403 |
|
11-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f76d180c9595d34641f4b5d2fbba2f2c175197d8 |
|
01-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll.
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| f4dff84c8614fc2106d821e4687c933d8d4b9420 |
|
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the inline asm 'A' constraint. This implements PR825 and
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 206ee9d86cd4e78176fad6bfa2b016023edf5df7 |
|
07-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| da08d2c39af6aceaa0230f699c4b53de0e97c2b9 |
|
24-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 32fe1035a708d16d67e632f21d8ec2d1b437a225 |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Switch X86 over to a call-selection model where the lowering code creates
the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 25caf63cd2befc2c4d18ce0316af853988b48224 |
|
23-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove PreprocessCCCArguments and PreprocessFastCCArguments now that
FORMAL_ARGUMENTS nodes include a token operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2d2970905cf745771d9c4f23293ca3de6659ab4f |
|
23-May-2006 |
Chris Lattner <sabre@nondot.org> |
Implement an annoying part of the Darwin/X86 abi: the callee of a struct
return argument pops the hidden struct pointer if present, not the caller.
For example, in this testcase:
struct X { int D, E, F, G; };
struct X bar() {
struct X a;
a.D = 0;
a.E = 1;
a.F = 2;
a.G = 3;
return a;
}
void foo(struct X *P) {
*P = bar();
}
We used to emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
addl $28, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
ret
This is correct on Linux/X86 but not Darwin/X86. With this patch, we now
emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
*** addl $24, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
*** ret $4
For the record, GCC emits (which is functionally equivalent to our new code):
_bar:
movl 4(%esp), %eax
movl $3, 12(%eax)
movl $2, 8(%eax)
movl $1, 4(%eax)
movl $0, (%eax)
ret $4
_foo:
pushl %esi
subl $40, %esp
movl 48(%esp), %esi
leal 16(%esp), %eax
movl %eax, (%esp)
call _bar
subl $4, %esp
movl 16(%esp), %eax
movl %eax, (%esi)
movl 20(%esp), %eax
movl %eax, 4(%esi)
movl 24(%esp), %eax
movl %eax, 8(%esi)
movl 28(%esp), %eax
movl %eax, 12(%esi)
addl $40, %esp
popl %esi
ret
This fixes SingleSource/Benchmarks/CoyoteBench/fftbench with LLC and the
JIT, and fixes the X86-backend portion of PR729. The CBE still needs to
be updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4ac8974d0220a382c8d0c4a4ae8e69c4e5864d56 |
|
17-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Should pass by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| eda65fa20ba99e520d7f171d5b536458eea6e9c7 |
|
27-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up formal argument lowering code. Prepare for vector pass by value work.
- Fixed vararg support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1bc7804e4c8747fd99b119e8f88686c9610c5d4e |
|
26-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0db9fe6775853d62632ad299dd734b6ba6c6b336 |
|
25-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Separate LowerOperation() into multiple functions, one per opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 017dcc6e556f3f89dd3e3881696084af694718ac |
|
21-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 39623daef67090025be5cd8af7d172fd1c9e6418 |
|
20-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added support to turn "vector clear elements", e.g. pand V, <-1, -1, 0, -1>
to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 533a0aa9ba8653e2a0219be442eebae02f371c88 |
|
19-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Commute vector_shuffle to match more movlhps, movlp{s|d} cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d953947d26da373b3b4e5ff66b60883fb78c0dd5 |
|
14-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Last few SSE3 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| d6d1cbd692dd519263e30d97d6c4c9e453b5c5d5 |
|
11-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added support for _mm_move_ss and _mm_move_sd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 5ced1d812e1de885b568ddfa6da008895d3f7ce7 |
|
07-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
- movlp{s|d} and movhp{s|d} support.
- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6be2c58c8c4d2b8dede9e3d6920a18f04164388b |
|
06-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for comi / ucomi intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1d5a8cca004c29d99526b3c327d948f8ab197c90 |
|
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 653159f4aac61a7ad796e406a4899d27ffe5a789 |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b067a1e7e68c4446d3512c25d3a5ac55c6dd76f8 |
|
31-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 506d3dfa90cfee6ab4736a6a2c892e9059a7864d |
|
30-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added some SSE2 128-bit packed integer ops.
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2064a2b47eb10ae9a63a8b9db19a8990c9cea7e4 |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
* Bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4fcb922c70b67bbd74ff77a9b831bd3699839b6d |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up / consoladate various shuffle masks.
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0038e598037f76c2dce8b55ebb5e9147fd786330 |
|
28-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Model unpack lower and interleave as vector_shuffle so we can lower the
intrinsics as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ffea91e522a8d969a3c0810ec231b1179137d575 |
|
26-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c60bd97b94261366800c2eb57e95ddd44092e6f8 |
|
25-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Build arbitrary vector with more than 2 distinct scalar elements with a
series of unpack and interleave ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| bc4832bc648f9cfb99a43e01852e0f2c7632f16c |
|
25-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for scalar to vector with zero extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 386031a06f06626d9d94927af754da6d44dcb5fb |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle BUILD_VECTOR with all zero elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 2c0dbd01d240f80e5517773d8e2f77924c69a6ec |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 14aed5e66b606ab3ba39e1effd2a0a17790d6f19 |
|
24-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Handle more shuffle cases with SHUFP* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ca6e8eafd2dfb13b89875405c54613b9cea1ca2e |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 0188ecba85c7139f237baa4ce5612fdfc83e1b84 |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 63d3300da1ec6403fbf11f62d6404c7f87bffdba |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| b9df0ca67b9a59c75685a72ee50b1b471aa9d1bf |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Some splat and shuffle support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 48090aa8145640c023563751a8a1e1bcc09125e5 |
|
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use movaps to store 128-bit vector integers.
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c4c6257c1a154279bf10e9498d46d6c1793dbaa7 |
|
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 020d2e8e7aa36692af13c1215fdd6248a6d9e950 |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a0ea0539e359f6d82218e5aa4cdf3b50b17d6fbd |
|
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 1efa40f6a4b561cf8f80fe018684236010645cd0 |
|
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
split register class handling from explicit physreg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4217ca8dc175f7268a4335c8406dedd901e8e631 |
|
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 7ccced634ae0ecdc1c4f599fd3abf188c367e231 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 / Darwin PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 551bf3f80058a026b6a128dffd5530019e1df1b9 |
|
17-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 368e18d56a87308045d341e85584597bfe7426e9 |
|
16-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| e3de85b447b0a94c82f147159a0c903ea47e0069 |
|
04-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
flag so it can be flagged to a FST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 223547ab3101f32252cb704a67bd757e00fdbd16 |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
- Use XORP* to implement fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 259e97cc725011a3c138563d421a4654b082a64c |
|
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
* Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ef6ffb17c71232af5962f9926b31508eb942cddc |
|
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added custom lowering of fabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 6dab05363f94b279a3877fd79d68649b865e10d9 |
|
30-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
conversions. SSE does not have instructions to handle these tasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| c6fd6cd65c88ef1f11da43c11be0152cb69013a7 |
|
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 87c890a9c2a8f9818772f3b9e359d301b246e3a4 |
|
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
adjust prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| ee625573b5b39b91441fc6ea23f3ba415abdc71f |
|
27-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 559806f575297866609c7bef0e5c1084dcdda9a5 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| acc398c195a697795bff3245943d104eb19192b9 |
|
25-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| a3195e86439896ecba9b3f2afce40919b20a987a |
|
12-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix sint_to_fp (fild*) support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 67f92a76497d1f50e0dd6279c81b45689bd463f5 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for MEMCPY and MEMSET.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|
| 4a46080fe0133c71b511805c63abfb158dcd56a5 |
|
11-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
SSE cmov support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| e3413160ca2fb42854b2a23be6b2114c1da2778c |
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09-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| d9558e0ba6ddcf2798cfb88cc56e5f1c8135eb0d |
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06-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
* Fast call support.
* FP cmp, setcc, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| d90eb7fb2435e2abedb4694edc44fa45642edbe9 |
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05-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
DAG based isel call support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| 38bcbaf23e8836c8f64e7fd66ebebc44a2b921a1 |
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23-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
More X86 floating point patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| 3a03ebb37747c2b3fd9b4f8b44f1124f53727894 |
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22-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| d5781fca4f8f98863560338d4f8d017389428119 |
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21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added support for X86 RET with an additional operand to specify number of
bytes to pop off stack.
* Added support for X86 SETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| b077b842b64af39c8e2e9aaad327b3be446790dd |
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21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added lowering hook for external weak global address. It inserts a load
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| 7226158d7e3986e55b58214a749aa4eabb3fb6d5 |
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20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added a hook to print out names of target specific DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| 898101c15fa11a896deb4e2fcb73b4727e1dcc1f |
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20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
X86 conditional branch support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| 7df96d66729d1f33934de7b52553e5f071686041 |
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17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
X86 lowers SELECT to a cmp / test followed by a conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| b873ff322c28ce097762355921100b677c71238d |
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20-Nov-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
The second patch of X86 support for read cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
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| dbdbf0ce2eef7b6585397121f56d3845e04866d1 |
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15-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch
contributed by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86ISelLowering.h
|