Cross Reference: /external/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

Lines Matching refs:RC
1091     const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1092     HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1144     const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1146     HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1205 /// Returns true if there are no caller-saved registers available in class RC.
1207       const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1219   for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1323     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1324     int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), S->Offset);
1335     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1336     int Off = MinOffset - RC->getSize();
1337     unsigned Align = std::min(RC->getAlignment(), getStackAlignment());
1340     int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), Off);
1473   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1481   unsigned TmpR1 = MRI.createVirtualRegister(RC);
1492   HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1513   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1520   unsigned TmpR1 = MRI.createVirtualRegister(RC);
1525   HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1558   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1560   unsigned Size = RC->getSize();
1561   unsigned NeedAlign = RC->getAlignment();
1611   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1613   unsigned Size = RC->getSize();
1614   unsigned NeedAlign = RC->getAlignment();
1660   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1663   unsigned NeedAlign = RC->getAlignment();
1697   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1700   unsigned NeedAlign = RC->getAlignment();
1811     for (auto *RC : SpillRCs) {
1812       if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
1814       unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
1815       unsigned S = RC->getSize(), A = RC->getAlignment();
1831       const TargetRegisterClass *RC) const {
1845   for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
1876     const TargetRegisterClass *RC;
1878     SlotInfo() : Map(), Size(0), RC(nullptr) {}
1950           const TargetRegisterClass *RC = nullptr;
1953             RC = getRegClass({DataOp.getReg(), DataOp.getSubReg()});
1956             RC = getRegClass({DataOp.getReg(), DataOp.getSubReg()});
1958           RC = getCommonRC(SI.RC, RC);
1959           if (RC == nullptr)
1962             SI.RC = RC;
2035       dbgs() << "  RC: ";
2036       if (P.second.RC != nullptr)
2037         dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2112         auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()});
2114         unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);