Lines Matching refs:Op2
688 MachineOperand &Op2 = MI->getOperand(2);
706 if (Op2.isImm()) {
708 .addImm(Op2.getImm());
709 } else if (Op2.isReg()) {
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
742 MachineOperand &Op2 = MI->getOperand(2);
743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
744 int64_t Sh64 = Op2.getImm();
866 MachineOperand &Op2 = MI->getOperand(2);
868 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
883 unsigned RS2 = getRegState(Op2);
889 // Op0 = S2_asl_i_p_or Op1, Op2, Op3
890 // means: Op0 = or (Op1, asl(Op2, Op3))
907 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
910 .addReg(Op2.getReg(), RS2, HiSR);
914 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
918 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
927 .addReg(Op2.getReg(), RS2, HiSR)
938 .addReg(Op2.getReg(), RS2, LoSR);
949 .addReg(Op2.getReg(), RS2, LoSR)