Lines Matching refs:v32i8
934 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
942 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
949 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
982 for (auto VT : { MVT::v32i8, MVT::v16i16 }) {
988 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1009 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1011 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1018 for (auto VT : { MVT::v32i8, MVT::v16i16 })
1031 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1039 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1046 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1047 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1049 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1103 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1116 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1118 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1119 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1144 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1161 MVT::v16i8, MVT::v16i16, MVT::v32i8, MVT::v16i32,
1348 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1387 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1446 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1463 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1481 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1487 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1514 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1821 return MVT::v32i8;
1948 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
7577 case MVT::v32i8: {
11575 /// instruction set for v32i8 shuffling..
11580 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
11581 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
11583 assert(Subtarget.hasAVX2() && "We can only lower v32i8 with AVX2!");
11588 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
11593 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1, V2,
11597 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
11603 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
11607 if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask,
11613 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
11619 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
11624 if (V2.isUndef() && is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
11625 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2, Mask,
11628 if (SDValue PSHUFB = lowerVectorShuffleWithPSHUFB(DL, MVT::v32i8, Mask, V1,
11635 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
11639 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
11702 case MVT::v32i8:
12301 case MVT::v32i8:
14172 In = DAG.getBitcast(MVT::v32i8, In);
14187 SDValue BV = DAG.getBuildVector(MVT::v32i8, DL, pshufbMask);
14188 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
16204 // v32i8
16205 assert(OpVT == MVT::v32i8 && "Unexpected operand type");
16292 assert(VT == MVT::v32i8 && "Unexpected extload type");
16315 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v32i8, Lo, Hi);
19309 // Lower v16i8/v32i8/v64i8 mul as sign-extension to v8i16/v16i16/v32i16
19311 if (VT == MVT::v16i8 || VT == MVT::v32i8 || VT == MVT::v64i8) {
19321 if (VT == MVT::v32i8 && !Subtarget.hasBWI())
19456 assert((VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget.hasInt256())) &&
19459 // Lower v16i8/v32i8 as extension to v8i16/v16i16 vector pairs, multiply,
19475 if (VT == MVT::v32i8) {
19810 (Subtarget.hasInt256() && VT == MVT::v32i8) ||
20228 (VT == MVT::v32i8 && Subtarget.hasInt256() && !Subtarget.hasXOP())) {
26742 (Subtarget.hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
26880 if (VT == MVT::v32i8 && !Subtarget.hasAVX2())
28406 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
28607 case MVT::v32i8:
31719 case MVT::v32i8: