Cross Reference: /external/llvm/utils/TableGen/SubtargetEmitter.cpp

Lines Matching defs:ProcModel
91   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
94                              const CodeGenProcModel &ProcModel);
96                           const CodeGenProcModel &ProcModel);
98                            const CodeGenProcModel &ProcModel);
99   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
367   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
369     if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
372     std::vector<Record*> FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
376     const std::string &Name = ProcModel.ItinsDef->getName();
386     std::vector<Record*> BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
420   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
427     if (!ProcModel.hasItineraries())
430     const std::string &Name = ProcModel.ItinsDef->getName();
433     assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
439       Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
600 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
602   char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
606      << ProcModel.ModelName << "ProcResources" << "[] = {\n"
609   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
610     Record *PRDef = ProcModel.ProcResourceDefs[i];
626           PRDef->getValueAsDef("Super"), ProcModel);
627         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
649   const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
662       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
667                     "defined for processor " + ProcModel.ModelName +
676   for (Record *WR : ProcModel.WriteResDefs) {
684                       ProcModel.ModelName);
689   // TODO: If ProcModel has a base model (previous generation processor),
692     PrintFatalError(ProcModel.ModelDef->getLoc(),
702                                           const CodeGenProcModel &ProcModel) {
714       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
719                     "defined for processor " + ProcModel.ModelName +
728   for (Record *RA : ProcModel.ReadAdvanceDefs) {
736                       ProcModel.ModelName);
741   // TODO: If ProcModel has a base model (previous generation processor),
744     PrintFatalError(ProcModel.ModelDef->getLoc(),
801 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
804   if (!ProcModel.hasInstrSchedModel())
831                                 TI->ProcIndices.end(), ProcModel.Index);
848                                 SC.ProcIndices.end(), ProcModel.Index);
860         if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
874       for (Record *I : ProcModel.ItinRWDefs) {
884         DEBUG(dbgs() << ProcModel.ModelName
896                                      ProcModel);
914           FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
931         ExpandProcResources(PRVec, Cycles, ProcModel);
936           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
962         FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
1258   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1259     GenSchedClassTables(ProcModel, SchedTables);