Lines Matching refs:Op2
262 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
268 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
286 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
717 SDValue Op1, SDValue Op2,
722 SDValue Ops[] = { Op1, Op2 };
4701 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) {
4705 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
4710 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
4721 if (N->OperandList[1] != Op2)
4722 N->OperandList[1].set(Op2);
4730 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) {
4731 SDValue Ops[] = { Op1, Op2, Op3 };
4736 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
4738 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
4743 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
4745 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
4815 SDValue Op2) {
4817 SDValue Ops[] = { Op1, Op2 };
4823 SDValue Op2, SDValue Op3) {
4825 SDValue Ops[] = { Op1, Op2, Op3 };
4873 SDValue Op1, SDValue Op2) {
4875 SDValue Ops[] = { Op1, Op2 };
4881 SDValue Op1, SDValue Op2,
4884 SDValue Ops[] = { Op1, Op2, Op3 };
4890 SDValue Op1, SDValue Op2,
4893 SDValue Ops[] = { Op1, Op2, Op3 };
5018 SDValue Op1, SDValue Op2) {
5020 SDValue Ops[] = { Op1, Op2 };
5026 SDValue Op1, SDValue Op2, SDValue Op3) {
5028 SDValue Ops[] = { Op1, Op2, Op3 };
5055 EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) {
5057 SDValue Ops[] = { Op1, Op2 };
5064 SDValue Op2, SDValue Op3) {
5066 SDValue Ops[] = { Op1, Op2, Op3 };
5081 SDValue Op1, SDValue Op2) {
5083 SDValue Ops[] = { Op1, Op2 };
5090 SDValue Op1, SDValue Op2, SDValue Op3) {
5092 SDValue Ops[] = { Op1, Op2, Op3 };