Lines Matching refs:BaseReg
92 unsigned DestReg, unsigned BaseReg,
99 (BaseReg != 0 && !isARMLowRegister(BaseReg));
111 assert(BaseReg == ARM::SP && "Unexpected!");
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
169 unsigned DestReg, unsigned BaseReg,
185 if (DestReg == BaseReg && BaseReg == ARM::SP) {
191 } else if (!isSub && BaseReg == ARM::SP) {
207 if (DestReg != BaseReg)
229 DestReg, BaseReg, NumBytes, true,
235 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
236 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
247 .addReg(BaseReg, RegState::Kill))
250 BaseReg = DestReg;
267 bool isKill = BaseReg != ARM::SP;
271 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
275 BaseReg = DestReg;
531 unsigned BaseReg, int64_t Offset) const {
540 bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);