Lines Matching refs:MVT
46 if (VT==MVT::i1) retval=3;
47 if (VT==MVT::i8) retval=3;
48 if (VT==MVT::i16) retval=2;
107 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
109 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
111 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
112 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
113 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
116 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
117 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
120 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
121 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
123 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
124 setTruncStoreAction(MVT::i128, MVT::i32, Expand);
125 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
126 setTruncStoreAction(MVT::i128, MVT::i8, Expand);
128 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
131 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
132 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
135 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
137 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
145 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
146 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
151 for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
153 MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
158 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
159 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
165 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
166 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
169 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
170 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
171 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
172 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
173 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
176 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
177 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
180 setOperationAction(ISD::SREM, MVT::i8, Expand);
181 setOperationAction(ISD::UREM, MVT::i8, Expand);
182 setOperationAction(ISD::SDIV, MVT::i8, Expand);
183 setOperationAction(ISD::UDIV, MVT::i8, Expand);
184 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
185 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
186 setOperationAction(ISD::SREM, MVT::i16, Expand);
187 setOperationAction(ISD::UREM, MVT::i16, Expand);
188 setOperationAction(ISD::SDIV, MVT::i16, Expand);
189 setOperationAction(ISD::UDIV, MVT::i16, Expand);
190 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
191 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
192 setOperationAction(ISD::SREM, MVT::i32, Expand);
193 setOperationAction(ISD::UREM, MVT::i32, Expand);
194 setOperationAction(ISD::SDIV, MVT::i32, Expand);
195 setOperationAction(ISD::UDIV, MVT::i32, Expand);
196 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
197 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
198 setOperationAction(ISD::SREM, MVT::i64, Expand);
199 setOperationAction(ISD::UREM, MVT::i64, Expand);
200 setOperationAction(ISD::SDIV, MVT::i64, Expand);
201 setOperationAction(ISD::UDIV, MVT::i64, Expand);
202 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
203 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
204 setOperationAction(ISD::SREM, MVT::i128, Expand);
205 setOperationAction(ISD::UREM, MVT::i128, Expand);
206 setOperationAction(ISD::SDIV, MVT::i128, Expand);
207 setOperationAction(ISD::UDIV, MVT::i128, Expand);
208 setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
209 setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
212 setOperationAction(ISD::FSIN , MVT::f64, Expand);
213 setOperationAction(ISD::FCOS , MVT::f64, Expand);
214 setOperationAction(ISD::FREM , MVT::f64, Expand);
215 setOperationAction(ISD::FSIN , MVT::f32, Expand);
216 setOperationAction(ISD::FCOS , MVT::f32, Expand);
217 setOperationAction(ISD::FREM , MVT::f32, Expand);
221 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
222 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
224 setOperationAction(ISD::FMA, MVT::f64, Expand);
225 setOperationAction(ISD::FMA, MVT::f32, Expand);
227 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
228 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
235 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
236 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
237 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
239 setOperationAction(ISD::ROTL, MVT::i32, Legal);
240 setOperationAction(ISD::ROTL, MVT::i16, Legal);
241 setOperationAction(ISD::ROTL, MVT::i8, Custom);
244 setOperationAction(ISD::SHL, MVT::i8, Custom);
245 setOperationAction(ISD::SRL, MVT::i8, Custom);
246 setOperationAction(ISD::SRA, MVT::i8, Custom);
249 setOperationAction(ISD::SHL, MVT::i64, Legal);
250 setOperationAction(ISD::SRL, MVT::i64, Legal);
251 setOperationAction(ISD::SRA, MVT::i64, Legal);
254 setOperationAction(ISD::MUL, MVT::i8, Custom);
255 setOperationAction(ISD::MUL, MVT::i32, Legal);
256 setOperationAction(ISD::MUL, MVT::i64, Legal);
260 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
261 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
262 setOperationAction(ISD::MULHU, MVT::i8, Expand);
263 setOperationAction(ISD::MULHS, MVT::i8, Expand);
264 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
265 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
266 setOperationAction(ISD::MULHU, MVT::i16, Expand);
267 setOperationAction(ISD::MULHS, MVT::i16, Expand);
268 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
269 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
270 setOperationAction(ISD::MULHU, MVT::i32, Expand);
271 setOperationAction(ISD::MULHS, MVT::i32, Expand);
272 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
273 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
274 setOperationAction(ISD::MULHU, MVT::i64, Expand);
275 setOperationAction(ISD::MULHS, MVT::i64, Expand);
278 setOperationAction(ISD::ADD, MVT::i8, Custom);
279 setOperationAction(ISD::ADD, MVT::i64, Legal);
280 setOperationAction(ISD::SUB, MVT::i8, Custom);
281 setOperationAction(ISD::SUB, MVT::i64, Legal);
285 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
286 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
288 setOperationAction(ISD::CTPOP, MVT::i8, Custom);
289 setOperationAction(ISD::CTPOP, MVT::i16, Custom);
290 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
291 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
292 setOperationAction(ISD::CTPOP, MVT::i128, Expand);
294 setOperationAction(ISD::CTTZ , MVT::i8, Expand);
295 setOperationAction(ISD::CTTZ , MVT::i16, Expand);
296 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
297 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
298 setOperationAction(ISD::CTTZ , MVT::i128, Expand);
300 setOperationAction(ISD::CTLZ , MVT::i8, Promote);
301 setOperationAction(ISD::CTLZ , MVT::i16, Promote);
302 setOperationAction(ISD::CTLZ , MVT::i32, Legal);
303 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
304 setOperationAction(ISD::CTLZ , MVT::i128, Expand);
308 setOperationAction(ISD::SELECT, MVT::i8, Legal);
309 setOperationAction(ISD::SELECT, MVT::i16, Legal);
310 setOperationAction(ISD::SELECT, MVT::i32, Legal);
311 setOperationAction(ISD::SELECT, MVT::i64, Legal);
313 setOperationAction(ISD::SETCC, MVT::i8, Legal);
314 setOperationAction(ISD::SETCC, MVT::i16, Legal);
315 setOperationAction(ISD::SETCC, MVT::i32, Legal);
316 setOperationAction(ISD::SETCC, MVT::i64, Legal);
317 setOperationAction(ISD::SETCC, MVT::f64, Custom);
320 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
323 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom);
325 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
326 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
327 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
328 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
331 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
333 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
334 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
335 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
336 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
339 setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
342 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
343 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
344 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
345 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
346 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
347 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
349 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
351 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
352 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
353 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
354 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
361 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
363 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
371 setOperationAction(ISD::VASTART , MVT::Other, Custom);
374 setOperationAction(ISD::VAARG , MVT::Other, Expand);
375 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
376 setOperationAction(ISD::VAEND , MVT::Other, Expand);
377 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
378 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
379 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
383 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
384 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
387 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
390 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
394 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
395 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
396 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
397 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
398 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
399 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
401 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
402 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
403 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
437 setOperationAction(ISD::AND, MVT::v16i8, Custom);
438 setOperationAction(ISD::OR, MVT::v16i8, Custom);
439 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
440 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
442 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
507 MVT::SimpleValueType retval;
510 case MVT::i1:
511 case MVT::i8:
512 retval = MVT::i8; break;
513 case MVT::i16:
514 retval = MVT::i16; break;
515 case MVT::i32:
517 retval = MVT::i32;
538 emitted, e.g. for MVT::f32 extending load to MVT::f64:
593 rotate = DAG.getConstant(rotamt, MVT::i16);
611 rotate = DAG.getConstant(rotamt, MVT::i16);
659 SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr,
670 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::i128,
686 SDValue offset = DAG.getNode(ISD::AND, dl, MVT::i32,
687 basePtr, DAG.getConstant( 0xf, MVT::i32 ) );
690 SDValue ones = DAG.getConstant(-1, MVT::v4i32 );
691 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
693 SDValue high = DAG.getLoad(MVT::i128, dl, the_chain,
700 the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1),
706 high = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, high,
707 DAG.getNode(ISD::SUB, dl, MVT::i32,
708 DAG.getConstant( 16, MVT::i32),
714 low = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, low, offset );
718 DAG.getNode(ISD::OR, dl, MVT::i128, low, high));
739 SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
891 MVT::v4i32, insertEltOp));
905 SDValue offset = DAG.getNode(ISD::AND, dl, MVT::i32,
907 DAG.getConstant(0xf, MVT::i32));
909 SDValue offset_compl = DAG.getNode(ISD::SUB, dl, MVT::i32,
910 DAG.getConstant( 16, MVT::i32),
913 SDValue surplus = DAG.getNode(ISD::SUB, dl, MVT::i32,
914 DAG.getConstant( 16, MVT::i32),
916 MVT::i32));
918 SDValue ones = DAG.getConstant(-1, MVT::v4i32);
919 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
930 lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, ones, surplus);
931 lowmask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask,
933 Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value);
934 Value = DAG.getNode(ISD::AND, dl, MVT::i128, Value, lowmask);
939 Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value);
942 himask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask,
944 lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, lowmask,
949 SDValue hi = DAG.getLoad(MVT::i128, dl, the_chain,
954 the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1),
957 low = DAG.getNode(ISD::AND, dl, MVT::i128,
958 DAG.getNode( ISD::BITCAST, dl, MVT::i128, low),
959 DAG.getNode( ISD::XOR, dl, MVT::i128, lowmask, ones));
960 hi = DAG.getNode(ISD::AND, dl, MVT::i128,
961 DAG.getNode( ISD::BITCAST, dl, MVT::i128, hi),
962 DAG.getNode( ISD::XOR, dl, MVT::i128, himask, ones));
966 SDValue rlow = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, Value, offset);
967 rlow = DAG.getNode(ISD::AND, dl, MVT::i128, rlow, lowmask);
968 SDValue rhi = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, Value,
973 rlow = DAG.getNode(ISD::OR, dl, MVT::i128,
974 DAG.getNode(ISD::BITCAST, dl, MVT::i128, low),
975 DAG.getNode(ISD::BITCAST, dl, MVT::i128, rlow));
976 rhi = DAG.getNode(ISD::OR, dl, MVT::i128,
977 DAG.getNode(ISD::BITCAST, dl, MVT::i128, hi),
978 DAG.getNode(ISD::BITCAST, dl, MVT::i128, rhi));
988 result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(0),
1090 if (VT == MVT::f64) {
1097 SDValue T = DAG.getConstant(dbits, MVT::i64);
1098 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
1100 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Tvec));
1146 case MVT::i8:
1149 case MVT::i16:
1152 case MVT::i32:
1155 case MVT::i64:
1158 case MVT::i128:
1161 case MVT::f32:
1164 case MVT::f64:
1167 case MVT::v2f64:
1168 case MVT::v4f32:
1169 case MVT::v2i64:
1170 case MVT::v4i32:
1171 case MVT::v8i16:
1172 case MVT::v16i8:
1226 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
1236 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1254 return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
1288 SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
1311 case MVT::i8:
1312 case MVT::i16:
1313 case MVT::i32:
1314 case MVT::i64:
1315 case MVT::i128:
1316 case MVT::f32:
1317 case MVT::f64:
1318 case MVT::v2i64:
1319 case MVT::v2f64:
1320 case MVT::v4f32:
1321 case MVT::v4i32:
1322 case MVT::v8i16:
1323 case MVT::v16i8:
1347 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1420 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Glue),
1485 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1487 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
1524 if (ValueType == MVT::i64) {
1546 if (ValueType == MVT::i64) {
1569 if (ValueType == MVT::i64) {
1595 if (ValueType == MVT::i16
1599 else if (ValueType == MVT::i8
1614 if ((ValueType == MVT::i32
1616 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1626 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
1635 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
1670 case MVT::v4f32: {
1675 SDValue T = DAG.getConstant(Value32, MVT::i32);
1676 return DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,
1677 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
1680 case MVT::v2f64: {
1685 SDValue T = DAG.getConstant(f64val, MVT::i64);
1686 return DAG.getNode(ISD::BITCAST, dl, MVT::v2f64,
1687 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1690 case MVT::v16i8: {
1695 Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
1697 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
1699 case MVT::v8i16: {
1707 case MVT::v4i32: {
1711 case MVT::v2i64: {
1729 SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
1731 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1746 SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
1747 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
1758 SDValue LO32C = DAG.getConstant(lower, MVT::i32);
1760 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1766 SDValue HI32C = DAG.getConstant(upper, MVT::i32);
1768 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1802 ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
1806 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1849 if (EltVT == MVT::i8) {
1851 maskVT = MVT::v16i8;
1852 } else if (EltVT == MVT::i16) {
1854 maskVT = MVT::v8i16;
1855 } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
1857 maskVT = MVT::v4i32;
1858 } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
1860 maskVT = MVT::v2i64;
1913 DAG.getConstant(V2EltOffset, MVT::i32));
1925 V1, DAG.getConstant(rotamt, MVT::i16));
1936 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
1938 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
1961 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
1962 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
1963 case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
1964 case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
1965 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1966 case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
1979 case MVT::i8:
1980 case MVT::i16:
1981 case MVT::i32:
1982 case MVT::i64:
1983 case MVT::f32:
1984 case MVT::f64:
2004 if (VT == MVT::i8 && EltNo >= 16)
2006 else if (VT == MVT::i16 && EltNo >= 8)
2008 else if (VT == MVT::i32 && EltNo >= 4)
2010 else if (VT == MVT::i64 && EltNo >= 2)
2013 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
2025 case MVT::i8: {
2029 case MVT::i16: {
2033 case MVT::i32:
2034 case MVT::f32: {
2038 case MVT::i64:
2039 case MVT::f64: {
2073 ShufMask[i] = DAG.getConstant(bits, MVT::i32);
2077 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2093 if (Elt.getValueType() != MVT::i32)
2094 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
2104 Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
2105 DAG.getConstant(scaleShift, MVT::i32));
2119 case MVT::i8: {
2120 SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
2121 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2125 case MVT::i16: {
2126 SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
2127 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2131 case MVT::i32:
2132 case MVT::f32: {
2133 SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
2134 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2138 case MVT::i64:
2139 case MVT::f64: {
2140 SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
2141 SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
2142 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2186 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ShufMask));
2198 assert(Op.getValueType() == MVT::i8);
2208 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2209 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2210 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2211 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2219 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2220 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2221 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2222 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2229 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2239 DAG.getNode(ISD::OR, dl, MVT::i16, N0,
2240 DAG.getNode(ISD::SHL, dl, MVT::i16,
2241 N0, DAG.getConstant(8, MVT::i32)));
2244 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2245 DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
2252 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2262 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2263 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2269 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2278 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2279 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2284 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2285 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2286 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2287 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2330 SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
2359 case MVT::i8: {
2361 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2366 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
2369 case MVT::i16: {
2376 SDValue Elt0 = DAG.getConstant(0, MVT::i16);
2377 SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
2378 SDValue Shift1 = DAG.getConstant(8, MVT::i32);
2386 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
2391 SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
2393 return DAG.getNode(ISD::AND, dl, MVT::i16,
2394 DAG.getNode(ISD::ADD, dl, MVT::i16,
2395 DAG.getNode(ISD::SRL, dl, MVT::i16,
2401 case MVT::i32: {
2409 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2410 SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
2411 SDValue Shift1 = DAG.getConstant(16, MVT::i32);
2412 SDValue Shift2 = DAG.getConstant(8, MVT::i32);
2420 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
2426 DAG.getNode(ISD::SRL, dl, MVT::i32,
2427 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
2431 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
2432 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
2438 DAG.getNode(ISD::SRL, dl, MVT::i32,
2439 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
2442 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
2443 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
2445 return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
2448 case MVT::i64:
2466 if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
2467 || OpVT == MVT::i64) {
2492 if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
2493 || Op0VT == MVT::i64) {
2509 This handles MVT::f64 (double floating point) condition lowering
2520 assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
2524 EVT IntVT(MVT::i64);
2530 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2532 i64lhs, DAG.getConstant(32, MVT::i32)));
2534 DAG.getNode(ISD::AND, dl, MVT::i32,
2535 lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
2537 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
2554 DAG.getConstant(0x7ff00000, MVT::i32),
2558 DAG.getConstant(0, MVT::i32),
2564 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2566 i64rhs, DAG.getConstant(32, MVT::i32)));
2573 lhsHi32, DAG.getConstant(31, MVT::i32));
2580 rhsHi32, DAG.getConstant(31, MVT::i32));
2618 lhs, DAG.getConstantFP(0.0, MVT::f64),
2621 rhs, DAG.getConstantFP(0.0, MVT::f64),
2675 MVT simpleVT = VT.getSimpleVT();
2684 if (Op0VT == MVT::i128 && simpleVT == MVT::i64) {
2689 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2690 DAG.getConstant(maskHigh, MVT::i32),
2691 DAG.getConstant(maskLow, MVT::i32),
2692 DAG.getConstant(maskHigh, MVT::i32),
2693 DAG.getConstant(maskLow, MVT::i32));
2719 MVT OpVT = Op.getValueType().getSimpleVT();
2723 MVT Op0VT = Op0.getValueType().getSimpleVT();
2726 if (Op0VT == MVT::i8 || Op0VT == MVT::i16) {
2727 Op0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, Op0);
2728 Op0VT = MVT::i32;
2733 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2739 unsigned mask2 = Op0VT == MVT::i64 ? 0x00010203 : 0x10101010; // byte 8 - 11
2740 unsigned mask3 = Op0VT == MVT::i64 ? 0x04050607 : 0x00010203; // byte 12 - 15
2741 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2742 DAG.getConstant(mask1, MVT::i32),
2743 DAG.getConstant(mask1, MVT::i32),
2744 DAG.getConstant(mask2, MVT::i32),
2745 DAG.getConstant(mask3, MVT::i32));
2749 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
2754 DAG.getConstant(31, MVT::i32));
2761 MVT::i32)), 0);
2766 return DAG.getNode(ISD::BITCAST, dl, MVT::i128, extShuffle);
2814 if (VT == MVT::i8)
2847 if (VT == MVT::i8)
3144 if (VT == MVT::i64)
3148 if (VT == MVT::f32)
3150 else if (VT == MVT::f64)
3204 if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
3205 VT = MVT::i32;