Cross Reference: /external/valgrind/VEX/priv/host_s390

Lines Matching defs:r11
951          HReg r10, r11, h1;
957          /* We use non-virtual registers r10 and r11 as pair */
959          r11  = make_gpr(11);
961          /* Move 1st operand into r11 and */
962          addInstr(env, s390_insn_move(8, r11, h1));
965          addInstr(env, s390_insn_divs(8, r10, r11, op2));
967          /* The result is in registers r10 (remainder) and r11 (quotient).
974          addInstr(env, s390_insn_move(8, *dst_lo, r11));
982             HReg r10, r11, h1;
990             /* We use non-virtual registers r10 and r11 as pair */
992             r11  = make_gpr(11);
994             /* Move the first operand to r11 */
995             addInstr(env, s390_insn_move(8, r11, h1));
998             addInstr(env, s390_insn_mul(8, r10, r11, op2, is_signed_multiply));
1000             /* The result is in registers r10 and r11. Assign to two virtual regs
1005             addInstr(env, s390_insn_move(8, *dst_lo, r11));
1010          HReg r10, r11, hi, lo;
1016          /* We use non-virtual registers r10 and r11 as pair */
1018          r11  = make_gpr(11);
1021             the low 64 bits into r11. */
1023          addInstr(env, s390_insn_move(8, r11, lo));
1026          addInstr(env, s390_insn_div(8, r10, r11, op2, is_signed_divide));
1028          /* The result is in registers r10 (remainder) and r11 (quotient).
1035          addInstr(env, s390_insn_move(8, *dst_lo, r11));
1139             HReg r10, r11;
1147             /* We use non-virtual registers r10 and r11 as pair */
1149             r11  = make_gpr(11);
1151             /* Move the first operand to r11 */
1152             addInstr(env, s390_insn_move(arg_size, r11, h1));
1155             addInstr(env, s390_insn_mul(arg_size, r10, r11, op2, is_signed_multiply));
1157             /* The result is in registers r10 and r11. Combine them into a SIZE-bit
1164             addInstr(env, s390_insn_alu(size, S390_ALU_AND, r11, value));
1165             opnd = s390_opnd_reg(r11);
1179             HReg r10, r11;
1184             /* We use non-virtual registers r10 and r11 as pair */
1186             r11  = make_gpr(11);
1189                the low 32 bits into r11. */
1191             addInstr(env, s390_insn_move(8, r11, h1));
1196             addInstr(env, s390_insn_div(4, r10, r11, op2, is_signed_divide));
1198             /* The result is in registers r10 (remainder) and r11 (quotient).
1207             addInstr(env, s390_insn_alu(8, S390_ALU_AND, r11, value));
1208             opnd = s390_opnd_reg(r11);
1777          HReg r10, r11;
1781             left-most zero bits) will be in r10. The value in r11 is unspecified
1784          r11  = make_gpr(11);
1786          addInstr(env, s390_insn_clz(8, r10, r11, opnd));
3874          HReg r8, r9, r10, r11, r1;
3889          /* Use non-virtual registers r10 and r11 as pair for op3
3892          r11 = make_gpr(11);
3894          addInstr(env, s390_insn_move(8, r11, op3_low));
3900             addInstr(env, s390_insn_cdas(4, r8, r9, op2, r10, r11,
3903             addInstr(env, s390_insn_cdas(8, r8, r9, op2, r10, r11,
3909          addInstr(env, s390_insn_move(8, op3_low,  r11));