Searched defs:RC1 (Results 1 - 3 of 3) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp159 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
268 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, argument
272 // If RC1[i] is "bottom", it cannot be proven equal to RC2[i].
273 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0)
278 if (RC1[B1+i] != RC2[B2+i])
H A DHexagonGenInsert.cpp316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); local
317 uint16_t W1 = RC1.width(), W2 = RC2.width();
319 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i];
334 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); local
336 uint16_t W1 = RC1.width(), W2 = RC2.width();
350 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2];
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1873 CodeGenRegisterClass *RC1 = RC; local
1875 if (RC1 == RC2)
1878 // Compute the set intersection of RC1 and RC2.
1879 const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
1890 // If RC1 and RC2 have different spill sizes or alignments, use the
1891 // larger size for sub-classing. If they are equal, prefer RC1.
1892 if (RC2->SpillSize > RC1->SpillSize ||
1893 (RC2->SpillSize == RC1->SpillSize &&
1894 RC2->SpillAlignment > RC1->SpillAlignment))
1895 std::swap(RC1, RC
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