Searched defs:CmpInstr (Results 1 - 6 of 6) sorted by relevance
/external/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.cpp | 286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, 293 // Get ready to iterate backward from CmpInstr. 294 MachineBasicBlock::iterator I = CmpInstr, E = MI, 295 B = CmpInstr.getParent()->begin(); 297 // Early exit if CmpInstr is at the beginning of the BB. 309 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) { 313 if (CmpInstr.getOpcode() == Lanai::SFSUB_F_RI_LO) 331 // Check whether CmpInstr can be made redundant by the current instruction. 332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 355 I = CmpInstr; 285 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 612 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, argument
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 1173 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 878 /// 1. Convert CmpInstr into an unconditional version. 879 /// 2. Remove CmpInstr if above there is an instruction producing a needed 883 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, 885 assert(CmpInstr.getParent()); 889 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); 891 if (CmpInstr.definesRegister(AArch64::WZR) || 892 CmpInstr.definesRegister(AArch64::XZR)) { 893 CmpInstr.eraseFromParent(); 896 unsigned Opc = CmpInstr.getOpcode(); 897 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); 882 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument 1074 canInstrSubstituteCmpInstr(MachineInstr *MI, MachineInstr *CmpInstr, const TargetRegisterInfo *TRI) argument 1118 substituteCmpToZero( MachineInstr &CmpInstr, unsigned SrcReg, const MachineRegisterInfo *MRI) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 2392 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, 2405 if (UI->getParent() != CmpInstr.getParent()) 2418 // Get ready to iterate backward from CmpInstr. 2419 MachineBasicBlock::iterator I = CmpInstr, E = MI, 2420 B = CmpInstr.getParent()->begin(); 2422 // Early exit if CmpInstr is at the beginning of the BB. 2433 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) { 2438 if (CmpInstr.getOpcode() == ARM::CMPri || 2439 CmpInstr.getOpcode() == ARM::t2CMPri) 2458 // Check whether CmpInstr ca 2391 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 5044 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, argument 5050 switch (CmpInstr.getOpcode()) { 5067 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg())) 5070 switch (CmpInstr.getOpcode()) { 5088 CmpInstr.setDesc(get(NewOpcode)); 5089 CmpInstr.RemoveOperand(0); 5101 // CmpInstr is the first instruction of the BB. 5102 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 5105 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 5107 if (IsCmpZero && MI->getParent() != CmpInstr [all...] |
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