Searched defs:Defs (Results 26 - 42 of 42) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DLiveDebugVariables.cpp666 SmallVector<std::pair<SlotIndex, unsigned>, 16> Defs; local
671 Defs.push_back(std::make_pair(I.start(), I.value()));
674 for (unsigned i = 0; i != Defs.size(); ++i) {
675 SlotIndex Idx = Defs[i].first;
676 unsigned LocNo = Defs[i].second;
695 addDefsFromCopies(LI, LocNo, Kills, Defs, MRI, LIS);
H A DMachineLICM.cpp1244 SmallVector<unsigned, 2> Defs; local
1256 Defs.push_back(i);
1260 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1261 unsigned Idx = Defs[i];
1269 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1274 for (unsigned Idx : Defs) {
H A DBranchFolding.cpp1668 SmallSet<unsigned,4> &Defs) {
1689 addRegAndItsAliases(Reg, TRI, Defs);
1753 addRegAndItsAliases(Reg, TRI, Defs);
1782 SmallSet<unsigned, 4> Uses, Defs;
1784 findHoistingInsertPosAndDeps(MBB, TII, TRI, Uses, Defs);
1836 if (Defs.count(Reg) && !MO.isDead()) {
1852 if (Defs.count(Reg)) {
1664 findHoistingInsertPosAndDeps(MachineBasicBlock *MBB, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, SmallSet<unsigned,4> &Uses, SmallSet<unsigned,4> &Defs) argument
H A DIfConversion.cpp1490 SmallVector<unsigned, 4> Defs; local
1499 Defs.push_back(Reg);
1509 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1510 unsigned Reg = Defs[i];
H A DTwoAddressInstructionPass.cpp869 SmallSet<unsigned, 2> Defs; local
877 Defs.insert(MOReg);
891 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
892 Defs.insert(End->getOperand(0).getReg());
921 if (!MO.isDead() && Defs.count(MOReg))
927 if (Defs.count(MOReg))
1047 SmallSet<unsigned, 2> Defs; local
1065 Defs.insert(MOReg);
1093 if (Defs.count(MOReg))
1117 Defs
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/external/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp844 unsigned Defs = Mask; local
848 if (!(Defs & (1 << RegNo)))
853 Defs &= ~(1 << RegNo);
855 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
858 while (Kills && Defs) {
860 unsigned DReg = countTrailingZeros(Defs);
865 Defs &= ~(1 << DReg);
890 while(Defs) {
891 unsigned DReg = countTrailingZeros(Defs);
895 Defs
1634 std::bitset<8> Defs; local
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DBranchFolding.cpp1435 SmallSet<unsigned,4> &Defs) {
1516 Defs.insert(Reg);
1518 Defs.insert(*AS);
1547 SmallSet<unsigned, 4> Uses, Defs;
1549 findHoistingInsertPosAndDeps(MBB, TII, TRI, Uses, Defs);
1597 if (Defs.count(Reg) && !MO.isDead()) {
1613 if (Defs.count(Reg)) {
1431 findHoistingInsertPosAndDeps(MachineBasicBlock *MBB, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, SmallSet<unsigned,4> &Uses, SmallSet<unsigned,4> &Defs) argument
H A DLiveDebugVariables.cpp624 SmallVector<std::pair<SlotIndex, unsigned>, 16> Defs; local
629 Defs.push_back(std::make_pair(I.start(), I.value()));
632 for (unsigned i = 0; i != Defs.size(); ++i) {
633 SlotIndex Idx = Defs[i].first;
634 unsigned LocNo = Defs[i].second;
643 addDefsFromCopies(LI, LocNo, Kills, Defs, MRI, LIS);
H A DIfConversion.cpp956 /// InitPredRedefs / UpdatePredRedefs - Defs by predicated instructions are
975 SmallVector<unsigned, 4> Defs; local
984 Defs.push_back(Reg);
991 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
992 unsigned Reg = Defs[i];
/external/llvm/include/llvm/TableGen/
H A DRecord.h1515 RecordMap Classes, Defs; member in class:llvm::RecordKeeper
1519 const RecordMap &getDefs() const { return Defs; }
1526 auto I = Defs.find(Name);
1527 return I == Defs.end() ? nullptr : I->second.get();
1536 bool Ins = Defs.insert(std::make_pair(R->getName(),
/external/llvm/lib/TableGen/
H A DRecord.cpp1783 std::vector<Record*> Defs; local
1786 Defs.push_back(DI->getDef());
1791 return Defs;
1892 errs() << "Defs:\n";
1905 OS << "------------- Defs -----------------\n";
1917 std::vector<Record*> Defs; local
1920 Defs.push_back(D.second.get());
1922 return Defs;
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp259 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
428 SetVector<MachineBasicBlock*> Defs; local
429 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
431 for (MachineBasicBlock *D : Defs)
439 if (Defs.count(B))
459 Defs.insert(DefI->getParent());
479 if (Dominate(Defs, BB))
789 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
792 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, argument
795 // "Defs" an
977 ReferenceMap Uses, Defs; local
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H A DRDFGraph.cpp988 // Pop all defs from this block from the definition stack. Defs that were
1006 NodeList Defs = IA.Addr->members_if(IsDef, *this); local
1024 for (NodeAddr<DefNode*> DA : Defs) {
1309 RegisterSet Defs;
1316 Defs.insert(RA.Addr->getRegRef());
1339 PhiM[DBA.Id].insert(Defs.begin(), Defs.end());
1500 RegisterSet Defs; local
1510 if (std::any_of(Defs.begin(), Defs
1538 RegisterSet Defs; local
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H A DHexagonInstrInfo.cpp178 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
179 Defs.clear();
196 Defs.push_back(MO.getReg());
177 parseOperands(const MachineInstr *MI, SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) argument
/external/spirv-llvm/lib/SPIRV/
H A DSPIRVWriter.cpp1389 std::vector<Function *> Decls, Defs; local
1399 Defs.push_back(I);
1403 for (auto I:Defs)
/external/swiftshader/third_party/LLVM/lib/TableGen/
H A DRecord.cpp1843 std::vector<Record*> Defs; local
1846 Defs.push_back(DI->getDef());
1852 return Defs;
1974 errs() << "Defs:\n";
1993 OS << "------------- Defs -----------------\n";
1994 const std::map<std::string, Record*> &Defs = RK.getDefs(); local
1995 for (std::map<std::string, Record*>::const_iterator I = Defs.begin(),
1996 E = Defs.end(); I != E; ++I)
2011 std::vector<Record*> Defs; local
2015 Defs
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/external/clang/utils/TableGen/
H A DNeonEmitter.cpp504 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
506 SmallVectorImpl<Intrinsic *> &Defs);
508 SmallVectorImpl<Intrinsic *> &Defs);
1966 SmallVectorImpl<Intrinsic *> &Defs) {
1973 for (auto *Def : Defs) {
1997 SmallVectorImpl<Intrinsic *> &Defs) {
2011 for (auto *Def : Defs) {
2093 SmallVectorImpl<Intrinsic *> &Defs) {
2098 for (auto *Def : Defs) {
2179 SmallVector<Intrinsic *, 128> Defs; local
1965 genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs) argument
1996 genOverloadTypeCheckCode(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs) argument
2092 genIntrinsicRangeCheckCode(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs) argument
2338 SmallVector<Intrinsic *, 128> Defs; local
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