Searched defs:Defs (Results 1 - 25 of 42) sorted by relevance

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/external/llvm/utils/TableGen/
H A DCTagsEmitter.cpp67 const auto &Defs = Records.getDefs(); local
70 Tags.reserve(Classes.size() + Defs.size());
73 for (const auto &D : Defs)
H A DInstrInfoEmitter.cpp366 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); local
367 if (!Defs.empty()) {
368 unsigned &IL = EmittedLists[Defs];
369 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
533 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
H A DCodeGenTarget.cpp431 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic"); local
434 Result.reserve(Defs.size());
436 for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
437 bool isTarget = Defs[I]->getValueAsBit("isTarget");
439 Result.push_back(CodeGenIntrinsic(Defs[I]));
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DInstrInfoEmitter.cpp192 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); local
193 if (!Defs.empty()) {
194 unsigned &IL = EmittedLists[Defs];
195 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
320 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
/external/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp255 SmallVector<unsigned, 2> Defs; local
270 Defs.push_back(Reg);
290 Defs.push_back(Reg);
333 // Any previous copy definition or reading the Defs is no longer available.
334 for (unsigned Reg : Defs)
H A DMachineInstrBundle.cpp135 SmallVector<MachineOperand*, 4> Defs; local
142 Defs.push_back(&MO);
167 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
168 MachineOperand &MO = *Defs[i];
195 Defs.clear();
H A DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) {
483 Defs.push_back(Reg); // Remember this def.
487 SmallVectorImpl<unsigned> &Defs) {
488 while (!Defs.empty()) {
489 unsigned Reg = Defs.back();
490 Defs.pop_back();
501 SmallVectorImpl<unsigned> &Defs) {
561 HandlePhysRegDef(MOReg, &MI, Defs);
563 UpdatePhysRegDefs(MI, Defs);
568 SmallVector<unsigned, 4> Defs; local
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument
486 UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) argument
500 runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) argument
770 SmallSet<unsigned, 16> Defs, Kills; local
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/external/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp51 SmallSet<unsigned, 4> &Defs,
62 SmallSet<unsigned, 4> &Defs,
92 Defs.insert(*Subreg);
126 SmallSet<unsigned, 4> &Defs,
141 if (Uses.count(DstReg) || Defs.count(SrcReg))
183 SmallSet<unsigned, 4> Defs; local
196 Defs.clear();
198 TrackDefUses(MI, Defs, Uses, TRI);
239 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
249 TrackDefUses(NMI, Defs, Use
61 TrackDefUses(MachineInstr *MI, SmallSet<unsigned, 4> &Defs, SmallSet<unsigned, 4> &Uses, const TargetRegisterInfo *TRI) argument
124 MoveCopyOutOfITBlock(MachineInstr *MI, ARMCC::CondCodes CC, ARMCC::CondCodes OCC, SmallSet<unsigned, 4> &Defs, SmallSet<unsigned, 4> &Uses) argument
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H A DA15SDOptimizer.cpp409 SmallVector<unsigned, 8> Defs;
420 Defs.push_back(MO.getReg());
422 return Defs;
608 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); local
611 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
/external/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp242 NodeList Defs; local
247 Defs = DFG.getRelatedRefs(IA, DA);
248 if (!std::all_of(Defs.begin(), Defs.end(), IsDead))
253 // Mark all nodes in Defs for removal.
254 for (auto D : Defs)
H A DHexagonBitSimplify.cpp157 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
224 RegisterSet Defs; local
226 getInstrDefs(I, Defs);
228 NewAVs.insert(Defs);
244 RegisterSet &Defs) {
251 Defs.insert(R);
1417 RegisterSet Defs;
1422 Defs.clear();
1423 HBS::getInstrDefs(*I, Defs);
1424 if (Defs
243 getInstrDefs(const MachineInstr &MI, RegisterSet &Defs) argument
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H A DHexagonGenMux.cpp67 BitVector Defs, Uses; member in struct:__anon13113::HexagonGenMux::DefUseInfo
68 DefUseInfo() : Defs(), Uses() {}
69 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
91 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
122 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, argument
129 expandReg(*R++, Defs);
139 BitVector &Set = Mo->isDef() ? Defs : Uses;
149 BitVector Defs(NR), Uses(NR);
154 Defs.reset();
156 getDefsUses(MI, Defs, Use
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H A DHexagonOptAddrMode.cpp195 NodeSet Visited, Defs; local
196 const auto &ReachingDefs = LV->getAllReachingDefsRec(UR, UN, Visited, Defs);
199 dbgs() << "*** Multiple Reaching Defs found!!! ***\n";
H A DRDFLiveness.cpp126 SetVector<NodeId> Defs; local
132 Defs.insert(TA.Id);
195 auto DefInSet = [&Defs] (NodeAddr<RefNode*> TA) -> bool {
197 Defs.count(TA.Id);
241 NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) {
245 for (const auto D : Defs) {
253 return Defs;
256 NodeSet TmpDefs = Defs;
260 NodeSet Result = Defs;
791 // LiveUses -= Defs(
240 getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) argument
837 auto &Defs = LiveIn[I.first]; local
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/external/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp62 SmallPtrSet<Value *, 8> Defs; local
65 Defs.insert(V);
71 if (Defs.insert(Op).second)
74 return Defs;
196 auto Defs = findAllDefs(U); local
199 if (!std::any_of(Defs.begin(), Defs.end(), isa<Instruction, Value *>))
205 for (Value *V : Defs)
209 for (Value *V : Defs)
220 for (Value *V : Defs)
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/external/lzma/C/
H A D7z.h64 Byte *Defs; /* MSB 0 bit numbering */ member in struct:__anon14103
70 Byte *Defs; /* MSB 0 bit numbering */ member in struct:__anon14104
77 #define SzBitWithVals_Check(p, i) ((p)->Defs && ((p)->Defs[(i) >> 3] & (0x80 >> ((i) & 7))) != 0)
/external/lzma/CPP/7zip/Archive/7z/
H A D7zItem.h92 CBoolVector Defs; member in struct:NArchive::N7z::CUInt32DefVector
97 Defs.ClearAndSetSize(newSize);
103 Defs.Clear();
109 Defs.ReserveDown();
113 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; }
118 CBoolVector Defs; member in struct:NArchive::N7z::CUInt64DefVector
123 Defs.Clear();
129 Defs.ReserveDown();
135 if (index < Defs
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DScheduleDAGInstrs.h107 /// Defs, Uses - Remember where defs and uses of each physical register
111 std::vector<std::vector<SUnit *> > Defs; member in class:llvm::ScheduleDAGInstrs
115 /// unknown store, as we iterate. As with Defs and Uses, this is here
H A DLiveVariables.cpp423 SmallVector<unsigned, 4> &Defs) {
462 Defs.push_back(Reg); // Remember this def.
466 SmallVector<unsigned, 4> &Defs) {
467 while (!Defs.empty()) {
468 unsigned Reg = Defs.back();
469 Defs.pop_back();
510 SmallVector<unsigned, 4> Defs; local
515 HandlePhysRegDef(*II, 0, Defs);
568 HandlePhysRegDef(MOReg, MI, Defs);
570 UpdatePhysRegDefs(MI, Defs);
422 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVector<unsigned, 4> &Defs) argument
465 UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs) argument
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H A DStackSlotColoring.cpp143 SmallSet<unsigned, 4> &Defs,
429 SmallSet<unsigned, 4> &Defs = NewDefs[MBBId]; local
430 UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
613 SmallSet<unsigned, 4> &Defs,
627 if (!Defs.count(Reg)) {
631 Defs.insert(Reg);
645 Defs.insert(Reg);
656 if (!Defs.count(Reg))
660 Defs.insert(Reg);
610 UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI, unsigned Reg, const TargetRegisterClass *RC, SmallSet<unsigned, 4> &Defs, MachineFunction &MF) argument
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp45 SmallSet<unsigned, 4> &Defs,
56 SmallSet<unsigned, 4> &Defs,
85 Defs.insert(Reg);
88 Defs.insert(*Subreg);
109 SmallSet<unsigned, 4> &Defs,
124 if (Uses.count(DstReg) || Defs.count(SrcReg))
166 SmallSet<unsigned, 4> Defs; local
179 Defs.clear();
181 TrackDefUses(MI, Defs, Uses, TRI);
218 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Use
55 TrackDefUses(MachineInstr *MI, SmallSet<unsigned, 4> &Defs, SmallSet<unsigned, 4> &Uses, const TargetRegisterInfo *TRI) argument
107 MoveCopyOutOfITBlock(MachineInstr *MI, ARMCC::CondCodes CC, ARMCC::CondCodes OCC, SmallSet<unsigned, 4> &Defs, SmallSet<unsigned, 4> &Uses) argument
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/external/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h149 /// Defs, Uses - Remember where defs and uses of each register are as we
153 Reg2SUnitsMap Defs; member in class:llvm::ScheduleDAGInstrs
/external/swiftshader/third_party/subzero/src/
H A DIceRegAlloc.cpp61 << " LIVE=" << Var->getLiveRange() << " Defs=";
64 const InstDefList &Defs = VMetadata->getLatterDefinitions(Var); local
65 for (size_t i = 0; i < Defs.size(); ++i) {
66 Str << "," << Defs[i]->getNumber();
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.h88 llvm::DenseMap<unsigned, PredSet> Defs; member in class:llvm::HexagonMCChecker
193 const NewSenseList &Defs) const;
/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp97 /// This function sets all caller-saved registers in Defs.
100 /// This function sets all unallocatable registers in Defs.
118 BitVector Defs, Uses; member in class:__anon13196::RegDefsUses
172 /// Update Defs and Uses. Return true if there exist dependences that
174 /// Defs.
182 SmallPtrSet<ValueType, 4> Uses, Defs; member in class:__anon13196::MemDefsUses
320 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
326 // If MI is a call, add RA to Defs to prevent users of RA from going into
329 Defs.set(Mips::RA);
335 Defs
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