/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 65 const MCOperand &Disp = MI->getOperand(OpNo+1); local 78 if (Disp.isExpr()) 79 Disp.getExpr()->print(O, &MAI); 81 assert(Disp.isImm() && "Expected immediate in displacement field"); 82 O << Disp.getImm();
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 63 const MCOperand &Disp = MI->getOperand(OpNo+1); local 76 if (Disp.isExpr()) 77 O << *Disp.getExpr(); 79 assert(Disp.isImm() && "Expected immediate in displacement field"); 80 O << Disp.getImm();
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 108 const MachineOperand &Disp = MI->getOperand(OpNum+1); local 113 if (Disp.isImm() && !Base.getReg())
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H A D | MSP430ISelDAGToDAG.cpp | 47 int16_t Disp; member in struct:__anon13175::MSP430ISelAddressMode 56 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr), 72 errs() << " Disp " << Disp << '\n'; 118 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); 144 AM.Disp += G->getOffset(); 149 AM.Disp += CP->getOffset(); 186 AM.Disp += Val; 229 AM.Disp += Offset; 244 SDValue &Base, SDValue &Disp) { 243 SelectAddr(SDValue N, SDValue &Base, SDValue &Disp) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 114 const MachineOperand &Disp = MI->getOperand(OpNum+1); local 119 if (Disp.isImm() && !Base.getReg())
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H A D | MSP430ISelDAGToDAG.cpp | 46 int16_t Disp; member in struct:__anon20072::MSP430ISelAddressMode 55 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0), 71 errs() << " Disp " << Disp << '\n'; 123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); 149 AM.Disp += G->getOffset(); 154 AM.Disp += CP->getOffset(); 191 AM.Disp += Val; 234 AM.Disp += Offset; 249 SDValue &Base, SDValue &Disp) { 248 SelectAddr(SDValue N, SDValue &Base, SDValue &Disp) argument [all...] |
/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 24 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, argument 26 O << Disp; local 198 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); 200 O << Disp << '(' << Length;
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local 153 assert(isUInt<4>(Base) && isUInt<12>(Disp)); 154 return (Base << 12) | Disp; 162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local 163 assert(isUInt<4>(Base) && isInt<20>(Disp)); 164 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); 172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local 174 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); 175 return (Index << 16) | (Base << 12) | Disp; 183 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local 195 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local 206 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
H A D | MBlazeISelDAGToDAG.cpp | 86 bool SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base); 148 SelectAddrRegImm(SDValue N, SDValue &Base, SDValue &Disp) { argument 150 if (SelectAddrRegReg(N, Base, Disp)) 156 Disp = CurDAG->getTargetConstant(imm, MVT::i32); 167 Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0)); 172 Disp = CurDAG->getTargetConstant(0, TM.getTargetLowering()->getPointerTy());
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 33 /// with R15 or R11 and Disp being offsetted accordingly. 46 int32_t Disp; member in struct:llvm::SystemZAddressMode 49 SystemZAddressMode() : BaseType(RegBase), IndexReg(0), Disp(0) { 98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
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H A D | SystemZISelDAGToDAG.cpp | 48 int64_t Disp; member in struct:__anon20112::SystemZRRIAddressMode 52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) { 72 errs() << " Disp " << Disp << '\n'; 86 SDValue &Base, SDValue &Disp); 88 SDValue &Base, SDValue &Disp, 124 SDValue &Base, SDValue &Disp); 126 SDValue &Base, SDValue &Disp, 128 bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp); 130 SDValue &Base, SDValue &Disp, SDValu 337 getAddressOperandsRI(const SystemZRRIAddressMode &AM, SDValue &Base, SDValue &Disp) argument 346 getAddressOperands(const SystemZRRIAddressMode &AM, SDValue &Base, SDValue &Disp, SDValue &Index) argument 355 SelectAddrRI12Only(SDValue &Addr, SDValue &Base, SDValue &Disp) argument 360 SelectAddrRI12(SDValue &Addr, SDValue &Base, SDValue &Disp, bool is12BitOnly) argument 410 SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp) argument 453 SelectAddrRRI12(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) argument 502 SelectAddrRRI20(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) argument 546 SelectLAAddr(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) argument 579 TryFoldLoad(SDNode *P, SDValue N, SDValue &Base, SDValue &Disp, SDValue &Index) argument [all...] |
/external/swiftshader/third_party/subzero/src/ |
H A D | IceInstX8632.cpp | 104 int32_t Disp = Var->getStackOffset(); local 107 Disp += Target->getFrameFixedAllocaOffset(); 111 return Disp; 140 int32_t Disp = 0; local 142 Disp += getRematerializableOffset(getBase(), Target); 156 if (getOffset() == nullptr && Disp == 0) { 158 } else if (getOffset() == nullptr && Disp != 0) { 159 Str << Disp; local 161 if (getBase() == nullptr || CI->getValue() || Disp != 0) 163 Str << CI->getValue() + Disp; 198 int32_t Disp = 0; local 226 Str << Disp; local 268 int32_t Disp = 0; local [all...] |
H A D | IceInstX8664.cpp | 94 int32_t Disp = Var->getStackOffset(); local 97 Disp += Target->getFrameFixedAllocaOffset(); 101 return Disp; 113 int32_t Disp = 0; local 115 Disp += getRematerializableOffset(getBase(), Target); 125 if (getOffset() == nullptr && Disp == 0) { 127 } else if (getOffset() == nullptr && Disp != 0) { 128 Str << Disp; local 130 if (Base == nullptr || CI->getValue() || Disp != 0) 132 Str << CI->getValue() + Disp; 194 int32_t Disp = 0; local 221 Str << Disp; local 254 int32_t Disp = 0; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 35 /// with BP or SP and Disp being offsetted accordingly. The displacement may 50 int Disp; member in struct:llvm::X86AddressMode 55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), 77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); 79 MO.push_back(MachineOperand::CreateImm(Disp)); 109 AM.Disp = Op.getImm(); 164 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); 166 MIB.addImm(AM.Disp);
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H A D | X86OptimizeLEAs.cpp | 71 const MachineOperand *Disp) 72 : Disp(Disp) { 89 return isSimilarDispOp(*Disp, *Other.Disp); 96 const MachineOperand *Disp; member in class:MemOpKey 119 assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key"); 120 assert(Val.Disp != PtrInfo::getTombstoneKey() && 130 switch (Val.Disp->getType()) { 135 Hash = hash_combine(Hash, Val.Disp 69 MemOpKey(const MachineOperand *Base, const MachineOperand *Scale, const MachineOperand *Index, const MachineOperand *Segment, const MachineOperand *Disp) argument [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 165 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, argument 167 switch (Disp.getType()) { 171 return addImm(Disp.getImm() + off); 173 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off);
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 36 /// with BP or SP and Disp being offsetted accordingly. The displacement may 51 int Disp; member in struct:llvm::X86AddressMode 56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) { 77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); 79 MO.push_back(MachineOperand::CreateImm(Disp)); 136 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); 138 MIB.addImm(AM.Disp);
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/external/llvm/tools/llvm-objdump/ |
H A D | COFFDump.cpp | 227 uint64_t Offset, uint32_t Disp) { 231 if (Disp > 0) 232 Out << format(" + 0x%04x", Disp); 234 Out << format("0x%04x", Disp); 225 printCOFFSymbolAddress(llvm::raw_ostream &Out, const std::vector<RelocationRef> &Rels, uint64_t Offset, uint32_t Disp) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 210 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, argument 217 TargetFlags = Disp.getTargetFlags(); 219 switch (Disp.getType()) { 223 return addImm(Disp.getImm() + off); 225 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off, 228 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 310 const MCExpr *Disp = MCConstantExpr::create(0, Ctx); local 312 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc())); 319 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx); local 321 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(), 329 const MCExpr *Disp = MCConstantExpr::create(0, Ctx); local 331 getPointerWidth(), 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc())); 337 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx); local 339 getPointerWidth(), 0, Disp, DstReg, CntReg, AccessSize, SMLoc(), 455 const MCConstantExpr *Disp = local 458 X86Operand::CreateMem(getPointerWidth(), 0, Disp, Re 488 const MCExpr *Disp = MCConstantExpr::create(NewDisplacement, Ctx); local 639 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx); local 665 const MCExpr *Disp = MCConstantExpr::create(1, Ctx); local 716 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx); local 856 const MCExpr *Disp = MCConstantExpr::create(Offset, Ctx); local 911 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx); local 937 const MCExpr *Disp = MCConstantExpr::create(1, Ctx); local 988 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx); local [all...] |
H A D | X86Operand.h | 54 const MCExpr *Disp; member in struct:llvm::X86Operand::MemOp 109 return Mem.Disp; 497 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, argument 502 Res->Mem.Disp = Disp; 516 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, argument 529 Res->Mem.Disp = Disp;
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 57 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 59 int64_t Disp; member in struct:__anon13282::SystemZAddressingMode 64 : Form(form), DR(dr), Base(), Disp(0), Index(), 90 errs() << " Disp " << Disp; 158 SDValue &Base, SDValue &Disp) const; 160 SDValue &Base, SDValue &Disp, SDValue &Index) const; 164 // Base and Disp respectively. 166 SDValue &Base, SDValue &Disp) const; 170 // base and displacement in Base and Disp respectivel 213 selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 219 selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 225 selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 231 selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 237 selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 243 selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 249 selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 255 selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 495 shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) argument 623 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 657 selectBDXAddr(SystemZAddressingMode::AddrForm Form, SystemZAddressingMode::DispRange DR, SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 669 selectBDVAddr12Only(SDValue Addr, SDValue Elem, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 1347 SDValue Base, Disp, Index; local [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); local 65 Disp.isImm() && Disp.getImm() < 0x10000) 102 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 354 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); local 402 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 446 if (Disp.isImm() && isDisp8(Disp.getImm())) { 447 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 454 EmitImmediate(Disp, M [all...] |
/external/llvm/lib/Transforms/IPO/ |
H A D | LowerTypeTests.cpp | 640 Constant *Disp = ConstantExpr::getSub(DestInt, SrcInt); local 643 Constant *OffsetedDisp = ConstantExpr::getSub(Disp, DispOffset);
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 254 bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp, 258 bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp, 373 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp, argument 377 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
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