| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | TargetInstrInfoImpl.cpp | 67 unsigned Idx1, Idx2; local
68 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
78 unsigned Reg1 = MI->getOperand(Idx1).getReg();
80 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
85 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
112 MI->getOperand(Idx1).setReg(Reg2);
114 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
|
| /external/llvm/lib/Analysis/ |
| H A D | StratifiedSets.h | 451 void merge(StratifiedIndex Idx1, StratifiedIndex Idx2) { argument
452 assert(inbounds(Idx1) && inbounds(Idx2));
453 assert(&linksAt(Idx1) != &linksAt(Idx2) &&
456 // CASE 1: If the set at `Idx1` is above or below `Idx2`, we need to merge
459 if (tryMergeUpwards(Idx1, Idx2))
462 if (tryMergeUpwards(Idx2, Idx1))
465 // CASE 2: The set at `Idx1` is not in the same chain as the set at `Idx2`.
467 mergeDirect(Idx1, Idx2);
470 /// \brief Merges two sets assuming that the set at `Idx1` is unreachable from
472 void mergeDirect(StratifiedIndex Idx1, StratifiedInde argument
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 619 Record *Idx1 = i1->first; local
625 // Try composing Idx1 with another SubRegIndex.
628 std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
641 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
653 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
|
| /external/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 127 bool NewMI, unsigned Idx1,
135 unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
138 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
140 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
144 unsigned Reg1 = MI.getOperand(Idx1).getReg();
147 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
149 bool Reg1IsKill = MI.getOperand(Idx1).isKill();
151 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
153 bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
158 MI.getDesc().getOperandConstraint(Idx1, MCO
126 commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned Idx1, unsigned Idx2) const argument
[all...] |
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1130 CodeGenSubRegIndex *Idx1 = i1->first; local
1136 // Try composing Idx1 with another SubRegIndex.
1149 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1150 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
|
| /external/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 1178 Value *CreateConstGEP2_32(Type *Ty, Value *Ptr, unsigned Idx0, unsigned Idx1, argument
1182 ConstantInt::get(Type::getInt32Ty(Context), Idx1)
1191 unsigned Idx1, const Twine &Name = "") {
1194 ConstantInt::get(Type::getInt32Ty(Context), Idx1)
1219 Value *CreateConstGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1, argument
1223 ConstantInt::get(Type::getInt64Ty(Context), Idx1)
1231 Value *CreateConstInBoundsGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1, argument
1235 ConstantInt::get(Type::getInt64Ty(Context), Idx1)
1190 CreateConstInBoundsGEP2_32(Type *Ty, Value *Ptr, unsigned Idx0, unsigned Idx1, const Twine &Name = �) argument
|
| /external/swiftshader/third_party/LLVM/include/llvm/Support/ |
| H A D | IRBuilder.h | 834 Value *CreateConstGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1, argument
838 ConstantInt::get(Type::getInt32Ty(Context), Idx1)
846 Value *CreateConstInBoundsGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1, argument
850 ConstantInt::get(Type::getInt32Ty(Context), Idx1)
875 Value *CreateConstGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1, argument
879 ConstantInt::get(Type::getInt64Ty(Context), Idx1)
887 Value *CreateConstInBoundsGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1, argument
891 ConstantInt::get(Type::getInt64Ty(Context), Idx1)
|
| /external/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 5112 llvm::Value *Idx1 = llvm::ConstantInt::get(SizeTy, 1); local
5114 Value *Op1 = Builder.CreateExtractElement(Vec, Idx1, "lane1");
5125 llvm::Value *Idx1 = llvm::ConstantInt::get(SizeTy, 1); local
5127 Value *Op1 = Builder.CreateExtractElement(Vec, Idx1, "lane1");
5138 llvm::Value *Idx1 = llvm::ConstantInt::get(SizeTy, 1); local
5140 Value *Op1 = Builder.CreateExtractElement(Vec, Idx1, "lane1");
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8436 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); local
8441 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8446 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9790 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); local
9795 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9800 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
|