/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/llvm/lib/CodeGen/ |
H A D | PatchableFunction.cpp | 72 auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(), local 78 MIB.addOperand(MO);
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H A D | XRayInstrumentation.cpp | 76 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), local 80 MIB.addOperand(MO);
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H A D | MachineInstrBundle.cpp | 123 MachineInstrBuilder MIB = local 125 Bundle.prepend(MIB); 204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | 213 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
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/external/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 122 MachineInstrBuilder MIB; local 124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg) 129 MIB.addMemOperand(MMO); 130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg); 131 MIB.addReg(Reg, RegState::Kill).addImm(0); 132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 133 AddDefaultPred(MIB);
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H A D | ARMBaseInstrInfo.h | 201 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 399 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument 400 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 404 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument 405 return MIB.addReg(0); 409 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument 411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 415 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument 416 return MIB.addReg(0);
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H A D | ThumbRegisterInfo.cpp | 164 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local 166 MIB = AddDefaultT1CC(MIB); 168 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 170 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 171 AddDefaultPred(MIB); 304 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg); 306 MIB = AddDefaultT1CC(MIB); 307 MIB [all...] |
H A D | Thumb2ITBlockPass.cpp | 201 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) local 209 MachineBasicBlock::iterator InsertPos = MIB.getInstr(); 258 MIB.addImm(Mask);
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H A D | Thumb2InstrInfo.cpp | 156 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); local 157 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 158 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 159 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); 160 AddDefaultPred(MIB); 198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); local 199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); 202 AddDefaultPred(MIB); [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 25 /// Add a BDX memory reference for frame object FI to MIB. 27 addFrameReference(const MachineInstrBuilder &MIB, int FI) { argument 28 MachineInstr *MI = MIB; 41 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXPeephole.cpp | 112 MachineInstrBuilder MIB = local 118 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFixupHwLoops.cpp | 172 MachineInstrBuilder MIB; local 190 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp)); 193 MIB.addOperand(MII->getOperand(i));
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 294 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument 295 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 299 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument 300 return MIB.addReg(0); 304 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 310 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument 311 return MIB.addReg(0);
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H A D | MLxExpansionPass.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg) local 229 MIB.addImm(LaneImm); 230 MIB.addImm(Pred).addReg(PredReg); 232 MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID2) 237 MIB.addReg(TmpReg, getKillRegState(true)) 240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); 242 MIB.addImm(Pred).addReg(PredReg);
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 59 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 62 return MIB.addReg(Reg).addImm(0).addReg(0); 66 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument 67 return MIB.addImm(Offset).addReg(0); 75 addRegOffset(const MachineInstrBuilder &MIB, argument 77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 83 addRegReg(const MachineInstrBuilder &MIB, argument 85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0) 90 addFullAddress(const MachineInstrBuilder &MIB, const SystemZAddressMode &AM) { argument 92 MIB 107 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 208 MachineInstrBuilder &MIB, 241 MIB.addReg(VRBase, RegState::Define); 254 MIB.addReg(VRBase, RegState::Define); 266 MIB.addReg(VRBase, RegState::Define); 312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, argument 324 const MCInstrDesc &MCID = MIB->getDesc(); 358 unsigned Idx = MIB->getNumOperands(); 360 MIB->getOperand(Idx-1).isReg() && 361 MIB->getOperand(Idx-1).isImplicit()) 368 MIB 207 CreateVirtualRegisters(SDNode *Node, MachineInstrBuilder &MIB, const MCInstrDesc &II, bool IsClone, bool IsCloned, DenseMap<SDValue, unsigned> &VRBaseMap) argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 284 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), local 287 DEBUG(dbgs() << " adding copy: " << *MIB); 289 return MIB;
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H A D | AArch64BranchRelaxation.cpp | 440 MachineInstrBuilder MIB = BuildMI( local 445 MIB.addOperand(MI->getOperand(1)); 447 invertBccCondition(MIB); 448 MIB.addMBB(NextBB);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local 106 MIB.addReg(Cond[i].getReg()); 108 MIB.addImm(Cond[i].getImm()); 112 MIB.addMBB(TBB); 399 MachineInstrBuilder MIB; local 430 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); 440 MIB->RemoveOperand(0); 443 MIB.addOperand(I->getOperand(J)); 446 MIB.addImm(0); 451 MIB [all...] |
H A D | MipsLongBranch.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); local 235 MIB.addReg(MO.getReg()); 238 MIB.addMBB(MBBOpnd); 245 MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFixIrreducibleControlFlow.cpp | 187 MachineInstrBuilder MIB = BuildMI(*Dispatch, Dispatch->end(), DebugLoc(), local 194 MIB.addReg(Reg); 207 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; 215 MIB.addMBB(MBB); 259 MIB.addMBB(MIB.getInstr() 260 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1)
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/external/llvm/lib/Target/X86/ |
H A D | X86ExpandPseudo.cpp | 112 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); local 114 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 118 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 125 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); local 127 MIB.addOperand(MBBI->getOperand(i)); 171 MachineInstrBuilder MIB; local 173 MIB = BuildMI(MBB, MBBI, DL, 176 MIB = BuildMI(MBB, MBBI, DL, 187 MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL)); 190 MIB [all...] |
H A D | X86InstrBuilder.h | 119 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 127 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument 128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); 136 addRegOffset(const MachineInstrBuilder &MIB, argument 138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 143 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument 146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 151 addFullAddress(const MachineInstrBuilder &MIB, argument 156 MIB 177 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument 202 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument [all...] |