Searched defs:RC2 (Results 1 - 9 of 9) sorted by relevance

/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/jcajce/provider/symmetric/
H A DRC2.java41 public final class RC2 class
43 private RC2() method in class:RC2
49 // * RC2
82 // * RC2
230 // throw new InvalidAlgorithmParameterException("No supported AlgorithmParameterSpec for RC2 parameter generation.");
250 // params = createParametersInstance("RC2");
262 // params = createParametersInstance("RC2");
280 // super("RC2", 128, new CipherKeyGenerator());
381 // throw new InvalidParameterSpecException("unknown parameter spec passed to RC2 parameters object.");
411 // throw new InvalidParameterSpecException("IvParameterSpec or RC2ParameterSpec required to initialise a RC2 parameter
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/external/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp884 LazyCallGraph::RefSCC *RC2 = CG.lookupRefSCC(B); local
885 EXPECT_EQ(RC2, CG.lookupRefSCC(C));
886 EXPECT_EQ(RC2, NewRCs[0]);
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DRegisterInfoEmitter.cpp553 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second); local
554 assert(RC2 && "Invalid register class in SubRegClasses");
555 SuperRegClassMap[RC2->EnumValue].insert(rc);
577 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II]; local
580 OS << "&" << RC2.getQualifiedName() << "RegClass";
/external/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp160 const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
269 uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2,
272 // If RC1[i] is "bottom", it cannot be proven equal to RC2[i].
275 // Same for RC2[i].
276 if (RC2[B2+i].Type == BitTracker::BitValue::Ref && RC2[B2+i].RefI.Reg == 0)
278 if (RC1[B1+i] != RC2[B2+i])
268 isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W) argument
H A DHexagonGenInsert.cpp316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); local
317 uint16_t W1 = RC1.width(), W2 = RC2.width();
319 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i];
335 const BitTracker::RegisterCell &RC2 = CM.lookup(VR2); local
336 uint16_t W1 = RC1.width(), W2 = RC2.width();
350 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2];
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp294 const TargetRegisterClass *RC2 = local
299 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
306 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
358 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; local
364 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1874 CodeGenRegisterClass *RC2 = &*I; local
1875 if (RC1 == RC2)
1878 // Compute the set intersection of RC1 and RC2.
1880 const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
1890 // If RC1 and RC2 have different spill sizes or alignments, use the
1892 if (RC2->SpillSize > RC1->SpillSize ||
1893 (RC2->SpillSize == RC1->SpillSize &&
1894 RC2->SpillAlignment > RC1->SpillAlignment))
1895 std::swap(RC1, RC2);
1898 RC1->getName() + "_and_" + RC2
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/external/google-tv-pairing-protocol/java/jar/
H A Dbcprov-jdk15-143.jarMETA-INF/MANIFEST.MF META-INF/BCKEY.SF META-INF/BCKEY.DSA META ...
/external/r8/deps/
H A Dcommons-compress-1.12.jarMETA-INF/ META-INF/MANIFEST.MF org/ org/apache/ org/apache/commons/ org/apache/commons/compress/ ...

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