| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon20077
|
| /external/valgrind/none/tests/mips64/ |
| H A D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator in enum:__anon25311
177 case SRA:
|
| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 38 SRA = 0x37, enumerator in enum:llvm::LPAC::AluCode
97 case SRA:
115 .Case("sha", SRA)
139 case ISD::SRA:
140 return AluCode::SRA;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
|
| /external/swiftshader/third_party/LLVM/include/llvm/TableGen/ |
| H A D | Record.h | 954 enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1011 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; local
1026 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1030 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1031 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
|
| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeSPARC_common.c | 156 #define SRA (OPC1(0x2) | OPC3(0x27)) macro
793 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(SLJIT_R0) | IMM(31), DR(TMP_REG1)));
|
| H A D | sljitNativeMIPS_common.c | 169 #define SRA (HI(0) | LO(3)) macro
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
408 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 837 if (Opc == ISD::SRA)
1071 case ISD::SRA: return visitSRA(N);
1148 case ISD::SRA:
1786 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1798 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, local
1804 return SRA;
1806 AddToWorkList(SRA.getNode());
1808 DAG.getConstant(0, VT), SRA);
1988 return DAG.getNode(ISD::SRA,
3488 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 670 setOperationAction(ISD::SRA, VT, Custom);
1673 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1701 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
2375 case ISD::SRA:
4438 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4473 Opc == ISD::SRA
6645 case ISD::SRA:
6650 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6658 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
7460 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(
7525 SDValue SRA = local
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1107 if (Opc == ISD::SRA)
1379 case ISD::SRA: return visitSRA(N);
1480 case ISD::SRA:
2270 DAG.getNode(ISD::SRA, DL, VT, N0,
2283 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD, local
2290 return SRA;
2292 AddToWorklist(SRA.getNode());
2293 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
2479 return DAG.getNode(ISD::SRA, D
4737 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT, local
[all...] |