Searched defs:SchedClass (Results 1 - 9 of 9) sorted by relevance
/external/llvm/include/llvm/Target/ |
H A D | TargetSubtargetInfo.h | 113 /// Resolve a SchedClass at runtime, where SchedClass identifies an 115 /// another variant SchedClass, but repeated invocation must quickly terminate 116 /// in a nonvariant SchedClass. 117 virtual unsigned resolveSchedClass(unsigned SchedClass, argument
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/external/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 105 unsigned SchedClass = MI->getDesc().getSchedClass(); local 106 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); 116 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); 117 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
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H A D | MachinePipeliner.cpp | 1251 unsigned SchedClass = MI.getDesc().getSchedClass(); local 1252 for (const InstrStage *IS = InstrItins->beginStage(SchedClass), 1253 *IE = InstrItins->endStage(SchedClass);
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/external/swiftshader/third_party/LLVM/include/llvm/MC/ |
H A D | MCInstrDesc.h | 138 unsigned short SchedClass; // enum identifying instr sched class member in class:llvm::MCInstrDesc 270 return SchedClass;
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/external/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 255 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass. variable 309 : Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr), 325 : Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr), 340 : Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
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/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 144 unsigned short SchedClass; // enum identifying instr sched class member in class:llvm::MCInstrDesc 528 unsigned getSchedClass() const { return SchedClass; }
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 380 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); local 381 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); 728 unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); local 729 switch (SchedClass) {
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/external/llvm/utils/TableGen/ |
H A D | SubtargetEmitter.cpp | 41 // Each processor has a SchedClassDesc table with an entry for each SchedClass. 799 // Generate the SchedClass table for this processor and update global 821 // A Variant SchedClass has no resources of its own. 842 // Determine if the SchedClass is actually reachable on this processor. If 957 // Create an entry for each operand Read in this SchedClass. 994 // Add the information for this SchedClass to the global tables using basic 1052 // Emit SchedClass tables for all processors and associated global tables. 1104 // Emit a SchedClass table for each processor. 1128 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); local 1129 OS << " {DBGFIELD(\"" << SchedClass [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 2041 unsigned SchedClass = MI->getDesc().getSchedClass(); local 2042 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23) 2251 unsigned SchedClass = MI->getDesc().getSchedClass(); local 2253 switch (SchedClass) { 2548 unsigned SchedClass = MI->getDesc().getSchedClass(); local 2549 switch (SchedClass) { 2567 unsigned SchedClass = MI->getDesc().getSchedClass(); local 2568 switch (SchedClass) { 2584 unsigned SchedClass = MI->getDesc().getSchedClass(); local 2585 switch (SchedClass) { 2608 unsigned SchedClass = MI->getDesc().getSchedClass(); local [all...] |
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