Searched defs:SrcReg1 (Results 1 - 4 of 4) sorted by relevance

/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program_alu.c63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
74 fpi->U.I.SrcReg[1] = SrcReg1;
82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
94 fpi->U.I.SrcReg[1] = SrcReg1;
59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument
78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp872 unsigned SrcReg1 = getRegForValue(SrcValue1); local
873 if (SrcReg1 == 0)
885 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
887 SrcReg1 = ExtReg;
899 .addReg(SrcReg1).addReg(SrcReg2);
902 .addReg(SrcReg1).addImm(Imm);
1204 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); local
1205 if (SrcReg1 == 0) return false;
1218 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1222 MRI.setRegClass(SrcReg1,
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/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3292 unsigned SrcReg1 = MUL->getOperand(2).getReg(); local
3301 if (TargetRegisterInfo::isVirtualRegister(SrcReg1))
3302 MRI.constrainRegClass(SrcReg1, RC);
3310 .addReg(SrcReg1, getKillRegState(Src1IsKill))
3316 .addReg(SrcReg1, getKillRegState(Src1IsKill))
3322 .addReg(SrcReg1, getKillRegState(Src1IsKill));
3356 unsigned SrcReg1 = MUL->getOperand(2).getReg(); local
3363 if (TargetRegisterInfo::isVirtualRegister(SrcReg1))
3364 MRI.constrainRegClass(SrcReg1, RC);
3371 .addReg(SrcReg1, getKillRegStat
[all...]
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1422 unsigned SrcReg1 = getRegForValue(Src1Value); local
1423 if (SrcReg1 == 0) return false;
1433 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1434 if (SrcReg1 == 0) return false;
1442 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1446 .addReg(SrcReg1).addReg(SrcReg2));
1450 .addReg(SrcReg1);
1758 unsigned SrcReg1 local
[all...]

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