Searched defs:imm (Results 1 - 25 of 180) sorted by relevance

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/external/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_opt_small_immediates.c84 uint32_t imm = c->uniform_data[src.index]; local
85 uint32_t small_imm = qpu_encode_small_immediate(imm);
95 inst->src[i].index = imm;
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_bitarit.c224 lp_build_shl_imm(struct lp_build_context *bld, LLVMValueRef a, unsigned imm) argument
226 LLVMValueRef b = lp_build_const_int_vec(bld->gallivm, bld->type, imm);
227 assert(imm < bld->type.width);
237 lp_build_shr_imm(struct lp_build_context *bld, LLVMValueRef a, unsigned imm) argument
239 LLVMValueRef b = lp_build_const_int_vec(bld->gallivm, bld->type, imm);
240 assert(imm < bld->type.width);
/external/v8/src/arm/
H A Dconstants-arm.cc27 uint64_t imm = high16 << 48; local
29 memcpy(&d, &imm, 8);
/external/v8/src/crankshaft/arm64/
H A Ddelayed-masm-arm64-inl.h38 void DelayedMasm::Fmov(FPRegister fd, double imm) { argument
40 __ Fmov(fd, imm);
/external/pcre/dist2/src/sljit/
H A DsljitNativeMIPS_32.c29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 dst_ar, sljit_sw imm) argument
31 if (!(imm & ~0xffff))
32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
34 if (imm < 0 && imm >= SIMM_MIN)
35 return push_inst(compiler, ADDIU | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
37 FAIL_IF(push_inst(compiler, LUI | TA(dst_ar) | IMM(imm >> 16), dst_ar));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
H A DsljitNativePPC_32.c29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) argument
31 if (imm <= SIMM_MAX && imm >= SIMM_MIN)
32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm));
34 if (!(imm & ~0xffff))
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16)));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm);
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H A DsljitNativeSPARC_32.c27 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 dst, sljit_sw imm) argument
29 if (imm <= SIMM_MAX && imm >= SIMM_MIN)
30 return push_inst(compiler, OR | D(dst) | S1(0) | IMM(imm), DR(dst));
32 FAIL_IF(push_inst(compiler, SETHI | D(dst) | ((imm >> 10) & 0x3fffff), DR(dst)));
33 return (imm & 0x3ff) ? push_inst(compiler, OR | D(dst) | S1(dst) | IMM_ARG | (imm & 0x3ff), DR(dst)) : SLJIT_SUCCESS;
H A DsljitNativeMIPS_64.c29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 dst_ar, sljit_sw imm) argument
37 if (!(imm & ~0xffff))
38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
40 if (imm < 0 && imm >= SIMM_MIN)
41 return push_inst(compiler, ADDIU | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
43 if (imm <= 0x7fffffffl && imm >= -0x80000000l) {
44 FAIL_IF(push_inst(compiler, LUI | TA(dst_ar) | IMM(imm >> 16), dst_ar));
45 return (imm
[all...]
H A DsljitNativePPC_64.c44 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) argument
51 if (imm <= SIMM_MAX && imm >= SIMM_MIN)
52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm));
54 if (!(imm & ~0xffff))
55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
57 if (imm <= 0x7fffffffl && imm >= -0x80000000l) {
58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16)));
59 return (imm
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H A DsljitNativeX86_32.c29 static sljit_s32 emit_do_imm(struct sljit_compiler *compiler, sljit_u8 opcode, sljit_sw imm) argument
37 sljit_unaligned_store_sw(inst, imm);
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_transform.c70 const struct tgsi_full_immediate *imm)
74 ti += tgsi_build_full_immediate(imm,
69 emit_immediate(struct tgsi_transform_context *ctx, const struct tgsi_full_immediate *imm) argument
H A Dtgsi_aa_point.c87 struct tgsi_full_immediate *imm)
91 ctx->emit_immediate(ctx, imm);
104 unsigned imm; local
120 imm = ts->num_imm++;
154 TGSI_FILE_IMMEDIATE, imm, true);
172 TGSI_FILE_IMMEDIATE, imm, TGSI_SWIZZLE_X,
178 TGSI_FILE_IMMEDIATE, imm, TGSI_SWIZZLE_X,
201 TGSI_FILE_IMMEDIATE, imm, TGSI_SWIZZLE_W, false);
86 aa_immediate(struct tgsi_transform_context *ctx, struct tgsi_full_immediate *imm) argument
H A Dtgsi_parse.c141 struct tgsi_full_immediate *imm = &ctx->FullToken.FullImmediate; local
144 memset(imm, 0, sizeof *imm);
145 copy_token(&imm->Immediate, &token);
147 imm_count = imm->Immediate.NrTokens - 1;
149 switch (imm->Immediate.DataType) {
153 next_token(ctx, &imm->u[i].Float);
160 next_token(ctx, &imm->u[i].Uint);
167 next_token(ctx, &imm->u[i].Int);
/external/mesa3d/src/gallium/drivers/ilo/core/
H A Dilo_builder_render.h81 uint64_t imm)
145 assert(!imm);
159 dw[4] = (uint32_t) imm;
160 dw[5] = (uint32_t) (imm >> 32);
171 dw[3] = (uint32_t) imm;
172 dw[4] = (uint32_t) (imm >> 32);
79 gen6_PIPE_CONTROL(struct ilo_builder *builder, uint32_t dw1, struct intel_bo *bo, uint32_t bo_offset, uint64_t imm) argument
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_tgsi_to_rc.c276 struct tgsi_full_immediate * imm,
285 if (imm->u[i].Float == 0.0f) {
287 } else if (imm->u[i].Float == 0.5f && ttr->use_half_swizzles) {
289 } else if (imm->u[i].Float == 1.0f) {
305 constant.u.Immediate[i] = imm->u[i].Float;
275 handle_immediate(struct tgsi_to_rc * ttr, struct tgsi_full_immediate * imm, unsigned index) argument
H A Dr300_vs.c186 struct ureg_src imm; local
192 imm = ureg_imm4f(ureg, 0, 0, 0, 1);
194 ureg_MOV(ureg, dst, imm);
/external/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_asm.h90 unsigned imm; /* takes place of src[2] for BRANCH/CALL */ member in struct:etna_inst
115 * imm
124 * Set field imm of already-assembled instruction.
128 etna_assemble_set_imm(uint32_t *out, uint32_t imm) argument
130 out[3] |= VIV_ISA_WORD_3_SRC2_IMM(imm);
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs_combine_constants.cpp101 struct imm { struct
142 struct imm *imm; member in struct:table
147 static struct imm *
151 if (table->imm[i].val == val) {
152 return &table->imm[i];
158 static struct imm *
163 table->imm = reralloc(mem_ctx, table->imm, struct imm, tabl
223 struct imm *imm = find_imm(&table, val); local
253 struct imm *imm = &table.imm[i]; local
273 struct imm *imm = &table.imm[i]; local
309 struct imm *imm = &table.imm[i]; local
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H A Dhsw_queryobj.c285 uint32_t offset, GLenum ptype, uint64_t imm)
290 brw_store_data_imm32(brw, bo, offset, imm);
294 brw_store_data_imm64(brw, bo, offset, imm);
284 store_query_result_imm(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, GLenum ptype, uint64_t imm) argument
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0;
129 if (isIntS32Immediate(N.getOperand(1), imm))
145 /// a signed 32-bit displacement [r+imm], and if it is not better
154 int32_t imm = 0; local
155 if (isIntS32Immediate(N.getOperand(1), imm)) {
156 Disp = CurDAG->getTargetConstant(imm, MVT::i32);
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeMCCodeEmitter.cpp86 void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const;
126 EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const { argument
127 int32_t val = (int32_t)imm.getImm();
/external/valgrind/none/tests/amd64/
H A Daes.c224 static void AESKEYGENASSIST(int imm, char* s_argL, char* s_exp) argument
236 if (imm == 1)
247 else if (imm == 2)
258 else if (imm == 8)
276 printf ("aeskeygenassist %d %s result %s\n", imm, s_argL, s_res);
282 int imm; // only for aeskeygenassist member in struct:Aes_Args
365 AESKEYGENASSIST(aes_args[i].imm, aes_args[i].argL, "");
/external/vixl/src/
H A Dutils-vixl.cc131 unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size) { argument
135 if ((imm & 0xffff) == 0) {
138 imm >>= 16;
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp34 static unsigned translateShiftImm(unsigned imm) { argument
36 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
38 if (imm == 0)
40 return imm;
56 O << "<imm:";
121 O << ", " << markup("<imm:") << "#"
279 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
330 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
332 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
391 O << ", " << markup("<imm
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/external/llvm/lib/Target/Sparc/
H A DSparc.h150 inline static unsigned HI22(int64_t imm) { argument
151 return (unsigned)((imm >> 10) & ((1 << 22)-1));
154 inline static unsigned LO10(int64_t imm) { argument
155 return (unsigned)(imm & 0x3FF);
158 inline static unsigned HIX22(int64_t imm) { argument
159 return HI22(~imm);
162 inline static unsigned LOX10(int64_t imm) { argument
163 return ~LO10(~imm);

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