| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 404 float reg_width, float reg_height,
408 buf[1] = buf[0] + reg_width / img_width;
422 unsigned reg_width, unsigned reg_height,
431 reg_width, reg_height,
439 verts[4] = dst_x_offset + reg_width;
444 verts[8] = dst_x_offset + reg_width;
499 unsigned reg_width,
516 if (reg_width + src_x_offset > src_width)
517 reg_width = src_width - src_x_offset;
520 if (reg_width
402 calc_tex_coords(float img_width, float img_height, float x, float y, float reg_width, float reg_height, unsigned flip_y, float *buf) argument
418 emit_draw_packet(struct r200_context *r200, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
482 r200_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, mesa_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, mesa_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_blit.c | 252 float reg_width, float reg_height,
256 buf[1] = buf[0] + reg_width / img_width;
270 unsigned reg_width, unsigned reg_height,
279 reg_width, reg_height,
287 verts[4] = dst_x_offset + reg_width;
292 verts[8] = dst_x_offset + reg_width;
350 unsigned reg_width,
367 if (reg_width + src_x_offset > src_width)
368 reg_width = src_width - src_x_offset;
371 if (reg_width
250 calc_tex_coords(float img_width, float img_height, float x, float y, float reg_width, float reg_height, unsigned flip_y, float *buf) argument
266 emit_draw_packet(struct r100_context *r100, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
333 r100_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, mesa_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, mesa_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_fs_reg_allocate.cpp | 49 int reg_width = dispatch_width / 8; local
52 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
471 int reg_width = v->dispatch_width / 8; local
479 if (reg_width == 2) {
533 /* Most of this allocation was written for a reg_width of 1
537 * for reg_width == 2.
539 int reg_width = dispatch_width / 8; local
541 int payload_node_count = ALIGN(this->first_non_payload_grf, reg_width);
542 int rsi = _mesa_logbase2(reg_width); /* Which compiler->fs_reg_sets[] to use */
|
| H A D | brw_fs_visitor.cpp | 138 int reg_width = dispatch_width / 8; local
143 bld.MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F),
152 write->mlen = 4 * reg_width;
156 write->mlen = 2 + 4 * reg_width;
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| H A D | brw_fs_generator.cpp | 77 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type)); local
93 const unsigned width = MIN2(reg_width, phys_width);
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| H A D | brw_fs.cpp | 956 int reg_width = dispatch_width / 8; local
957 return fs_reg(VGRF, alloc.allocate(type_size_scalar(type) * reg_width),
3971 unsigned reg_width = bld.dispatch_width() / 8;
3999 if (!inst->eot && regs_written(inst) != 4 * reg_width) {
4000 assert(regs_written(inst) % reg_width == 0);
4001 unsigned mask = ~((1 << (regs_written(inst) / reg_width)) - 1) & 0xf;
4141 if (reg_width == 2)
4142 mlen = length * reg_width - header_size;
4144 mlen = length * reg_width;
|