Searched refs:RC (Results 276 - 300 of 446) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp322 const TargetRegisterClass *RC, int SPAdj) {
324 unsigned Reg = RS->FindUnusedReg(RC);
328 Reg = RS->scavengeRegister(RC, II, SPAdj);
372 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; local
377 Reg = findScratchRegister(II, RS, RC, SPAdj);
465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; local
466 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
321 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
/external/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp214 const TargetRegisterClass *RC) const {
216 return RC->contains(Reg);
218 return MRI->getRegClass(Reg) == RC;
H A DSIInstrInfo.cpp574 const TargetRegisterClass *RC,
589 if (RI.isSGPRClass(RC)) {
592 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) {
601 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
620 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
622 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
672 const TargetRegisterClass *RC,
687 if (RI.isSGPRClass(RC)) {
690 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
692 if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC
570 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
669 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp216 unsigned RC; local
217 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
218 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetInstrInfo.h372 const TargetRegisterClass *RC,
384 const TargetRegisterClass *RC,
571 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
369 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
381 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinRegisterInfo.cpp180 const TargetRegisterClass *RC,
183 unsigned Reg = RS->FindUnusedReg(RC);
185 Reg = RS->scavengeRegister(RC, II, SPAdj);
178 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp301 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
303 DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC];
309 if (RC == &NVPTX::Int1RegsRegClass) {
311 } else if (RC == &NVPTX::Int16RegsRegClass) {
313 } else if (RC == &NVPTX::Int32RegsRegClass) {
315 } else if (RC == &NVPTX::Int64RegsRegClass) {
317 } else if (RC == &NVPTX::Float32RegsRegClass) {
319 } else if (RC == &NVPTX::Float64RegsRegClass) {
564 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
569 VRegRCMap::const_iterator I = VRegMapping.find(RC);
1672 const TargetRegisterClass *RC = MRI->getRegClass(vr); local
1691 const TargetRegisterClass *RC = TRI->getRegClass(i); local
[all...]
/external/clang/include/clang/AST/
H A DRawCommentList.h186 void addComment(const RawComment &RC, llvm::BumpPtrAllocator &Allocator);
/external/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h291 const TargetRegisterClass *RC);
H A DPasses.h308 /// The pass will examine instructions using and defining registers in RC.
310 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h250 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
788 const TargetRegisterClass *RC,
800 const TargetRegisterClass *RC,
1117 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
785 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
797 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp113 const TargetRegisterClass *RC = MRI->getRegClass(R); local
114 return RC == &Hexagon::PredRegsRegClass;
415 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); local
416 unsigned NewOutR = MRI->createVirtualRegister(RC);
H A DHexagonInstrInfo.h171 const TargetRegisterClass *RC,
180 const TargetRegisterClass *RC,
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp94 const TargetRegisterClass *RC,
101 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
112 const TargetRegisterClass *RC,
120 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
91 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
109 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
H A DMipsRegisterInfo.cpp71 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
73 switch (RC->getID()) {
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp570 const TargetRegisterClass *RC = local
572 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
574 // If cross copy register class is the same as RC, then it must be
576 // If cross copy register class is not the same as RC, then it's
582 if (DestRC != RC) {
591 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
/external/harfbuzz_ng/src/
H A Dhb-ot-shape-complex-thai.cc40 RC, enumerator in enum:thai_consonant_type_t
52 return RC;
173 T0, /* RC */
200 B1, /* RC */
/external/libogg/win32/
H A DMakefile98 RC = @RC@ macro
/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp245 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
247 unsigned VReg = MF.addLiveIn(PReg, RC);
H A DLocalStackSlotAllocation.cpp389 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); local
390 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
H A DMachineSSAUpdater.cpp115 const TargetRegisterClass *RC,
118 unsigned NewVR = MRI->createVirtualRegister(RC);
113 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
/external/llvm/unittests/Support/
H A DProgramTest.cpp152 int RC = ExecuteAndWait(MyExe, ArgV, getEnviron(), Redirects, local
156 EXPECT_EQ(0, RC);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DMachineSSAUpdater.cpp114 const TargetRegisterClass *RC,
117 unsigned NewVR = MRI->createVirtualRegister(RC);
112 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
H A DMachineVerifier.cpp751 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
754 TRI->getSubClassWithSubReg(RC, SubIdx);
757 *OS << "Register class " << RC->getName()
761 if (RC != SRC) {
763 *OS << "Register class " << RC->getName()
771 TRI->getLargestLegalSuperClass(RC);
782 if (!RC->hasSuperClassEq(DRC)) {
785 << RC->getName() << " register\n";
H A DProcessImplicitDefs.cpp276 const TargetRegisterClass* RC = MRI->getRegClass(Reg); local
277 unsigned NewVReg = MRI->createVirtualRegister(RC);

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