/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 322 const TargetRegisterClass *RC, int SPAdj) { 324 unsigned Reg = RS->FindUnusedReg(RC); 328 Reg = RS->scavengeRegister(RC, II, SPAdj); 372 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; local 377 Reg = findScratchRegister(II, RS, RC, SPAdj); 465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; local 466 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 321 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
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/external/llvm/lib/Target/AMDGPU/ |
H A D | R600MachineScheduler.cpp | 214 const TargetRegisterClass *RC) const { 216 return RC->contains(Reg); 218 return MRI->getRegClass(Reg) == RC;
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H A D | SIInstrInfo.cpp | 574 const TargetRegisterClass *RC, 589 if (RI.isSGPRClass(RC)) { 592 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) { 601 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize()); 620 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); 622 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize()); 672 const TargetRegisterClass *RC, 687 if (RI.isSGPRClass(RC)) { 690 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize()); 692 if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC 570 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 669 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 216 unsigned RC; local 217 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC); 218 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
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/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 372 const TargetRegisterClass *RC, 384 const TargetRegisterClass *RC, 571 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 369 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 381 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinRegisterInfo.cpp | 180 const TargetRegisterClass *RC, 183 unsigned Reg = RS->FindUnusedReg(RC); 185 Reg = RS->scavengeRegister(RC, II, SPAdj); 178 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 301 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 303 DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC]; 309 if (RC == &NVPTX::Int1RegsRegClass) { 311 } else if (RC == &NVPTX::Int16RegsRegClass) { 313 } else if (RC == &NVPTX::Int32RegsRegClass) { 315 } else if (RC == &NVPTX::Int64RegsRegClass) { 317 } else if (RC == &NVPTX::Float32RegsRegClass) { 319 } else if (RC == &NVPTX::Float64RegsRegClass) { 564 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 569 VRegRCMap::const_iterator I = VRegMapping.find(RC); 1672 const TargetRegisterClass *RC = MRI->getRegClass(vr); local 1691 const TargetRegisterClass *RC = TRI->getRegClass(i); local [all...] |
/external/clang/include/clang/AST/ |
H A D | RawCommentList.h | 186 void addComment(const RawComment &RC, llvm::BumpPtrAllocator &Allocator);
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/external/llvm/include/llvm/CodeGen/ |
H A D | FunctionLoweringInfo.h | 291 const TargetRegisterClass *RC);
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H A D | Passes.h | 308 /// The pass will examine instructions using and defining registers in RC. 310 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 250 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 788 const TargetRegisterClass *RC, 800 const TargetRegisterClass *RC, 1117 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 785 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 797 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 113 const TargetRegisterClass *RC = MRI->getRegClass(R); local 114 return RC == &Hexagon::PredRegsRegClass; 415 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); local 416 unsigned NewOutR = MRI->createVirtualRegister(RC);
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H A D | HexagonInstrInfo.h | 171 const TargetRegisterClass *RC, 180 const TargetRegisterClass *RC,
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 94 const TargetRegisterClass *RC, 101 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 112 const TargetRegisterClass *RC, 120 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 91 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument 109 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
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H A D | MipsRegisterInfo.cpp | 71 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 73 switch (RC->getID()) {
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 570 const TargetRegisterClass *RC = local 572 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); 574 // If cross copy register class is the same as RC, then it must be 576 // If cross copy register class is not the same as RC, then it's 582 if (DestRC != RC) { 591 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
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/external/harfbuzz_ng/src/ |
H A D | hb-ot-shape-complex-thai.cc | 40 RC, enumerator in enum:thai_consonant_type_t 52 return RC; 173 T0, /* RC */ 200 B1, /* RC */
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/external/libogg/win32/ |
H A D | Makefile | 98 RC = @RC@ macro
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/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 245 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); 247 unsigned VReg = MF.addLiveIn(PReg, RC);
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H A D | LocalStackSlotAllocation.cpp | 389 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); local 390 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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H A D | MachineSSAUpdater.cpp | 115 const TargetRegisterClass *RC, 118 unsigned NewVR = MRI->createVirtualRegister(RC); 113 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
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/external/llvm/unittests/Support/ |
H A D | ProgramTest.cpp | 152 int RC = ExecuteAndWait(MyExe, ArgV, getEnviron(), Redirects, local 156 EXPECT_EQ(0, RC);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | MachineSSAUpdater.cpp | 114 const TargetRegisterClass *RC, 117 unsigned NewVR = MRI->createVirtualRegister(RC); 112 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
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H A D | MachineVerifier.cpp | 751 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 754 TRI->getSubClassWithSubReg(RC, SubIdx); 757 *OS << "Register class " << RC->getName() 761 if (RC != SRC) { 763 *OS << "Register class " << RC->getName() 771 TRI->getLargestLegalSuperClass(RC); 782 if (!RC->hasSuperClassEq(DRC)) { 785 << RC->getName() << " register\n";
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H A D | ProcessImplicitDefs.cpp | 276 const TargetRegisterClass* RC = MRI->getRegClass(Reg); local 277 unsigned NewVReg = MRI->createVirtualRegister(RC);
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