/external/swiftshader/third_party/subzero/src/ |
H A D | IceInstARM32.h | 1185 void emitSRegsAsText(const Cfg *Func, const Variable *BaseReg, 1187 void emitSRegsOp(const Cfg *Func, const EmitForm, const Variable *BaseReg, 1199 const Variable *BaseReg, SizeT RegCount) const = 0; 1225 void emitSRegs(const Cfg *Func, const EmitForm Form, const Variable *BaseReg, 1253 void emitSRegs(const Cfg *Func, const EmitForm Form, const Variable *BaseReg,
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H A D | IceAssemblerARM32.cpp | 1125 IValueT BaseReg, IValueT Registers) { 1127 assert(BaseReg < RegARM32::getNumGPRegs()); 1130 AddressMode | (IsLoad ? L : 0) | (BaseReg << kRnShift) | 3413 const IValueT BaseReg = getEncodedSRegNum(OpBaseReg); 3414 const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register. 3415 const IValueT Rd = mask(BaseReg, 1, 4); // Top 4 bits of base register. 3419 assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs()); 3434 // cccc11001D111101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and 3449 // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
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H A D | IceAssemblerARM32.h | 701 // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and 704 bool IsLoad, IValueT BaseReg, IValueT Registers); 706 // Pattern ccccxxxxxDxxxxxxddddxxxxiiiiiiii where cccc=Cond, ddddD=BaseReg,
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H A D | IceTargetLoweringARM32.cpp | 5721 // legalize the addressing mode to [BaseReg, OffsetReg{, LSL Shamt}]. 5722 // Instead of a zeroed BaseReg, we initialize it with OffsetImm: 5725 // mov BaseReg, #OffsetImm 5726 // use of [BaseReg, OffsetReg{, LSL Shamt}] 6276 Variable *BaseReg = nullptr; 6281 BaseReg = legalizeToReg(Offset); 6283 BaseReg = makeReg(getPointerType()); 6284 _movw(BaseReg, Offset); 6285 _movt(BaseReg, Offset); 6287 From = formMemoryOperand(BaseReg, T [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 1510 unsigned BaseReg = MI.getOperand(1).getReg(); local 1512 if (MI.modifiesRegister(BaseReg, TRI)) 1538 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, 1568 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); 1573 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, 1694 BaseReg = LdSt.getOperand(1).getReg(); 1698 BaseReg = LdSt.getOperand(2).getReg(); 1537 getMemOpBaseRegImmOfs( MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const argument 1572 getMemOpBaseRegImmOfsWidth( MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 174 SDValue &BaseReg, SDValue &Opc); 391 SDValue &BaseReg, 403 BaseReg = N.getOperand(0); 414 SDValue &BaseReg, 427 BaseReg = N.getOperand(0); 1154 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, argument 1165 BaseReg = N.getOperand(0); 390 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument 413 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1093 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { argument 1095 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1143 unsigned BaseReg = MI->getOperand(1).getReg(); local 1144 if (BaseReg == 0 || BaseReg == X86::RIP) 1152 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1173 unsigned BaseReg = MI->getOperand(1).getReg(); local 1174 if (BaseReg == 0) 1179 return regIsPICBase(BaseReg, MRI);
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 83 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg, 520 SDValue& BaseReg, SDValue &Offset) { 522 BaseReg = Addr; 519 SelectGlobalValueVariableOffset(SDValue Addr, SDValue& BaseReg, SDValue &Offset) argument
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H A D | SIInstrInfo.h | 113 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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H A D | SIInstrInfo.cpp | 205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, argument 218 BaseReg = AddrReg->getReg(); 252 BaseReg = AddrReg->getReg(); 271 BaseReg = AddrReg->getReg(); 284 BaseReg = SBaseReg->getReg(); 291 BaseReg = AddrReg->getReg();
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 213 unsigned BaseReg = MI->getOperand(0).getReg(); local 215 if (MI->getOperand(i).getReg() == BaseReg) 223 printRegName(O, BaseReg);
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | RegionStore.cpp | 1555 } else if (const CXXBaseObjectRegion *BaseReg = 1559 Result = findLazyBinding(B, cast<SubRegion>(BaseReg->getSuperRegion()), 1563 Result.second = MRMgr.getCXXBaseObjectRegionWithSuper(BaseReg,
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 2295 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { argument 2297 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 2300 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), 2379 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); local 2380 if (BaseReg == 0 || BaseReg == X86::RIP) 2387 return regIsPICBase(BaseReg, MRI); 2401 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); local 2402 if (BaseReg == 0) 2407 return regIsPICBase(BaseReg, MR 4706 getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | X86MCInstLower.cpp | 780 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; local 782 BaseReg = X86::RAX; 821 .addReg(BaseReg)
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 532 SDValue &BaseReg, 546 BaseReg = Handle.getValue(); 560 BaseReg = N.getOperand(0); 571 SDValue &BaseReg, 584 BaseReg = N.getOperand(0); 531 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument 570 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 2943 unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) 2947 BaseReg = getBaseAndOffset(&LdSt, OffsetVal, AccessSize); 2949 return BaseReg != 0; 2942 getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 8720 unsigned BaseReg; local 8722 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; 8724 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; 8728 .addReg(BaseReg)
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