/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 738 const SDValue Op, APInt &KnownZero, APInt &KnownOne, 740 switch (Op.getOpcode()) { 745 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1); 746 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1); 752 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1)); 759 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); 769 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 779 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); 1616 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) { argument 1617 assert((Op 737 computeKnownBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 1730 LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const argument 1736 LowerXOR(SDValue Op, SelectionDAG &DAG) argument 1795 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument 1831 LowerXALUO(SDValue Op, SelectionDAG &DAG) argument 1862 LowerPREFETCH(SDValue Op, SelectionDAG &DAG) argument 1888 LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const argument 1898 LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const argument 1916 LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) argument 1954 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const argument 1982 LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument 2010 LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const argument 2042 LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const argument 2074 LowerBITCAST(SDValue Op, SelectionDAG &DAG) argument 2211 LowerMUL(SDValue Op, SelectionDAG &DAG) argument 2280 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument 2305 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument 3358 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 3428 LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 3503 LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 3603 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 3612 LowerBR_CC(SDValue Op, SelectionDAG &DAG) const argument 3743 LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const argument 3818 LowerCTPOP(SDValue Op, SelectionDAG &DAG) const argument 3852 LowerSETCC(SDValue Op, SelectionDAG &DAG) const argument 4065 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument 4076 LowerSELECT(SDValue Op, SelectionDAG &DAG) const argument 4117 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const argument 4145 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument 4186 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument 4209 LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const argument 4222 LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const argument 4291 LowerVASTART(SDValue Op, SelectionDAG &DAG) const argument 4297 LowerVACOPY(SDValue Op, SelectionDAG &DAG) const argument 4313 LowerVAARG(SDValue Op, SelectionDAG &DAG) const argument 4376 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument 4405 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument 4429 LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const argument 4487 LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const argument 4754 LowerAsmOperandForConstraint( SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument 4927 ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const argument 5370 tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) argument 5503 GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 5578 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const argument 5752 LowerVectorAND(SDValue Op, SelectionDAG &DAG) const argument 5944 LowerVectorOR(SDValue Op, SelectionDAG &DAG) const argument 6047 NormalizeBuildVector(SDValue Op, SelectionDAG &DAG) argument 6069 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const argument 6445 LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const argument 6479 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const argument 6515 LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const argument 6584 getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) argument 6604 isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) argument 6615 isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) argument 6623 LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const argument 6767 LowerVSETCC(SDValue Op, SelectionDAG &DAG) const argument 8261 isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) argument 8304 isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) argument 8317 performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) argument 8944 tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV, unsigned Op, SelectionDAG &DAG) argument 9095 unsigned Op = VectorOp->getOpcode(); local 9648 getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) argument 9984 getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const argument 10028 getPostIndexedAddressParts( SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument 10056 SDValue Op = N->getOperand(0); local [all...] |
/external/swiftshader/third_party/LLVM/lib/VMCore/ |
H A D | Instructions.cpp | 125 Op<-1>().set(0); 261 Op<-1>() = Func; 283 Op<-1>() = Func; 516 Op<-3>() = Fn; 517 Op<-2>() = IfNormal; 518 Op<-1>() = IfException; 593 Op<0>() = RI.Op<0>(); 602 Op<0>() = retVal; 609 Op< 1792 Create(BinaryOps Op, Value *S1, Value *S2, const Twine &Name, Instruction *InsertBefore) argument 1800 Create(BinaryOps Op, Value *S1, Value *S2, const Twine &Name, BasicBlock *InsertAtEnd) argument 1808 CreateNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument 1816 CreateNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument 1824 CreateNSWNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument 1830 CreateNSWNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument 1836 CreateNUWNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument 1842 CreateNUWNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument 1848 CreateFNeg(Value *Op, const Twine &Name, Instruction *InsertBefore) argument 1856 CreateFNeg(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument 1864 CreateNot(Value *Op, const Twine &Name, Instruction *InsertBefore) argument 1879 CreateNot(Value *Op, const Twine &Name, BasicBlock *InsertAtEnd) argument 2840 Create(OtherOps Op, unsigned short predicate, Value *S1, Value *S2, const Twine &Name, Instruction *InsertBefore) argument 2861 Create(OtherOps Op, unsigned short predicate, Value *S1, Value *S2, const Twine &Name, BasicBlock *InsertAtEnd) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 166 LowerOperation(SDValue Op, SelectionDAG &DAG) const { argument 167 switch (Op.getOpcode()) 169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 173 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 174 case ISD::LOAD: return LowerLOAD(Op, DAG); 175 case ISD::STORE: return LowerSTORE(Op, DAG); 176 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DA 214 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument 246 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 264 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 298 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument 309 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument 331 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const argument 393 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument 493 LowerSTORE(SDValue Op, SelectionDAG &DAG) const argument 552 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const argument 569 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const argument 591 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, SDValue &Addend1, bool requireIntermediatesHaveOneUse) argument 745 LowerVAARG(SDValue Op, SelectionDAG &DAG) const argument 769 LowerVASTART(SDValue Op, SelectionDAG &DAG) const argument 781 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument 795 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const argument 800 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const argument 1514 computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 163 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, argument 165 switch (Op.getOpcode()) { 166 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 167 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 168 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 169 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 689 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { argument 690 SDValue Chain = Op.getOperand(0); 691 ISD::CondCode CC = cast<CondCodeSDNode>(Op 703 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument 725 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 764 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const argument 776 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument [all...] |
/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeGenInstruction.cpp | 155 CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) { argument 156 if (Op.empty() || Op[0] != '$') 157 throw TheDef->getName() + ": Illegal operand name: '" + Op + "'"; 159 std::string OpName = Op.substr(1); 167 throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'"; 178 " whole operand part of complex operand '" + Op + "'"; 187 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'"; 195 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'"; 209 std::pair<unsigned,unsigned> Op local 276 std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false); local [all...] |
/external/eigen/Eigen/src/SparseCore/ |
H A D | SparseUtil.h | 21 #define EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(Derived, Op) \ 23 EIGEN_STRONG_INLINE Derived& operator Op(const Eigen::SparseMatrixBase<OtherDerived>& other) \ 25 return Base::operator Op(other.derived()); \ 27 EIGEN_STRONG_INLINE Derived& operator Op(const Derived& other) \ 29 return Base::operator Op(other); \ 32 #define EIGEN_SPARSE_INHERIT_SCALAR_ASSIGNMENT_OPERATOR(Derived, Op) \ 34 EIGEN_STRONG_INLINE Derived& operator Op(const Other& scalar) \ 36 return Base::operator Op(scalar); \
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/external/llvm/include/llvm/MC/ |
H A D | MCWinEH.h | 27 Instruction(unsigned Op, MCSymbol *L, unsigned Reg, unsigned Off) argument 28 : Label(L), Offset(Off), Register(Reg), Operation(Op) {}
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/external/llvm/lib/Bitcode/Writer/ |
H A D | ValueEnumerator.cpp | 63 for (const Value *Op : C->operands()) 64 if (!isa<BasicBlock>(Op) && !isa<GlobalValue>(Op)) 65 orderValue(Op, OM); 129 for (const Value *Op : I.operands()) 130 if ((isa<Constant>(*Op) && !isa<GlobalValue>(*Op)) || 131 isa<InlineAsm>(*Op)) 132 orderValue(Op, OM); 225 for (const Value *Op 601 auto *Op = cast<MDNode>(*I); local [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 44 unsigned Op; local 46 Op = NVPTX::IMOV1rr; 48 Op = NVPTX::IMOV16rr; 50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr 53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr 56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr 59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr 64 BuildMI(MBB, I, DL, get(Op), DestReg)
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/external/skia/include/core/ |
H A D | SkRegion.h | 239 enum Op { enum in class:SkRegion 254 * Set this region to the result of applying the Op to this region and the 258 bool op(const SkIRect& rect, Op op) { 269 * Set this region to the result of applying the Op to this region and the 273 bool op(int left, int top, int right, int bottom, Op op) { 280 * Set this region to the result of applying the Op to this region and the 284 bool op(const SkRegion& rgn, Op op) { return this->op(*this, rgn, op); } 287 * Set this region to the result of applying the Op to the specified 291 bool op(const SkIRect& rect, const SkRegion& rgn, Op); 294 * Set this region to the result of applying the Op t [all...] |
/external/skia/src/gpu/ |
H A D | GrSWMaskHelper.h | 53 void drawRect(const SkRect& rect, SkRegion::Op op, GrAA, uint8_t alpha); 56 void drawShape(const GrShape&, SkRegion::Op op, GrAA, uint8_t alpha);
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/external/swiftshader/third_party/LLVM/include/llvm/Bitcode/ |
H A D | BitstreamReader.h | 448 void ReadAbbreviatedLiteral(const BitCodeAbbrevOp &Op, argument 450 assert(Op.isLiteral() && "Not a literal"); 452 Vals.push_back(Op.getLiteralValue()); 455 void ReadAbbreviatedField(const BitCodeAbbrevOp &Op, argument 457 assert(!Op.isLiteral() && "Use ReadAbbreviatedLiteral for literals!"); 460 switch (Op.getEncoding()) { 463 Vals.push_back(Read((unsigned)Op.getEncodingData())); 466 Vals.push_back(ReadVBR64((unsigned)Op.getEncodingData())); 495 const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i); local 496 if (Op [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXISelLowering.cpp | 109 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { argument 110 switch (Op.getOpcode()) { 114 return LowerSETCC(Op, DAG); 116 return LowerGlobalAddress(Op, DAG); 147 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { argument 148 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer"); 149 SDValue Op0 = Op.getOperand(0); 150 SDValue Op1 = Op.getOperand(1); 151 SDValue Op2 = Op.getOperand(2); 152 DebugLoc dl = Op 170 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 116 static unsigned getRelaxedOpcodeBranch(unsigned Op) { argument 117 switch (Op) { 119 return Op; 141 static unsigned getRelaxedOpcodeArith(unsigned Op) { argument 142 switch (Op) { 144 return Op; 210 static unsigned getRelaxedOpcode(unsigned Op) { argument 211 unsigned R = getRelaxedOpcodeArith(Op); 212 if (R != Op) 214 return getRelaxedOpcodeBranch(Op); 234 const MCOperand &Op = Inst.getOperand(i); local [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | ValueMapper.cpp | 212 Metadata &getFwdReference(MDNode &Op); 269 /// If \c Op is already mapped, return the mapping. If it's not an \a 273 /// \return None if \c Op is an unmapped uniqued \a MDNode. 274 /// \post getMappedOp(Op) only returns None if this returns None. 275 Optional<Metadata *> tryToMapOperand(const Metadata *Op); 287 Optional<Metadata *> getMappedOp(const Metadata *Op) const; 431 Value *Op = C->getOperand(OpNo); local 432 Mapped = mapValueOrNull(Op); 435 if (Mapped != Op) 516 Optional<Metadata *> MDNodeMapper::tryToMapOperand(const Metadata *Op) { argument 572 getFwdReference(MDNode &Op) argument 603 MDNode::op_iterator Op; ///< Current operand of \\c N. member in struct:__anon13578::POTWorklistEntry 648 Metadata *Op = *I++; // Increment even on early return. local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 482 static bool isFloatingPointZero(SDValue Op) { argument 483 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 485 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 487 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 494 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 495 /// true if Op is undef or if it matches the specified value. 496 static bool isConstantOrUndef(int Op, int Val) { argument 497 return Op < 0 || Op 794 isIntS16Immediate(SDValue Op, short &Imm) argument 1158 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument 1173 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const argument 1184 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument 1197 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 1230 LowerSETCC(SDValue Op, SelectionDAG &DAG) const argument 1273 LowerVAARG(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 1378 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const argument 1383 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const argument 1422 LowerVASTART(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 2330 isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) argument 3466 LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 3548 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 3571 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument 3644 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const argument 3680 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const argument 3730 LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const argument 3794 LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const argument 3823 LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const argument 3852 LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const argument 3953 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const argument 4195 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const argument 4361 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument 4429 LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const argument 4447 LowerMUL(SDValue Op, SelectionDAG &DAG) const argument 4508 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument 5463 computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 5591 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue>&Ops, SelectionDAG &DAG) const argument 5707 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument 5741 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument [all...] |
/external/skia/include/private/ |
H A D | GrAuditTrail.h | 107 struct Op { struct in struct:GrAuditTrail::OpInfo 114 SkTArray<Op> fOps; 126 struct Op { struct in class:GrAuditTrail 135 typedef SkTArray<std::unique_ptr<Op>, true> OpPool; 137 typedef SkTArray<Op*> Ops;
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/external/skia/tests/ |
H A D | PrimitiveProcessorTest.cpp | 27 class Op : public GrMeshDrawOp { class in namespace:__anon18504 31 const char* name() const override { return "Dummy Op"; } 34 return std::unique_ptr<GrDrawOp>(new Op(numAttribs)); 46 Op(int numAttribs) : INHERITED(ClassID()), fNumAttribs(numAttribs) { function in class:__anon18504::Op 130 renderTargetContext->priv().testingOnly_addDrawOp(Op::Make(attribCnt)); 137 renderTargetContext->priv().testingOnly_addDrawOp(Op::Make(attribCnt + 1));
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.h | 77 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG, 115 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 123 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 130 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 144 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | TestAfterDivZeroChecker.cpp | 108 BinaryOperator::Opcode Op = BO->getOpcode(); local 109 if (Op == BO_Div || Op == BO_Rem || Op == BO_DivAssign || 110 Op == BO_RemAssign) { 205 BinaryOperator::Opcode Op = B->getOpcode(); local 206 if (Op == BO_Div || Op == BO_Rem || Op == BO_DivAssign || 207 Op [all...] |
/external/skia/src/core/ |
H A D | SkLiteDL.cpp | 43 // Helper for getting back at arrays which have been copy_v'd together after an Op. 65 struct Op { struct in namespace:__anon18188 69 static_assert(sizeof(Op) == 4, ""); 71 struct SetDrawFilter final : Op { 84 struct Save final : Op { 88 struct Restore final : Op { 92 struct SaveLayer final : Op { 116 struct Concat final : Op { 122 struct SetMatrix final : Op { 130 struct Translate final : Op { [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 40 static inline const char *getAddrOpcStr(AddrOpc Op) { argument 41 return Op == sub ? "-" : ""; 44 static inline const char *getShiftOpcStr(ShiftOpc Op) { argument 45 switch (Op) { 55 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { argument 56 switch (Op) { 114 static inline unsigned getSORegOffset(unsigned Op) { 115 return Op >> 3; 117 static inline ShiftOpc getSORegShOp(unsigned Op) { 118 return (ShiftOpc)(Op [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 543 // Returns Op if setcc is not a floating point comparison. 544 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { argument 546 if (Op.getOpcode() != ISD::SETCC) 547 return Op; 549 SDValue LHS = Op.getOperand(0); 552 return Op; 554 SDValue RHS = Op.getOperand(1); 555 SDLoc DL(Op); 559 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 694 // Op' 892 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument 1665 lowerBR_JT(SDValue Op, SelectionDAG &DAG) const argument 1697 lowerBRCOND(SDValue Op, SelectionDAG &DAG) const argument 1722 lowerSELECT(SDValue Op, SelectionDAG &DAG) const argument 1735 lowerSETCC(SDValue Op, SelectionDAG &DAG) const argument 1749 lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 1793 lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument 1805 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 1887 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const argument 1899 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument 1920 lowerVASTART(SDValue Op, SelectionDAG &DAG) const argument 1935 lowerVAARG(SDValue Op, SelectionDAG &DAG) const argument 1995 lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 2042 lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 2093 lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const argument 2101 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument 2115 lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument 2139 lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const argument 2163 lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const argument 2173 lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const argument 2204 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument 2263 lowerLOAD(SDValue Op, SelectionDAG &DAG) const argument 2388 lowerSTORE(SDValue Op, SelectionDAG &DAG) const argument 2401 lowerADD(SDValue Op, SelectionDAG &DAG) const argument 2423 lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const argument 3569 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue>&Ops, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 521 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) argument 919 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, argument 942 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 957 HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const { argument 958 SDNode *Node = Op.getNode(); 1003 return Op; 1009 SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op, argument 1011 SDValue Chain = Op.getOperand(0); 1012 SDValue Addr = Op.getOperand(1); 1015 SDLoc DL(Op); 1020 LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const argument 1035 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const argument 1206 LowerVASTART(SDValue Op, SelectionDAG &DAG) const argument 1241 LowerCTPOP(SDValue Op, SelectionDAG &DAG) const argument 1252 LowerSETCC(SDValue Op, SelectionDAG &DAG) const argument 1302 LowerVSELECT(SDValue Op, SelectionDAG &DAG) const argument 1320 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument 1406 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument 1424 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const argument 1437 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument 1463 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument 1481 LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const argument 1488 LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const argument 1521 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument 1537 LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const argument 1681 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 2278 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) argument 2338 LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) argument 2394 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const argument 2532 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const argument 2593 LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const argument 2667 LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const argument 2732 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const argument 2760 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument [all...] |
/external/eigen/unsupported/Eigen/CXX11/src/util/ |
H A D | CXX11Meta.h | 412 template<typename Op, typename A, typename B, std::size_t N, int... n> 413 constexpr inline array<decltype(Op::run(A(), B())),N> h_array_zip(array<A, N> a, array<B, N> b, numeric_list<int, n...>) 415 return array<decltype(Op::run(A(), B())),N>{{ Op::run(array_get<n>(a), array_get<n>(b))... }}; 418 template<typename Op, typename A, typename B, std::size_t N> 419 constexpr inline array<decltype(Op::run(A(), B())),N> array_zip(array<A, N> a, array<B, N> b) 421 return h_array_zip<Op>(a, b, typename gen_numeric_list<int, N>::type()); 426 template<typename Reducer, typename Op, typename A, typename B, std::size_t N, int... n> 427 constexpr inline auto h_array_zip_and_reduce(array<A, N> a, array<B, N> b, numeric_list<int, n...>) -> decltype(reduce<Reducer, typename id_numeric<int,n,decltype(Op::run(A(), B()))>::type...>::run(Op [all...] |