/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | neont2-mul-encoding.s | 7 @ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09] 8 vmul.i16 d16, d16, d17 15 @ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09] 16 vmul.i16 q8, q8, q9
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H A D | neon-sub-encoding.s | 5 @ CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] 6 vsub.i16 d16, d17, d16 15 @ CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] 16 vsub.i16 q8, q8, q9 97 @ CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2] 98 vsubhn.i16 d16, q8, q9 103 @ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3] 104 vrsubhn.i16 d16, q8, q9
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H A D | neont2-shift-encoding.s | 15 @ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0xdf,0xef,0x30,0x05] 16 vshl.i16 d16, d16, #15 31 @ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0xdf,0xef,0x70,0x05] 32 vshl.i16 q8, q8, #15 83 @ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0xf6,0xff,0x20,0x03] 84 vshll.i16 q8, d16, #16 87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08] 88 vshrn.i16 d16, q8, #8 157 @ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x08] 158 vrshrn.i16 d1 [all...] |
/external/libhevc/common/arm/ |
H A D | ihevc_intra_pred_filters_luma_mode_11_to_17.s | 330 vrshrn.i16 d24, q12, #5 @round shft (row 0) 341 vrshrn.i16 d22, q11, #5 @round shft (row 1) 352 vrshrn.i16 d20, q10, #5 @round shft (row 2) 363 vrshrn.i16 d18, q9, #5 @round shft (row 3) 374 vrshrn.i16 d24, q12, #5 @round shft (row 4) 385 vrshrn.i16 d22, q11, #5 @round shft (row 5) 396 vrshrn.i16 d20, q10, #5 @round shft (row 6) 397 vrshrn.i16 d18, q9, #5 @round shft (row 7) 453 vrshrn.i16 d24, q11, #5 @round shft (row 5) 474 vrshrn.i16 d2 [all...] |
H A D | ihevc_intra_pred_luma_mode_3_to_9.s | 220 vrshrn.i16 d24, q12, #5 @round shft (row 0) 231 vrshrn.i16 d22, q11, #5 @round shft (row 1) 242 vrshrn.i16 d20, q10, #5 @round shft (row 2) 253 vrshrn.i16 d18, q9, #5 @round shft (row 3) 264 vrshrn.i16 d24, q12, #5 @round shft (row 4) 275 vrshrn.i16 d22, q11, #5 @round shft (row 5) 286 vrshrn.i16 d20, q10, #5 @round shft (row 6) 287 vrshrn.i16 d18, q9, #5 @round shft (row 7) 343 vrshrn.i16 d22, q11, #5 @round shft (row 5) 365 vrshrn.i16 d2 [all...] |
H A D | ihevc_intra_pred_filters_chroma_mode_11_to_17.s | 332 vrshrn.i16 d24, q12, #5 @round shft (row 0) 343 vrshrn.i16 d22, q11, #5 @round shft (row 1) 354 vrshrn.i16 d20, q10, #5 @round shft (row 2) 365 vrshrn.i16 d18, q9, #5 @round shft (row 3) 378 vrshrn.i16 d24, q12, #5 @round shft (row 4) 389 vrshrn.i16 d22, q11, #5 @round shft (row 5) 400 vrshrn.i16 d20, q10, #5 @round shft (row 6) 401 vrshrn.i16 d18, q9, #5 @round shft (row 7) 463 vrshrn.i16 d24, q11, #5 @round shft (row 5) 492 vrshrn.i16 d2 [all...] |
H A D | ihevc_itrans_recon_4x4_ttype1.s | 140 vmov.i16 d4[0],r8 142 vmov.i16 d4[1],r9 144 vmov.i16 d4[2],r10 146 vmov.i16 d4[3],r11
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 48 if (VT==MVT::i16) retval=2; 108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass); 115 // SPU has no sign or zero extended loads for i1, i8, i16: 125 setTruncStoreAction(MVT::i128, MVT::i16, Expand); 171 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 186 setOperationAction(ISD::SREM, MVT::i16, Expand); 187 setOperationAction(ISD::UREM, MVT::i16, Expand); 188 setOperationAction(ISD::SDIV, MVT::i16, Expand); 189 setOperationAction(ISD::UDIV, MVT::i16, Expand); 190 setOperationAction(ISD::SDIVREM, MVT::i16, Expan [all...] |
/external/libmpeg2/common/arm/ |
H A D | impeg2_mem_func.s | 151 vmov.i16 q0, #0
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H A D | icv_sad_a9.s | 97 vadd.i16 d0, d1, d0
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/external/libavc/encoder/arm/ |
H A D | ih264e_evaluate_intra4x4_modes_a9q.s | 159 vadd.i16 d28, d29, d28 185 vadd.i16 d28, d29, d28 221 vadd.i16 d28, d29, d28 270 vadd.i16 d28, d29, d28 299 vadd.i16 d28, d29, d28 337 vadd.i16 d28, d29, d28 374 vadd.i16 d28, d29, d28 402 vadd.i16 d28, d29, d28 427 vmov.i16 d28[0], r14 438 vadd.i16 d2 [all...] |
H A D | ih264e_evaluate_intra16x16_modes_a9q.s | 183 vadd.i16 q9, q9, q8 @/VERT 184 vadd.i16 d18, d19, d18 @/VERT 186 vadd.i16 q14, q13, q14 @/HORZ 187 vadd.i16 d28, d29, d28 @/HORZ 193 vadd.i16 q12, q11, q12 @/DC 196 vadd.i16 d24, d24, d25 @/DC
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H A D | ih264e_evaluate_intra_chroma_modes_a9q.s | 237 vadd.i16 q9, q9, q8 @/VERT 238 vadd.i16 q7, q13, q7 @/HORZ 239 vadd.i16 q12, q11, q12 @/DC 240 vadd.i16 d18, d19, d18 @/VERT 241 vadd.i16 d14, d15, d14 @/HORZ 242 vadd.i16 d24, d24, d25 @/DC
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/external/libvpx/libvpx/vpx_dsp/arm/ |
H A D | loopfilter_16_neon.asm | 517 vsub.i16 q15, q10 519 vadd.i16 q15, q14 523 vsub.i16 q15, q10 524 vadd.i16 q15, q14 530 vadd.i16 q15, q14 536 vadd.i16 q15, q14 542 vadd.i16 q15, q14 565 vadd.i16 q12, q13 566 vadd.i16 q15, q14 568 vadd.i16 q1 [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 746 case MVT::i16: 774 case MVT::i16: 803 case MVT::i16: 826 case MVT::i16: 855 case MVT::i16: 878 case MVT::i16: 992 case MVT::i16: 1016 case MVT::i16: 1045 case MVT::i16: 1069 case MVT::i16 [all...] |
/external/llvm/test/MC/ARM/ |
H A D | neont2-shift-encoding.s | 15 @ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0xdf,0xef,0x30,0x05] 16 vshl.i16 d16, d16, #15 31 @ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0xdf,0xef,0x70,0x05] 32 vshl.i16 q8, q8, #15 83 @ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0xf6,0xff,0x20,0x03] 84 vshll.i16 q8, d16, #16 87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08] 88 vshrn.i16 d16, q8, #8 157 @ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x08] 158 vrshrn.i16 d1 [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinISelLowering.cpp | 51 addRegisterClass(MVT::i16, BF::D16RegisterClass); 67 // i16 registers don't do much 68 setOperationAction(ISD::AND, MVT::i16, Promote); 69 setOperationAction(ISD::OR, MVT::i16, Promote); 70 setOperationAction(ISD::XOR, MVT::i16, Promote); 71 setOperationAction(ISD::CTPOP, MVT::i16, Promote); 74 setOperationAction(ISD::CTLZ, MVT::i16, Promote); 75 setOperationAction(ISD::CTTZ, MVT::i16, Promote); 76 setOperationAction(ISD::SETCC, MVT::i16, Promote); 79 setOperationAction(ISD::SDIV, MVT::i16, Expan [all...] |
H A D | BlackfinISelLowering.h | 35 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; }
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXSelectionDAGInfo.cpp | 101 VT = MVT::i16; 123 VT = MVT::i16;
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/external/llvm/include/llvm/Support/ |
H A D | DataTypes.h | 153 # define INT16_C(C) C##i16
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/external/swiftshader/third_party/LLVM/include/llvm/Support/ |
H A D | DataTypes.h | 153 # define INT16_C(C) C##i16
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/external/swiftshader/third_party/LLVM/include-android/llvm/Support/ |
H A D | DataTypes.h | 152 # define INT16_C(C) C##i16
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/external/swiftshader/third_party/LLVM/include-linux/llvm/Support/ |
H A D | DataTypes.h | 152 # define INT16_C(C) C##i16
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/external/swiftshader/third_party/LLVM/include-osx/llvm/Support/ |
H A D | DataTypes.h | 152 # define INT16_C(C) C##i16
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/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/Support/ |
H A D | DataTypes.h | 153 #define INT16_C(C) C##i16
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