Searched refs:RC1 (Results 1 - 5 of 5) sorted by relevance
/external/ltp/testcases/commands/mail/ |
H A D | mail_tests.sh | 101 RC1=0 143 RC1=0 169 RC1=$(awk '/^>N/ {IGNORECASE=1; print match($3, "Mailer-Daemon")}' \ 172 RC1=$(awk '/^>N/ {IGNORECASE=1; print match($3 $4 $5, "MailDelivery(Subsys|System)")}' \ 196 if [ -z "$RC1" -a -z "$RC2" -a -z "$RC3" ]; then 209 if [ $RC1 -ne 0 -a $RC2 -ne 0 ] || [ $RC1 -ne 0 -a $RC3 -ne 0 ]; then 230 RC1=0 250 RC1=$(awk '/^>N/ {IGNORECASE=1; print match($3, "Mailer-Daemon")}' \ 253 RC1 [all...] |
/external/ltp/testcases/kernel/security/integrity/ima/tests/ |
H A D | ima_policy.sh | 93 wait "$p1"; RC1=$? 95 if [ $RC1 -eq 0 ] && [ $RC2 -eq 0 ]; then 97 elif [ $RC1 -eq 0 ] || [ $RC2 -eq 0 ]; then
|
/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1873 CodeGenRegisterClass *RC1 = RC; local 1875 if (RC1 == RC2) 1878 // Compute the set intersection of RC1 and RC2. 1879 const CodeGenRegister::Vec &Memb1 = RC1->getMembers(); 1890 // If RC1 and RC2 have different spill sizes or alignments, use the 1891 // larger size for sub-classing. If they are equal, prefer RC1. 1892 if (RC2->SpillSize > RC1->SpillSize || 1893 (RC2->SpillSize == RC1->SpillSize && 1894 RC2->SpillAlignment > RC1->SpillAlignment)) 1895 std::swap(RC1, RC [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenInsert.cpp | 316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); local 317 uint16_t W1 = RC1.width(), W2 = RC2.width(); 319 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; 334 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); local 336 uint16_t W1 = RC1.width(), W2 = RC2.width(); 350 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2];
|
H A D | HexagonBitSimplify.cpp | 159 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1, 268 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, argument 272 // If RC1[i] is "bottom", it cannot be proven equal to RC2[i]. 273 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0) 278 if (RC1[B1+i] != RC2[B2+i])
|
Completed in 232 milliseconds