| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 25 ADDC = 0x01, enumerator in enum:llvm::LPAC::AluCode
81 case ADDC:
107 .Case("addc", ADDC)
124 return AluCode::ADDC;
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| /external/libedit/src/ |
| H A D | keymacro.c | 628 #define ADDC(c) \ macro
644 ADDC(sep[0]);
647 ADDC('^');
648 ADDC('@');
665 ADDC(sep[1]);
667 ADDC('\0');
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 201 // like ADDC/SUBC, which indicate the carry result is always false.
208 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 906 case ISD::ADDC:
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 207 /// like ADDC/SUBC, which indicate the carry result is always false.
214 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| H A D | MBlazeDelaySlotFiller.cpp | 196 op == MBlaze::ADDC || op == MBlaze::ADDIC ||
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 199 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| H A D | MipsSEISelDAGToDAG.cpp | 245 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeSPARC_32.c | 100 return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS));
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| H A D | sljitNativePPC_32.c | 119 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2));
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| H A D | sljitNativePPC_64.c | 240 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2));
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsISelDAGToDAG.cpp | 213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_eu.h | 187 ALU2(ADDC)
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| H A D | brw_fs_builder.h | 452 ALU2_ACC(ADDC)
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| H A D | brw_vec4.h | 227 EMIT2(ADDC)
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| H A D | brw_vec4_builder.h | 398 ALU2_ACC(ADDC)
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 74 ADDC, // Add with carry enumerator in enum:llvm::ARMISD::NodeType
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 71 ADDC, // Add with carry
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1142 case ISD::ADDC:
1277 TLI.isOperationLegalOrCustom(ISD::ADDC,
1282 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1512 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1514 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1519 ISD::ADDC : ISD::SUBC,
1525 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1573 if (N->getOpcode() == ISD::ADDC) {
1574 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 226 case ISD::ADDC: return "addc";
|
| H A D | LegalizeIntegerTypes.cpp | 1387 case ISD::ADDC:
1736 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1738 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1743 ISD::ADDC : ISD::SUBC,
1749 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1829 if (N->getOpcode() == ISD::ADDC) {
1830 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 90 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 99 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| H A D | MBlazeDisassembler.cpp | 41 MBlaze::ADD, MBlaze::RSUB, MBlaze::ADDC, MBlaze::RSUBC, //00,01,02,03
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1842 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1843 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1844 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1845 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1937 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
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