Searched refs:AddrBaseReg (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp197 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
222 printOperand(MI, Op + X86::AddrBaseReg, O);
H A DX86IntelInstPrinter.cpp159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
175 printOperand(MI, Op+X86::AddrBaseReg, O);
/external/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp174 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg),
330 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
424 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO))
430 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) &&
520 MI.getOperand(MemOpNo + X86::AddrBaseReg)
H A DX86AsmPrinter.cpp231 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
267 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier);
296 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
312 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier, AsmVariant);
H A DX86CallFrameOptimization.cpp380 // Note that AddrBaseReg may, counter to its name, not be a register,
385 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
386 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
H A DX86FixupLEAs.cpp254 unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
307 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
H A DX86InstrInfo.h125 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
H A DX86MCInstLower.cpp313 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
338 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
H A DX86InstrInfo.cpp2171 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2178 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
2374 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2379 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2399 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
2401 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4716 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
355 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
720 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
766 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
798 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
996 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1006 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1016 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrBaseReg) <<
[all...]
H A DX86BaseInfo.h33 AddrBaseReg = 0, enumerator in enum:llvm::X86::__anon13337
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp162 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
247 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
505 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
536 MI.getOperand(MemAddrOffset+X86::AddrBaseReg).getReg()))
549 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
H A DX86BaseInfo.h32 AddrBaseReg = 0, enumerator in enum:llvm::X86::__anon20147

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