Searched refs:BrCond (Results 1 - 17 of 17) sorted by relevance

/external/swiftshader/third_party/subzero/src/
H A DIceConditionCodesX8664.h27 enum BrCond { enum in class:Ice::CondX8664
H A DIceConditionCodesX8632.h31 enum BrCond { enum in class:Ice::CondX86
H A DIceTargetLoweringX8632Traits.h755 Cond::BrCond C1, C2;
766 static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
776 Cond::BrCond C1, C2, C3;
781 static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
939 Cond::BrCond Opposite;
H A DIceAssemblerX86Base.h58 using BrCond = typename Traits::Cond::BrCond;
300 void setcc(BrCond condition, ByteRegister dst);
301 void setcc(BrCond condition, const Address &address);
325 void cmov(Type Ty, BrCond cond, GPRRegister dst, GPRRegister src);
326 void cmov(Type Ty, BrCond cond, GPRRegister dst, const Address &src);
707 void j(BrCond condition, Label *label, bool near = kFarJump);
708 void j(BrCond condition, const ConstantRelocatable *label); // not testable.
H A DIceTargetLoweringX86Base.h66 using BrCond = typename Traits::Cond::BrCond;
563 void _br(BrCond Condition, CfgNode *TargetTrue, CfgNode *TargetFalse) {
570 void _br(BrCond Condition, CfgNode *Target) {
573 void _br(BrCond Condition, InstX86Label *Label,
593 void _cmov(Variable *Dest, Operand *Src0, BrCond Condition) {
940 void _setcc(Variable *Dest, BrCond Condition) {
1142 void setccOrConsumer(BrCond Condition, Variable *Dest, const Inst *Consumer);
1154 void lowerSelectMove(Variable *Dest, BrCond Cond, Operand *SrcT,
1156 void lowerSelectIntMove(Variable *Dest, BrCond Con
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H A DIceTargetLoweringX8664Traits.h837 Cond::BrCond C1, C2;
848 static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
858 Cond::BrCond C1, C2, C3;
863 static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
1015 Cond::BrCond Opposite;
H A DIceInstX86Base.h50 using BrCond = typename Traits::Cond::BrCond;
207 static BrCond getOppositeCondition(BrCond Cond);
380 CfgNode *TargetFalse, BrCond Condition,
397 static InstX86Br *create(Cfg *Func, CfgNode *Target, BrCond Condition,
407 static InstX86Br *create(Cfg *Func, InstX86Label *Label, BrCond Condition,
442 const InstX86Label *Label, BrCond Condition, Mode Kind);
444 BrCond Condition;
2474 BrCond Con
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H A DIceAssemblerX86BaseImpl.h210 void AssemblerX86Base<TraitsType>::setcc(BrCond condition, ByteRegister dst) {
219 void AssemblerX86Base<TraitsType>::setcc(BrCond condition,
420 void AssemblerX86Base<TraitsType>::cmov(Type Ty, BrCond cond, GPRRegister dst,
434 void AssemblerX86Base<TraitsType>::cmov(Type Ty, BrCond cond, GPRRegister dst,
3587 void AssemblerX86Base<TraitsType>::j(BrCond condition, Label *label,
3621 void AssemblerX86Base<TraitsType>::j(BrCond condition,
H A DIceInstX86BaseImpl.h44 typename InstImpl<TraitsType>::Cond::BrCond
45 InstImpl<TraitsType>::InstX86Base::getOppositeCondition(BrCond Cond) {
111 BrCond Condition, Mode Kind)
193 BrCond Condition)
366 BrCond Cond)
H A DIceTargetLoweringX86BaseImpl.h3813 void TargetX86Base<TraitsType>::setccOrConsumer(BrCond Condition,
6658 const BrCond Cond = Traits::Cond::Br_ne;
6663 void TargetX86Base<TraitsType>::lowerSelectMove(Variable *Dest, BrCond Cond,
6705 void TargetX86Base<TraitsType>::lowerSelectIntMove(Variable *Dest, BrCond Cond,
/external/llvm/lib/CodeGen/
H A DIfConversion.cpp109 /// BrCond - Conditions for end of block conditional branches.
127 SmallVector<MachineOperand, 4> BrCond; member in struct:__anon12671::IfConverter::BBInfo
455 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
457 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
517 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
656 BBI.BrCond.clear();
658 !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
661 if (BBI.BrCond.size()) {
779 if (BBI.BrCond.size()) {
785 SmallVector<MachineOperand, 4> Cond(BBI.BrCond
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H A DMachinePipeliner.cpp166 SmallVector<MachineOperand, 4> BrCond; member in struct:__anon12702::MachinePipeliner::LoopInfo
761 LI.BrCond.clear();
762 if (TII->analyzeBranch(*L.getHeader(), LI.TBB, LI.FBB, LI.BrCond))
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DIfConversion.cpp100 /// BrCond - Conditions for end of block conditional branches.
118 SmallVector<MachineOperand, 4> BrCond; member in struct:__anon19814::IfConverter::BBInfo
430 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
432 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
492 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
627 BBI.BrCond.clear();
629 !TII->AnalyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
632 if (BBI.BrCond.size()) {
720 if (BBI.BrCond.size()) {
726 SmallVector<MachineOperand, 4> Cond(BBI.BrCond
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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/
H A DSimplifyCFG.cpp974 Value *BrCond = BI->getCondition();
975 if (isa<FCmpInst>(BrCond))
1071 if (InsertPos == BrCond && !isa<PHINode>(BrCond)) {
1076 for(Value::use_iterator UI = BrCond->use_begin(), UE = BrCond->use_end();
1081 // If BrCond uses the instruction that place it just before
1096 (Builder.CreateSelect(BrCond, FalseV, HInst,
1100 (Builder.CreateSelect(BrCond, HInst, FalseV,
1438 Value *BrCond local
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp1594 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, local
1601 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1604 DAG.setRoot(BrCond);
1662 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), local
1667 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1670 DAG.setRoot(BrCond);
1931 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, local
1936 BrCond
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/external/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp1598 Value *BrCond = BI->getCondition(); local
1599 if (isa<FCmpInst>(BrCond))
1735 BrCond, TrueV, FalseV, TrueV->getName() + "." + FalseV->getName(), BI);
1768 BrCond, TrueV, FalseV, TrueV->getName() + "." + FalseV->getName(), BI);
2119 Value *BrCond = BI->getCondition(); local
2127 Builder.CreateSelect(BrCond, TrueValue, FalseValue, "retval", BI);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp1927 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1934 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1937 DAG.setRoot(BrCond);
1991 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1997 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2000 DAG.setRoot(BrCond);
2105 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2110 MVT::Other, BrCond,
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