Searched refs:CFC1 (Results 1 - 13 of 13) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 112 Opc = Mips::CFC1;
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| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 115 #define CFC1 (HI(17) | (2 << 21)) macro
1384 FAIL_IF(push_inst(compiler, CFC1 | TA(EQUAL_FLAG) | DA(FCSR_REG), EQUAL_FLAG));
1391 FAIL_IF(push_inst(compiler, CFC1 | TA(ULESS_FLAG) | DA(FCSR_REG), ULESS_FLAG));
1395 FAIL_IF(push_inst(compiler, CFC1 | TA(UGREATER_FLAG) | DA(FCSR_REG), UGREATER_FLAG));
2083 FAIL_IF(push_inst(compiler, CFC1 | TA(sugg_dst_ar) | DA(FCSR_REG), sugg_dst_ar));
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 93 Opc = Mips::CFC1;
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| /external/v8/src/mips/ |
| H A D | constants-mips.h | 497 CFC1 = ((0U << 3) + 2) << 21,
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| H A D | disasm-mips.cc | 499 if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
1352 case CFC1:
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| H A D | assembler-mips.cc | 2344 GenInstrRegister(COP1, CFC1, rt, fs);
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| H A D | simulator-mips.cc | 3543 case CFC1:
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| /external/v8/src/mips64/ |
| H A D | constants-mips64.h | 526 CFC1 = ((0U << 3) + 2) << 21,
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| H A D | disasm-mips64.cc | 515 if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
1108 case CFC1:
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| H A D | assembler-mips64.cc | 2677 GenInstrRegister(COP1, CFC1, rt, fs);
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| H A D | simulator-mips64.cc | 3431 case CFC1:
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| /external/valgrind/none/tests/mips64/ |
| H A D | fpu_control_word.stdout.exp | 1 --- CTC1, CFC1 ---
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3147 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
3148 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
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