Searched refs:FramePtr (Results 1 - 25 of 36) sorted by relevance

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/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp110 unsigned FIOperandNum, int Offset, unsigned FramePtr) {
115 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
135 .addReg(FramePtr);
153 .addReg(FramePtr);
108 replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, unsigned FramePtr) argument
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86FrameLowering.h37 unsigned FramePtr) const;
H A DX86RegisterInfo.h49 /// FramePtr - X86 physical register used as frame ptr.
51 unsigned FramePtr; member in class:llvm::X86RegisterInfo
H A DX86FrameLowering.cpp288 unsigned FramePtr) const {
341 if (HasFP && FramePtr == Reg)
466 unsigned FramePtr = RegInfo->getFrameRegister(MF);
516 if (DstReg != FramePtr || SrcReg != StackPtr)
613 unsigned FramePtr = RegInfo->getFrameRegister(MF);
698 .addReg(FramePtr, RegState::Kill)
718 // Change the rule for the FramePtr to be an "offset" rule.
720 MachineLocation FPSrc(FramePtr);
726 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
737 MachineLocation FPDst(FramePtr);
[all...]
H A DX86RegisterInfo.cpp70 FramePtr = X86::RBP;
74 FramePtr = X86::EBP;
484 if (Reg == FramePtr && TFI->hasFP(MF)) {
613 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
617 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
648 return TFI->hasFP(MF) ? FramePtr : StackPtr;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb1FrameLowering.cpp61 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
93 if (Reg == FramePtr)
102 if (Reg == FramePtr)
136 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
218 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
246 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
254 .addReg(FramePtr));
H A DARMFrameLowering.cpp137 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
169 if (Reg == FramePtr)
178 if (Reg == FramePtr)
206 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
333 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
364 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
376 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
386 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
390 .addReg(FramePtr));
874 unsigned FramePtr local
[all...]
H A DARMBaseRegisterInfo.h80 /// FramePtr - ARM physical register used as frame ptr.
81 unsigned FramePtr; member in class:llvm::ARMBaseRegisterInfo
H A DARMBaseRegisterInfo.cpp60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
111 Reserved.set(FramePtr);
141 if (FramePtr == Reg && TFI->hasFP(MF))
512 } else if (FramePtr == ARM::R7) {
517 } else { // FramePtr == ARM::R11
534 } else if (FramePtr == ARM::R7) {
539 } else { // FramePtr == ARM::R11
676 return FramePtr;
H A DARMExpandPseudoInsts.cpp822 unsigned FramePtr = RI.getFrameRegister(MF); local
828 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
831 FramePtr, -NumBytes, *TII, RI);
834 FramePtr, -NumBytes, ARMCC::AL, 0,
H A DARMAsmPrinter.cpp1056 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
1150 if (DstReg == FramePtr && FramePtr != ARM::SP)
1153 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp71 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
76 FramePtr = X86::EBP;
557 if (!MRI->canReserveReg(FramePtr))
589 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
591 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
595 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
636 assert(BasePtr == FramePtr && "Expected the FP as base register");
659 return TFI->hasFP(MF) ? FramePtr : StackPtr;
H A DX86RegisterInfo.h43 /// FramePtr - X86 physical register used as frame ptr.
45 unsigned FramePtr; member in class:llvm::final
H A DX86FrameLowering.cpp931 unsigned FramePtr = TRI->getFrameRegister(MF);
934 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
1057 // Change the rule for the FramePtr to be an "offset" rule.
1065 .addImm(FramePtr)
1073 FramePtr)
1086 // Mark the FramePtr as live-in in every block. Don't do this again for
1252 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1255 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1261 .addImm(FramePtr)
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreFrameLowering.cpp184 unsigned FramePtr = XCore::R10; local
185 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
191 MachineLocation SPDst(FramePtr);
225 unsigned FramePtr = XCore::R10; local
227 .addReg(FramePtr);
/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp107 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
163 if (Reg == FramePtr)
240 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
246 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
253 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
337 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
366 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
374 .addReg(FramePtr));
H A DARMFrameLowering.cpp311 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
370 if (Reg == FramePtr)
525 dl, TII, FramePtr, ARM::SP,
530 nullptr, MRI->getDwarfRegNum(FramePtr, true),
538 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
708 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
746 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
758 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
768 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
772 .addReg(FramePtr));
1490 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
[all...]
H A DARMAsmPrinter.cpp1139 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
1245 if (DstReg == FramePtr && FramePtr != ARM::SP)
1248 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
H A DARMExpandPseudoInsts.cpp1164 unsigned FramePtr = RI.getFrameRegister(MF); local
1170 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1173 FramePtr, -NumBytes, *TII, RI);
1176 FramePtr, -NumBytes, ARMCC::AL, 0,
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp35 static const unsigned FramePtr = XCore::R10; variable
151 FramePtr));
306 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
309 MRI->getDwarfRegNum(FramePtr, true));
385 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
/external/llvm/lib/CodeGen/
H A DSjLjEHPrepare.cpp382 Value *FramePtr = Builder.CreateConstGEP2_32(doubleUnderJBufTy, JBufPtr, 0, 0, local
386 Builder.CreateStore(Val, FramePtr, /*isVolatile=*/true);
/external/swiftshader/third_party/subzero/src/
H A DIceRegistersARM32.h92 unsigned FramePtr : 1; member in struct:Ice::ARM32::RegARM32::RegTableType
H A DIceTargetLoweringX8632Traits.h72 static constexpr RegisterSet::AllRegisters FramePtr = RegX8632::Reg_ebp; member in struct:Ice::X8632::TargetX8632Traits
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DSjLjEHPrepare.cpp617 Value *FramePtr = local
625 new StoreInst(Val, FramePtr, true, EntryBB->getTerminator());
949 Value *FramePtr = GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep", local
956 new StoreInst(Val, FramePtr, true, EntryBB->getTerminator());
/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp554 unsigned FramePtr = RegInfo->getFrameRegister(MF); local
623 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);

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