| /external/llvm/lib/Analysis/ |
| H A D | StratifiedSets.h | 451 void merge(StratifiedIndex Idx1, StratifiedIndex Idx2) { argument
452 assert(inbounds(Idx1) && inbounds(Idx2));
453 assert(&linksAt(Idx1) != &linksAt(Idx2) &&
456 // CASE 1: If the set at `Idx1` is above or below `Idx2`, we need to merge
459 if (tryMergeUpwards(Idx1, Idx2))
462 if (tryMergeUpwards(Idx2, Idx1))
465 // CASE 2: The set at `Idx1` is not in the same chain as the set at `Idx2`.
467 mergeDirect(Idx1, Idx2);
471 /// traversing above or below the set at `Idx2`.
472 void mergeDirect(StratifiedIndex Idx1, StratifiedIndex Idx2) { argument
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | TargetInstrInfoImpl.cpp | 67 unsigned Idx1, Idx2; local
68 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
79 unsigned Reg2 = MI->getOperand(Idx2).getReg();
81 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
89 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
111 MI->getOperand(Idx2).setReg(Reg1);
113 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
|
| H A D | ShadowStackGC.cpp | 71 int Idx1, int Idx2, const char *Name);
351 int Idx, int Idx2, const char *Name) {
354 ConstantInt::get(Type::getInt32Ty(Context), Idx2) };
350 CreateGEP(LLVMContext &Context, IRBuilder<> &B, Value *BasePtr, int Idx, int Idx2, const char *Name) argument
|
| /external/swiftshader/third_party/subzero/crosstest/ |
| H A D | test_vector_ops.cpp | 660 template <typename Ty, uint8_t Idx0, uint8_t Idx1, uint8_t Idx2, uint8_t Idx3,
668 Idx2 % (NumElements * 2), Idx3 % (NumElements * 2));
676 template <typename Ty, uint8_t Idx0, uint8_t Idx1, uint8_t Idx2, uint8_t Idx3,
684 Idx2 % (NumElements * 2), Idx3 % (NumElements * 2),
694 template <typename Ty, uint8_t Idx0, uint8_t Idx1, uint8_t Idx2, uint8_t Idx3,
702 V1, V2, Idx0, Idx1 % (NumElements * 2), Idx2 % (NumElements * 2),
|
| /external/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 128 unsigned Idx2) const {
136 unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
138 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 && local
140 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
145 unsigned Reg2 = MI.getOperand(Idx2).getReg();
148 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
150 bool Reg2IsKill = MI.getOperand(Idx2).isKill();
152 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
154 bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
163 MI.getDesc().getOperandConstraint(Idx2, MCO
[all...] |
| H A D | ShadowStackGCLowering.cpp | 63 Type *Ty, Value *BasePtr, int Idx1, int Idx2,
356 int Idx2,
360 ConstantInt::get(Type::getInt32Ty(Context), Idx2)};
353 CreateGEP(LLVMContext &Context, IRBuilder<> &B, Type *Ty, Value *BasePtr, int Idx, int Idx2, const char *Name) argument
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1139 CodeGenSubRegIndex *Idx2 = i2->first; local
1149 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1151 " and " + Idx2->getQualifiedName() +
1210 for (auto &Idx2 : SubRegIndices) {
1212 if (!Idx2.getComposites().empty())
1219 assert(Idx2.LaneMask == SrcMask);
1222 auto C = Composites.find(&Idx2);
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringX86Base.h | 1198 int8_t Idx0, int8_t Idx1, int8_t Idx2, int8_t Idx3, int8_t Idx4,
1204 int8_t Idx2, int8_t Idx3, int8_t Idx4,
|
| H A D | IceTargetLoweringX86BaseImpl.h | 6156 int8_t Idx0, int8_t Idx1, int8_t Idx2, int8_t Idx3, int8_t Idx4,
6162 Idx0, Idx1, Idx2, Idx3, Idx4, Idx5, Idx6, Idx7,
6185 int8_t Idx2, int8_t Idx3, int8_t Idx4, int8_t Idx5, int8_t Idx6,
6202 IDX_IN_SRC(Idx0, 0), IDX_IN_SRC(Idx1, 0), IDX_IN_SRC(Idx2, 0),
6216 if (Idx0 >= 16 || Idx1 >= 16 || Idx2 >= 16 || Idx3 >= 16 || Idx4 >= 16 ||
6223 IDX_IN_SRC(Idx0, 1), IDX_IN_SRC(Idx1, 1), IDX_IN_SRC(Idx2, 1),
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 12770 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
12771 if (Idx2 && Idx2->getZExtValue() == 0) {
[all...] |