| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 72 unsigned InReg = MI->getOperand(1).getReg(); local
76 const unsigned OrigRegs[] = {OutReg, InReg, GPR3};
106 .addReg(InReg);
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| H A D | TargetCallingConv.h | 27 static const uint64_t InReg = 1ULL<<2; ///< Passed in register member in struct:llvm::ISD::ArgFlagsTy
56 bool isInReg() const { return Flags & InReg; }
|
| /external/mesa3d/src/amd/common/ |
| H A D | ac_llvm_helper.cpp | 54 AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg);
|
| /external/swiftshader/third_party/LLVM/include/llvm/ |
| H A D | Attributes.h | 40 const Attributes InReg = 1<<3; ///< Force argument to be passed in register member in namespace:llvm::Attribute
102 ByVal | InReg | Nest | StructRet,
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.h | 32 static const uint64_t InReg = 1ULL<<2; ///< Passed in register member in struct:llvm::ISD::ArgFlagsTy
76 bool isInReg() const { return Flags & InReg; }
|
| H A D | TargetLowering.h | 2549 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
|
| /external/clang/include/clang/CodeGen/ |
| H A D | CGFunctionInfo.h | 96 bool InReg : 1; // isDirect() || isExtend() || isIndirect()
113 : TheKind(K), PaddingInReg(false), InReg(false) {
119 TheKind(Direct), PaddingInReg(false), InReg(false) {}
300 return InReg;
305 InReg = IR;
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/IR/ |
| H A D | Attributes.inc | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 104 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
128 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | VirtRegRewriter.cpp | 1808 unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1809 if (InReg == Phys) {
1818 << TRI->getName(InReg) << " for " << PrintReg(VirtReg)
1827 } else if (InReg && InReg != Phys) {
1834 << TRI->getName(InReg) << " for " << PrintReg(VirtReg)
1847 .addReg(InReg, RegState::Kill);
2359 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
2361 if (DestReg != InReg) {
2366 .addReg(InReg, RegStat
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 297 if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| H A D | Attributes.cpp | 43 if (Attrs & Attribute::InReg)
|
| /external/clang/lib/CodeGen/ |
| H A D | TargetInfo.cpp | 572 "Unexpected InReg seen in arginfo in generic VAArg emitter!");
924 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1430 bool &InReg,
1439 InReg = !IsMCUABI;
1523 bool InReg; local
1524 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1528 if (InReg)
1572 bool InReg = shouldPrimitiveUseInReg(Ty, State); local
1575 if (InReg)
1580 if (InReg)
1429 shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg, bool &NeedsPadding) const argument
[all...] |
| H A D | CGCall.cpp | 1815 RetAttrs.addAttribute(llvm::Attribute::InReg);
1858 SRETAttrs.addAttribute(llvm::Attribute::InReg);
1884 llvm::Attribute::InReg));
1905 Attrs.addAttribute(llvm::Attribute::InReg);
1910 Attrs.addAttribute(llvm::Attribute::InReg);
|
| /external/llvm/lib/IR/ |
| H A D | Attributes.cpp | 253 if (hasAttribute(Attribute::InReg))
477 case Attribute::InReg: return 1 << 3;
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86WinEHState.cpp | 415 Call->addAttribute(1, Attribute::InReg);
|
| H A D | X86FastISel.cpp | 2916 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3000 CS->paramHasAttr(1, Attribute::InReg) || Subtarget->isTargetMCU())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 85 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
864 Attrs.push_back(Attribute::InReg);
|
| H A D | SelectionDAGBuilder.cpp | 1041 unsigned InReg = It->second;
1043 DAG.getDataLayout(), InReg, Ty);
1231 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1232 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1454 Attribute::InReg);
2065 if (Fn->hasAttribute(1, Attribute::AttrKind::InReg))
7471 Attrs.push_back(Attribute::InReg);
7876 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 984 unsigned InReg = It->second; local
985 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
1122 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); local
1123 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1199 if (F->paramHasAttr(0, Attribute::InReg))
5191 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5236 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
6580 if (F.paramHasAttr(Idx, Attribute::InReg))
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1592 if (CS.paramHasAttr(AttrInd, Attribute::InReg))
1859 if (CS.paramHasAttr(0, Attribute::InReg))
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringARM32.cpp | 3701 bool InReg = false;
3704 InReg = CC.argInGPR(Ty, &Reg);
3706 InReg = CC.argInVFP(Ty, &Reg);
3709 if (!InReg) {
|
| H A D | IceTargetLoweringMIPS32.cpp | 3390 bool InReg = false; local
3393 InReg = CC.argInReg(Ty, i, &Reg);
3395 if (!InReg) {
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2342 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
3011 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
|
| /external/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1601 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
|