/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | hsw_queryobj.c | 43 MI_MATH_ALU2(LOAD, SRCA, R0), 44 MI_MATH_ALU2(LOAD, SRCB, R0), 47 MI_MATH_ALU2(LOAD, SRCA, R1), 48 MI_MATH_ALU2(LOAD, SRCB, R1), 51 MI_MATH_ALU2(LOAD, SRCA, R1), 52 MI_MATH_ALU2(LOAD, SRCB, R1), 55 MI_MATH_ALU2(LOAD, SRCA, R1), 56 MI_MATH_ALU2(LOAD, SRCB, R1), 60 MI_MATH_ALU2(LOAD, SRCA, R1), 61 MI_MATH_ALU2(LOAD, SRC [all...] |
H A D | hsw_sol.c | 110 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); 111 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); 115 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); 116 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); 132 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); 133 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); 141 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); 142 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); 145 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); 146 OUT_BATCH(MI_MATH_ALU2(LOAD, SRC [all...] |
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/ |
H A D | streamout_jit.cpp | 52 return LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_pBuffer, buffer }); 67 Value* enabled = TRUNC(LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_enable }), IRB()->getInt1Ty()); 70 Value* bufferSize = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_bufferSize }); 73 Value* streamOffset = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_streamOffset }); 76 Value* pitch = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_pitch }); 151 Value *vattrib = LOAD(pAttrib); 194 Value *numPrimStorageNeeded = LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimStorageNeeded }); 213 Value* numPrimsWritten = LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimsWritten }); 224 Value* pData = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_pBuffer }); 225 Value* streamOffset = LOAD(pBu [all...] |
H A D | fetch_jit.cpp | 120 Value* streams = LOAD(mpFetchInfo,{0, SWR_FETCH_CONTEXT_pStreams}); 124 Value* indices = LOAD(mpFetchInfo,{0, SWR_FETCH_CONTEXT_pIndices}); 128 Value* pLastIndex = LOAD(mpFetchInfo,{0, SWR_FETCH_CONTEXT_pLastIndex}); 138 vIndices = LOAD(BITCAST(indices, PointerType::get(VectorType::get(mInt8Ty, mpJitMgr->mVWidth), 0)), {(uint32_t)0}); 149 vIndices = LOAD(BITCAST(indices, PointerType::get(VectorType::get(mInt16Ty, mpJitMgr->mVWidth), 0)), {(uint32_t)0}); 158 (fetchState.bDisableIndexOOBCheck) ? vIndices = LOAD(BITCAST(indices, PointerType::get(mSimdInt32Ty,0)),{(uint32_t)0}) 168 Value* vBaseVertex = VBROADCAST(LOAD(mpFetchInfo, { 0, SWR_FETCH_CONTEXT_BaseVertex })); 169 Value* vStartVertex = VBROADCAST(LOAD(mpFetchInfo, { 0, SWR_FETCH_CONTEXT_StartVertex })); 251 Value* startVertex = LOAD(mpFetchInfo, {0, SWR_FETCH_CONTEXT_StartVertex}); 252 Value* startInstance = LOAD(mpFetchInf [all...] |
H A D | blend_jit.cpp | 449 Value* pRef = VBROADCAST(LOAD(pBlendState, { 0, SWR_BLEND_STATE_alphaTestReference })); 452 Value* pAlpha = LOAD(ppAlpha); 500 Value* pMask = LOAD(ppMask); 574 dst[i] = LOAD(pDst, { i }); 577 constantColor[i] = VBROADCAST(LOAD(pBlendState, { 0, SWR_BLEND_STATE_constantColor, i })); 580 src[i] = LOAD(pSrc, { i }); 583 src1[i] = LOAD(pSrc1, { i }); 754 Value* oMask = LOAD(ppoMask); 762 Value* sampleMask = LOAD(pBlendState, { 0, SWR_BLEND_STATE_sampleMask}); 780 Value* pMask = LOAD(ppMas [all...] |
H A D | builder_misc.cpp | 287 LoadInst *Builder::LOAD(Value *basePtr, const std::initializer_list<uint32_t> &indices, const llvm::Twine& name) function in class:SwrJit::Builder 292 return LOAD(GEPA(basePtr, valIndices), name); 300 return LOAD(GEPA(basePtr, valIndices), name); 575 Value *val = LOAD(validAddress); 625 Value *val = LOAD(validAddress, C(0)); 675 Value *val = LOAD(validAddress);
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/external/mesa3d/src/gallium/drivers/swr/ |
H A D | swr_shader.cpp | 222 Value *vtxInput = LOAD(pVsCtx, {0, SWR_VS_CONTEXT_pVin}); 229 wrap(LOAD(vtxInput, {0, 0, attrib, channel})); 239 system_values.instance_id = wrap(LOAD(pVsCtx, {0, SWR_VS_CONTEXT_InstanceID})); 240 system_values.vertex_id = wrap(LOAD(pVsCtx, {0, SWR_VS_CONTEXT_VertexID})); 261 Value *vtxOutput = LOAD(pVsCtx, {0, SWR_VS_CONTEXT_pVout}); 268 Value *val = LOAD(unwrap(outputs[attrib][channel])); 318 Value *px = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 0})); 319 Value *py = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 1})); 320 Value *pz = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 2})); 321 Value *pw = LOAD(GE [all...] |
/external/mesa3d/src/compiler/nir/ |
H A D | nir_intrinsics.h | 392 #define LOAD(name, srcs, num_indices, idx0, idx1, idx2, flags) \ macro 396 LOAD(uniform, 1, 2, BASE, RANGE, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) 398 LOAD(ubo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) 400 LOAD(input, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) 402 LOAD(per_vertex_input, 2, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) 409 LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE) 411 LOAD(output, 1, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE) 413 LOAD(per_vertex_output, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE) 415 LOAD(shared, 1, 1, BASE, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE) 417 LOAD(push_constan [all...] |
/external/libevent/ |
H A D | evthread_win32.c | 112 #define LOAD(name) \ macro 114 LOAD(InitializeConditionVariable); 115 LOAD(SleepConditionVariableCS); 116 LOAD(WakeAllConditionVariable); 117 LOAD(WakeConditionVariable);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | SlotIndexes.cpp | 79 SlotIndex blockStartIndex(back(), SlotIndex::LOAD); member in class:SlotIndex 91 mi2iMap.insert(std::make_pair(mi, SlotIndex(back(), SlotIndex::LOAD))); 100 MBBRanges[mbb->getNumber()].second = SlotIndex(back(), SlotIndex::LOAD);
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/external/elfutils/libebl/ |
H A D | eblsegmenttypename.c | 50 PTYPE (LOAD),
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/external/v8/src/compiler/ |
H A D | machine-operator.cc | 458 #define LOAD(Type) \ macro 494 MACHINE_TYPE_LIST(LOAD) 495 #undef LOAD macro 651 #define LOAD(Type) \ macro 655 MACHINE_TYPE_LIST(LOAD) 656 #undef LOAD macro 700 #define LOAD(Type) \ macro 704 MACHINE_TYPE_LIST(LOAD) 705 #undef LOAD macro 711 #define LOAD(Typ macro 716 #undef LOAD macro 804 #define LOAD macro 809 #undef LOAD macro 835 #define LOAD macro 840 #undef LOAD macro [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | SlotIndexes.h | 86 enum Slot { LOAD, USE, DEF, STORE, NUM }; enumerator in enum:llvm::SlotIndex::Slot 194 /// isLoad - Return true if this is a LOAD slot. 196 return getSlot() == LOAD; 215 /// is the one associated with the LOAD slot for the instruction pointed to 222 /// index is the one associated with the LOAD slot for the instruction 228 /// Returns the index of the LOAD slot for the instruction pointed to by 231 return SlotIndex(&entry(), SlotIndex::LOAD); 261 return SlotIndex(entry().getNext(), SlotIndex::LOAD); 274 /// index is a LOAD, the last slot for the previous instruction. 280 if (s == SlotIndex::LOAD) { [all...] |
H A D | ISDOpcodes.h | 454 // LOAD and STORE have token chains as their first operand, then the same 458 LOAD, STORE, enumerator in enum:llvm::ISD::NodeType
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/external/freetype/src/gzip/ |
H A D | infutil.h | 85 #define LOAD {LOADIN LOADOUT} macro
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H A D | infcodes.c | 98 LOAD 109 LOAD
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H A D | infblock.c | 133 LOAD 344 LOAD
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelDAGToDAG.cpp | 223 case ISD::LOAD:
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/external/libavc/encoder/arm/ |
H A D | ime_distortion_metrics_a9q.s | 589 vld1.8 {d2, d3}, [r5], r10 @ y top LOAD 590 vld1.8 {d4, d5}, [r7], r10 @ xy top LOAD 591 vld1.8 {d6, d7}, [r8], r10 @ xy top-left LOAD 595 vld1.8 {d8, d9}, [r1], r10 @ x LOAD 598 vld1.8 {d10, d11}, [r4], r10 @ x left LOAD 602 vld1.8 {d2, d3}, [r2], r10 @ y LOAD 605 vld1.8 {d4, d5}, [r3], r10 @ xy LOAD 609 vld1.8 {d6, d7}, [r6], r10 @ xy left LOAD 624 vld1.8 {d8, d9}, [r1], r10 @ x LOAD 627 vld1.8 {d10, d11}, [r4], r10 @ x left LOAD [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 353 if (N1.getOpcode() == ISD::LOAD && 413 case ISD::LOAD:
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 356 if (N1.getOpcode() == ISD::LOAD && 413 case ISD::LOAD:
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/external/autotest/client/site_tests/platform_ToolchainOptions/ |
H A D | platform_ToolchainOptions.py | 270 # Verify all binaries have W^X LOAD program headers. 272 "grep \"LOAD\" | egrep -v \"(RW |R E)\" | " 275 option_sets.append(self.create_and_filter("LOAD Writable and Exec",
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 540 /// LOAD and STORE have token chains as their first operand, then the same 544 LOAD, STORE, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 71 setOperationAction(ISD::LOAD, MVT::f32, Promote); 72 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); 74 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 75 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); 77 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); 78 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); 80 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); 81 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); 83 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); 84 AddPromotedToType(ISD::LOAD, MV [all...] |
/external/pdfium/third_party/zlib_v128/ |
H A D | infback.c | 128 #define LOAD() \ macro 488 LOAD();
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