Searched refs:LW (Results 1 - 25 of 35) sorted by relevance

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/external/python/cpython2/Modules/_ctypes/libffi/src/tile/
H A Dtile.S48 #define LW ld define
52 #define LW lw define
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r10
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsEmitGPRestore.cpp67 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
80 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
H A DMipsInstrInfo.cpp53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
201 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
/external/libyuv/files/include/libyuv/
H A Dmacros_msa.h19 #define LW(psrc) \ macro
45 val0_m = LW(psrc_ld_m); \
46 val1_m = LW(psrc_ld_m + 4); \
84 #define LW(psrc) \ macro
110 val0_m = LW(psrc_ld_m); \
111 val1_m = LW(psrc_ld_m + 4); \
/external/libpng/mips/
H A Dfilter_msa_intrinsics.c44 #define LW(psrc) \ macro
115 #define LW(psrc) \ macro
183 #define LW(psrc) \ macro
471 inp0 = LW(src);
512 inp0 = LW(src);
553 inp0 = LW(pp);
555 inp1 = LW(src);
608 inp0 = LW(pp);
610 inp1 = LW(src);
669 inp0 = LW(nx
[all...]
/external/clang/utils/ABITest/
H A DEnumeration.py150 LW,RW = W//2, W - (W//2)
151 L,R = getNthPairBounded(N, H**LW, H**RW)
152 return (getNthNTuple(L,LW,H=H,useLeftToRight=useLeftToRight) +
/external/libvpx/libvpx/vpx_dsp/mips/
H A Dintrapred_msa.c24 src_data = LW(src);
34 src_data1 = LW(src);
35 src_data2 = LW(src + 4);
162 val0 = LW(src_top);
163 val1 = LW(src_left);
182 val0 = LW(src);
394 val = LW(src_top_ptr);
H A Dmacros_msa.h54 #define LW(psrc) \ macro
87 val0_m = LW(psrc_m); \
88 val1_m = LW(psrc_m + 4); \
144 #define LW(psrc) \ macro
177 val0_m = LW(psrc_m1); \
178 val1_m = LW(psrc_m1 + 4); \
233 out0 = LW((psrc)); \
234 out1 = LW((psrc) + stride); \
235 out2 = LW((psrc) + 2 * stride); \
236 out3 = LW((psr
[all...]
H A Dvpx_convolve_copy_msa.c214 tmp = LW(src);
/external/libyuv/files/source/
H A Dscale_msa.cc109 data0 = LW(src_argb);
110 data1 = LW(src_argb + stepx);
111 data2 = LW(src_argb + stepx * 2);
112 data3 = LW(src_argb + stepx * 3);
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp216 case Mips::LW:
H A DMipsTargetStreamer.cpp225 emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
1059 // and adds a corresponding LW after every JAL.
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
266 Opc = Mips::LW;
292 Opc = Mips::LW;
296 Opc = Mips::LW;
H A DMipsLongBranch.cpp332 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
H A DMipsFastISel.cpp375 emitInst(Mips::LW, DestReg)
392 emitInst(Mips::LW, DestReg)
726 Opc = Mips::LW;
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp239 SDValue Load = SDValue(CurDAG->getMachineNode(MBlaze::LW, dl,
/external/libvpx/libvpx/vp8/common/mips/msa/
H A Dvp8_macros_msa.h43 #define LW(psrc) \ macro
76 val0_m = LW(psrc_m); \
77 val1_m = LW(psrc_m + 4); \
120 #define LW(psrc) \ macro
153 val0_m = LW(psrc_m1); \
154 val1_m = LW(psrc_m1 + 4); \
208 out0 = LW((psrc)); \
209 out1 = LW((psrc) + stride); \
210 out2 = LW((psrc) + 2 * stride); \
211 out3 = LW((psr
[all...]
/external/webp/src/dsp/
H A Dmsa_macro.h99 #define LW(psrc) MSA_LOAD(psrc, msa_lw) macro
118 #define LW(psrc) MSA_LOAD(psrc, msa_ulw) macro
150 out0 = LW(ptmp); \
152 out1 = LW(ptmp); \
154 out2 = LW(ptmp); \
156 out3 = LW(ptmp); \
H A Ddec_msa.c708 const uint32_t val0 = LW(ptop + 0);
709 const uint32_t val1 = LW(ptop + 4);
725 uint32_t val0 = LW(ptop + 0);
726 uint32_t val1 = LW(ptop + 4);
753 uint32_t val0 = LW(ptop + 0);
754 uint32_t val1 = LW(ptop + 4);
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp56 MBlaze::LBU, MBlaze::LHU, MBlaze::LW, UNSUPPORTED, //30,31,32,33
374 case 0x0: return MBlaze::LW;
475 case MBlaze::LW: return decodeLW(insn);
/external/v8/src/mips/
H A Dassembler-mips.cc272 LW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT
275 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
280 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
656 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
670 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
1879 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1882 GenInstrImmediate(LW, at, rd, off16);
2255 GenInstrImmediate(LW, src.rm(), at,
2261 GenInstrImmediate(LW, at, at, off16 + Register::kExponentOffset);
H A Dconstants-mips.h375 LW = ((4U << 3) + 3) << kOpcodeShift,
915 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
/external/v8/src/mips64/
H A Dconstants-mips64.h350 LW = ((4U << 3) + 3) << kOpcodeShift,
947 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
H A Dassembler-mips64.cc256 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
261 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
628 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
642 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
2042 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
2045 GenInstrImmediate(LW, at, rd, off16);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1674 TOut.emitRRX(Mips::LW, Mips::T9, Mips::GP,
1687 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9,
1699 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1914 // We need a NOP between the JALR and the LW:
2387 TOut.emitRRX(Mips::LW, DstReg, ABI.GetGlobalPtr(),
2427 TOut.emitRRX(Mips::LW, TmpReg, ABI.GetGlobalPtr(),

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