| /external/clang/include/clang/AST/ |
| H A D | StmtIterator.h | 65 void NextVA();
93 NextVA();
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| /external/clang/lib/AST/ |
| H A D | StmtIterator.cpp | 33 void StmtIteratorBase::NextVA() { function in class:StmtIteratorBase
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 389 CCValAssign &VA, CCValAssign &NextVA,
393 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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| H A D | ARMFastISel.cpp | 1643 CCValAssign &NextVA = ArgLocs[++i];
1646 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1650 .addReg(NextVA.getLocReg(), RegState::Define)
1653 RegArgs.push_back(NextVA.getLocReg());
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| H A D | ARMISelLowering.cpp | 1190 CCValAssign &VA, CCValAssign &NextVA,
1199 if (NextVA.isRegLoc())
1200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1202 assert(NextVA.isMemLoc());
1207 dl, DAG, NextVA,
2363 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, argument
2380 if (NextVA.isMemLoc()) {
2382 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2390 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1187 PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVector<SDValue, 8> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 191 CCValAssign &NextVA = ArgLocs[++i]; local
194 if (NextVA.isMemLoc()) {
196 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
202 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
481 CCValAssign &NextVA = ArgLocs[++i]; local
482 if (NextVA.isRegLoc()) {
483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
486 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 511 CCValAssign &VA, CCValAssign &NextVA,
515 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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| H A D | ARMFastISel.cpp | 1984 CCValAssign &NextVA = ArgLocs[++i]; local
1986 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1991 .addReg(NextVA.getLocReg(), RegState::Define)
1994 RegArgs.push_back(NextVA.getLocReg());
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| H A D | ARMISelLowering.cpp | 1547 CCValAssign &VA, CCValAssign &NextVA,
1557 if (NextVA.isRegLoc())
1558 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1560 assert(NextVA.isMemLoc());
1566 dl, DAG, NextVA,
3074 CCValAssign &NextVA,
3092 if (NextVA.isMemLoc()) {
3094 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3103 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1544 PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
3073 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &dl) const argument
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 424 CCValAssign &NextVA = ArgLocs[++i]; local
427 if (NextVA.isMemLoc()) {
429 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
435 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
877 CCValAssign &NextVA = ArgLocs[++i]; local
878 if (NextVA.isRegLoc()) {
879 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
882 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
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