Searched refs:OrigVT (Results 1 - 9 of 9) sorted by relevance

/external/llvm/include/llvm/Target/
H A DTargetLowering.h1494 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1498 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1499 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1504 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1505 setOperationAction(Opc, OrigVT, Promote);
1506 AddPromotedToType(Opc, OrigVT, DestVT);
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetLowering.h1116 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1120 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1121 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4117 EVT OrigVT = Op.getOperand(0).getValueType();
4118 if (OrigVT.getSizeInBits() <= OptSize) {
4123 EVT OrigVT = Op.getOperand(0).getValueType();
4124 if (OrigVT.getSizeInBits() <= OptSize) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp262 EVT OrigVT = VT; local
269 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
270 TLI.ShouldShrinkFPConstant(OrigVT)) {
283 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
289 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2751 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, argument
2784 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2785 Align = OrigVT.getStoreSize();
2797 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, argument
2809 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3202 EVT OrigVT = Ins[ArgNo].ArgVT; local
3216 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
5055 EVT OrigVT = Outs[i].ArgVT; local
5104 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5170 EVT OrigVT local
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp354 EVT OrigVT = VT; local
362 TLI.ShouldShrinkFPConstant(OrigVT)) {
373 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
377 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2089 static EVT getExtensionTo64Bits(const EVT &OrigVT) { argument
2090 if (OrigVT.getSizeInBits() >= 64)
2091 return OrigVT;
2093 assert(OrigVT.isSimple() && "Expecting a simple value type");
2095 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6507 static EVT getExtensionTo64Bits(const EVT &OrigVT) { argument
6508 if (OrigVT.getSizeInBits() >= 64)
6509 return OrigVT;
6511 assert(OrigVT.isSimple() && "Expecting a simple value type");
6513 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp10488 MVT OrigVT = V.getSimpleValueType();
10489 int OrigNumElements = OrigVT.getVectorNumElements();
10491 MVT OrigScalarVT = OrigVT.getVectorElementType();
30877 MVT OrigVT = OrigV.getSimpleValueType(); local
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