/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 351 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, local 354 if (ResultReg == 0) return false; 357 UpdateValueMap(I, ResultReg); 380 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, local 382 if (ResultReg == 0) return false; 385 UpdateValueMap(I, ResultReg); 391 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), local 393 if (ResultReg != 0) { 395 UpdateValueMap(I, ResultReg); 408 unsigned ResultReg local 593 unsigned ResultReg = createResultReg(RC); local 617 unsigned ResultReg = createResultReg(RC); local 642 unsigned ResultReg = getRegForValue(ResCI); local 688 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), local 727 unsigned ResultReg = 0; local 803 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), local 857 unsigned ResultReg; local 1082 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); local 1104 unsigned ResultReg = createResultReg(RC); local 1114 unsigned ResultReg = createResultReg(RC); local 1134 unsigned ResultReg = createResultReg(RC); local 1156 unsigned ResultReg = createResultReg(RC); local 1179 unsigned ResultReg = createResultReg(RC); local 1200 unsigned ResultReg = createResultReg(RC); local 1223 unsigned ResultReg = createResultReg(RC); local 1245 unsigned ResultReg = createResultReg(RC); local 1267 unsigned ResultReg = createResultReg(RC); local 1283 unsigned ResultReg = createResultReg(RC); local 1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local 325 ResultReg) 329 return ResultReg; 346 unsigned ResultReg = createResultReg(RC); local 348 ResultReg).addReg(ZeroReg, getKillRegState(true)); 349 return ResultReg; 383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local 385 TII.get(TargetOpcode::COPY), ResultReg) 388 return ResultReg; 403 unsigned ResultReg local 427 unsigned ResultReg; local 977 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local 988 unsigned ResultReg = 0; local 1026 unsigned ResultReg; local 1133 unsigned ResultReg = 0; local 1254 unsigned ResultReg; local 1299 unsigned ResultReg; local 1339 unsigned ResultReg; local 1382 unsigned ResultReg; local 1480 unsigned ResultReg; local 1542 unsigned ResultReg = 0; local 1640 unsigned ResultReg = local 1683 unsigned ResultReg = local 1809 unsigned ResultReg = createResultReg(RC); local 1843 unsigned ResultReg; local 1869 unsigned ResultReg; local 1938 unsigned ResultReg = local 2446 unsigned ResultReg = 0; local 2572 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, local 2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, local 2717 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); local 2733 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); local 2766 unsigned ResultReg = createResultReg( local 2814 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, local 2922 unsigned ResultReg = createResultReg(RC); local 3047 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local 3220 unsigned ResultReg = emitLoad(VT, VT, Src); local 3484 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local 3507 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); local 3801 unsigned ResultReg; local 3844 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); local 3927 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local 3955 unsigned ResultReg = createResultReg(RC); local 4034 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local 4062 unsigned ResultReg = createResultReg(RC); local 4155 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local 4183 unsigned ResultReg = createResultReg(RC); local 4431 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); local 4452 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); local 4499 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true, local 4551 unsigned ResultReg = local 4570 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); local 4588 unsigned ResultReg = 0; local 4647 unsigned ResultReg = 0; local 4700 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); local 4767 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); local 4801 unsigned ResultReg; local [all...] |
H A D | AArch64InstrInfo.cpp | 3289 unsigned ResultReg = Root.getOperand(0).getReg(); local 3297 if (TargetRegisterInfo::isVirtualRegister(ResultReg)) 3298 MRI.constrainRegClass(ResultReg, RC); 3308 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) 3313 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) 3319 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) 3353 unsigned ResultReg = Root.getOperand(0).getReg(); local 3359 if (TargetRegisterInfo::isVirtualRegister(ResultReg)) 3360 MRI.constrainRegClass(ResultReg, RC); 3369 ResultReg) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 414 unsigned ResultReg = local 417 if (!ResultReg) 421 updateValueMap(I, ResultReg); 448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, local 450 if (!ResultReg) 454 updateValueMap(I, ResultReg); 460 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), local 462 if (ResultReg) { 464 updateValueMap(I, ResultReg); 475 unsigned ResultReg local 1222 unsigned ResultReg = getRegForValue(ResCI); local 1229 unsigned ResultReg = getRegForValue(II->getArgOperand(0)); local 1269 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), local 1304 unsigned ResultReg = 0; local 1485 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, local 1538 unsigned ResultReg; local 1761 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); local 1808 unsigned ResultReg = createResultReg(RC); local 1820 unsigned ResultReg = createResultReg(RC); local 1842 unsigned ResultReg = createResultReg(RC); local 1867 unsigned ResultReg = createResultReg(RC); local 1893 unsigned ResultReg = createResultReg(RC); local 1916 unsigned ResultReg = createResultReg(RC); local 1940 unsigned ResultReg = createResultReg(RC); local 1960 unsigned ResultReg = createResultReg(RC); local 1982 unsigned ResultReg = createResultReg(RC); local 1998 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 89 unsigned &ResultReg, unsigned Alignment = 1); 98 unsigned &ResultReg); 349 MachineMemOperand *MMO, unsigned &ResultReg, 488 ResultReg = createResultReg(RC); 490 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); 697 unsigned &ResultReg) { 703 ResultReg = RR; 1319 unsigned ResultReg = 0; local 1320 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, 1324 updateValueMap(I, ResultReg); 348 X86FastEmitLoad(EVT VT, X86AddressMode &AM, MachineMemOperand *MMO, unsigned &ResultReg, unsigned Alignment) argument 695 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 1420 unsigned ResultReg = 0; local 1510 unsigned ResultReg = getRegForValue(I->getOperand(0)); local 1763 unsigned ResultReg = createResultReg(RC); local 1906 unsigned ResultReg = 0; local 2045 unsigned ResultReg = fastEmitInst_rr(Opc, RC, RHSReg, RHSIsKill, local 2123 unsigned ResultReg; local 2218 unsigned ResultReg = local 2245 unsigned ResultReg = createResultReg(RC); local 2302 unsigned ResultReg = local 2320 unsigned ResultReg = createResultReg(RC); local 2388 unsigned ResultReg = fastEmitInst_extractsubreg(MVT::i8, local 2461 unsigned ResultReg = 0; local 2679 unsigned ResultReg = createResultReg(RC); local 2750 unsigned ResultReg = 0; local 2880 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local 2978 unsigned ResultReg = createResultReg(RC); local 3080 unsigned ResultReg; local 3352 unsigned ResultReg = FuncInfo.CreateRegs(CLI.RetTy); local 3498 unsigned ResultReg = createResultReg(&X86::GR64RegClass); local 3526 unsigned ResultReg = createResultReg(&X86::GR64RegClass); local 3591 unsigned ResultReg = createResultReg(RC); local 3628 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local 3687 unsigned ResultReg = createResultReg(RC); local 3726 unsigned ResultReg = createResultReg(RC); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 133 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 279 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local 280 if (!ResultReg) 283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); 284 return ResultReg; 298 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local 300 ResultReg) 303 return ResultReg; 319 unsigned ResultReg = createResultReg(RC); local 323 emitInst(Opc, ResultReg) 595 emitCmp(unsigned ResultReg, const CmpInst *CI) argument 717 emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment) argument 835 unsigned ResultReg; local 872 unsigned ResultReg; local 940 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local 1008 unsigned ResultReg = createResultReg(RC); local 1238 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local 1568 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local 1692 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local 1711 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local 1877 unsigned ResultReg = createResultReg(RC); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr); 190 unsigned &ResultReg); 280 unsigned ResultReg = createResultReg(RC); local 283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); 284 return ResultReg; 290 unsigned ResultReg = createResultReg(RC); local 294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 300 TII.get(TargetOpcode::COPY), ResultReg) 303 return ResultReg; 310 unsigned ResultReg local 333 unsigned ResultReg = createResultReg(RC); local 357 unsigned ResultReg = createResultReg(RC); local 379 unsigned ResultReg = createResultReg(RC); local 402 unsigned ResultReg = createResultReg(RC); local 425 unsigned ResultReg = createResultReg(RC); local 444 unsigned ResultReg = createResultReg(RC); local 464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local 673 unsigned ResultReg = createResultReg(RC); local 859 unsigned ResultReg = createResultReg(RC); local 917 ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) argument 971 unsigned ResultReg; local 1350 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); local 1377 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); local 1410 unsigned ResultReg = createResultReg(RC); local 1501 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local 1511 FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 1689 unsigned ResultReg = createResultReg(DstRC); local 1705 unsigned ResultReg = createResultReg(DstRC); local [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 516 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); local 518 TII.get(WebAssembly::COPY), ResultReg) 520 return ResultReg; 528 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? local 534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 536 return ResultReg; 544 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? local 550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 552 return ResultReg; 606 unsigned ResultReg local 638 unsigned ResultReg; local 761 unsigned ResultReg = createResultReg(RC); local 870 unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass); local 931 unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass); local 1016 unsigned ResultReg = createResultReg(RC); local 1074 unsigned ResultReg = createResultReg(RC); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86FastISel.cpp | 87 unsigned &ResultReg); 177 unsigned &ResultReg) { 224 ResultReg = createResultReg(RC); 226 DL, TII.get(Opc), ResultReg), AM); 312 unsigned &ResultReg) { 317 ResultReg = RR; 811 unsigned ResultReg = 0; local 812 if (X86FastEmitLoad(VT, AM, ResultReg)) { 813 UpdateValueMap(I, ResultReg); 896 unsigned ResultReg local 176 X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &ResultReg) argument 310 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 976 unsigned ResultReg = getRegForValue(I->getOperand(0)); local 1188 unsigned ResultReg = createResultReg(RC); local 1227 unsigned ResultReg = createResultReg(RC); local 1242 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); local 1261 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); local 1307 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, local 1469 unsigned ResultReg = FuncInfo.CreateRegs(I.getType()); local 1870 unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); local 2030 unsigned ResultReg = createResultReg(RC); local 2061 unsigned ResultReg = createResultReg(RC); local 2085 unsigned ResultReg = createResultReg(RC); local 2124 unsigned ResultReg = createResultReg(RC); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 157 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 443 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local 445 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); 446 Addr.Base.Reg = ResultReg; 462 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, argument 468 // If ResultReg is given, it determines the register class of the load. 476 (ResultReg ? MRI.getRegClass(ResultReg) : 524 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg); 612 unsigned ResultReg = 0; local 989 unsigned ResultReg = 0; local 1098 unsigned ResultReg = 0; local 1203 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); local 1421 unsigned ResultReg = 0; local 1800 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass); local 1841 unsigned ResultReg = createResultReg(RC); local 2011 unsigned ResultReg = createResultReg(RC); local 2083 unsigned ResultReg = createResultReg(RC); local 2166 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local 2244 unsigned ResultReg = MI->getOperand(0).getReg(); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 281 unsigned ResultReg = createResultReg(RC); local 289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); 294 TII.get(TargetOpcode::COPY), ResultReg) 297 return ResultReg; 304 unsigned ResultReg = createResultReg(RC); local 314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) 322 TII.get(TargetOpcode::COPY), ResultReg) 325 return ResultReg; 332 unsigned ResultReg local 359 unsigned ResultReg = createResultReg(RC); local 387 unsigned ResultReg = createResultReg(RC); local 507 unsigned ResultReg = 0; local 680 unsigned ResultReg = createResultReg(RC); local 855 unsigned ResultReg = createResultReg(RC); local 919 ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument 1050 unsigned ResultReg; local 1571 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); local 1597 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); local 1663 unsigned ResultReg = createResultReg(RC); local 1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local 1814 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); local 2037 unsigned ResultReg = createResultReg(DstRC); local 2058 unsigned ResultReg = createResultReg(DstRC); local 2455 unsigned ResultReg; local 2684 unsigned ResultReg; local 2740 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); local 2782 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local 2927 unsigned ResultReg = MI->getOperand(0).getReg(); local 3048 unsigned ResultReg = createResultReg(RC); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 80 unsigned ResultReg; member in struct:llvm::FastISel::CallLoweringInfo 96 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {}
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 2682 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2688 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) 2692 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2693 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2833 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2846 BuildMI(MBB, MII, DL, InstDesc, ResultReg) 2850 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2854 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2878 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 2889 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) [all...] |