| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 334 unsigned ShiftImm; // shift for OffsetReg. member in struct:__anon20007::ARMOperand::__anon20008::__anon20021
344 unsigned ShiftImm; member in struct:__anon20007::ARMOperand::__anon20008::__anon20022
355 unsigned ShiftImm; member in struct:__anon20007::ARMOperand::__anon20008::__anon20024
360 unsigned ShiftImm; member in struct:__anon20007::ARMOperand::__anon20008::__anon20025
746 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
763 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
974 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
982 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1176 Memory.ShiftImm, Memory.ShiftType);
1326 Memory.ShiftImm, Memor
1505 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
1520 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
1607 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E) argument
1628 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2716 unsigned ShiftImm = 0; local
3246 unsigned ShiftImm = 0; local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 170 uint64_t ShiftImm, bool SetFlags = false,
175 uint64_t ShiftImm, bool SetFlags = false,
201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
209 uint64_t ShiftImm);
1277 unsigned ShiftImm; local
1279 ShiftImm = 0;
1281 ShiftImm = 12;
1310 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1318 uint64_t ShiftImm, bool SetFlags,
1326 if (ShiftImm >
1314 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1355 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1510 emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1650 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) argument
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 1526 uint64_t ShiftImm; local
1527 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1528 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1532 if (ShiftImm + Width > BitWidth)
1537 Immr = ShiftImm;
1538 Imms = ShiftImm + Width - 1;
1550 // SRL Value2, ShiftImm
1552 // with MaskImm >> ShiftImm to search for the bit width.
1556 // UBFM Value, ShiftImm, BitWide + SrlImm -1
1662 uint64_t ShiftImm;
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 516 unsigned ShiftImm; // shift for OffsetReg. member in struct:__anon13040::ARMOperand::MemoryOp
526 unsigned ShiftImm; member in struct:__anon13040::ARMOperand::PostIdxRegOp
538 unsigned ShiftImm; member in struct:__anon13040::ARMOperand::RegShiftedRegOp
544 unsigned ShiftImm; member in struct:__anon13040::ARMOperand::RegShiftedImmOp
1254 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1271 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1817 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2131 Memory.ShiftImm, Memor
2649 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2663 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2803 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) argument
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
4667 unsigned ShiftImm = 0; local
4993 unsigned ShiftImm = 0; local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1083 int64_t ShiftImm = (Size == 1) ? 24 : 16; local
1090 .addReg(SrlRes).addImm(ShiftImm);
1092 .addReg(SllRes).addImm(ShiftImm);
1294 int64_t ShiftImm = (Size == 1) ? 24 : 16; local
1299 .addReg(SrlRes).addImm(ShiftImm);
1301 .addReg(SllRes).addImm(ShiftImm);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2759 unsigned ShiftImm; local
2762 ShiftImm = CI->getZExtValue();
2766 if (ShiftImm == 0 || ShiftImm >=32)
2790 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1218 int64_t ShiftImm = 32 - (Size * 8);
1220 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1221 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
|